PCIe device, link training method, chip and electronic device

Abstract

The application discloses a PCIe device, a link training method, a chip and an electronic device, and belongs to the technical field of electronics. The PCIe device comprises a first memory, a processor and a link training module, and the PCIe device is connected with a second memory. The processor reads first configuration information from the first memory and sends the first configuration information to the link training module, and reads second configuration information from the second memory and sends the second configuration information to the link training module. The link training module performs link training on a transmission link based on the first configuration information and the second configuration information, so as to realize configuration of a transmission rate of the transmission link based on the first configuration information and improvement of the transmission rate of the transmission link based on the second configuration information, thereby enabling the transmission rate of the transmission link to meet the demand of actual application.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a PCIe device, a link training method, a chip, and an electronic device. Background Technology

[0002] With the development of electronic technology, the requirements for the transmission rate of PCIe (Peripheral Component Interconnect Express) devices are becoming increasingly stringent. Typically, PCIe devices need to perform link training on the transmission link to ensure that the transmission rate reaches the desired level. Therefore, how to perform link training on the transmission link for PCIe devices has become a pressing issue that needs to be addressed. Summary of the Invention

[0003] This application provides a PCIe device, a link training method, a chip, and an electronic device, which can perform link training on a transmission link based on first configuration information and second configuration information, thereby improving the transmission rate of the transmission link. The technical solution includes the following:

[0004] On one hand, a PCIe device is provided, the PCIe device including a first memory, a processor and a link training module, the PCIe device being connected to a second memory, the first memory being used to store first configuration information, the second memory being used to store second configuration information, the first configuration information being used to configure the transmission link to a first transmission rate, and the second configuration information being used to increase the transmission link to a second transmission rate from the first transmission rate.

[0005] The processor is configured to read the first configuration information from the first memory and send the first configuration information to the link training module;

[0006] The processor is further configured to read second configuration information from the second memory and send the second configuration information to the link training module;

[0007] The link training module is used to receive the first configuration information and the second configuration information, and to perform link training on the transmission link based on the first configuration information and the second configuration information.

[0008] On the other hand, a link training method is provided, the method being executed by a PCIe device. The PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The first memory stores first configuration information, and the second memory stores second configuration information. The first configuration information configures the transmission link's transmission rate to a first transmission rate, and the second configuration information increases the transmission link's transmission rate from the first transmission rate to a second transmission rate. The method includes:

[0009] The processor reads the first configuration information from the first memory and sends the first configuration information to the link training module.

[0010] The processor reads the second configuration information from the second memory and sends the second configuration information to the link training module.

[0011] The link training module receives the first configuration information and the second configuration information, and performs link training on the transmission link based on the first configuration information and the second configuration information.

[0012] On the other hand, a chip is provided that includes the PCIe device described above.

[0013] On the other hand, an electronic device is provided, which includes the chip described above.

[0014] The technical solution provided in this application brings at least the following beneficial effects:

[0015] In the technical solution provided in this application, the PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The processor reads first configuration information from the first memory and sends the first configuration information to the link training module, and reads second configuration information from the second memory and sends the second configuration information to the link training module. The link training module performs link training on the transmission link based on the first and second configuration information, thereby enabling the transmission rate of the transmission link to be configured based on the first configuration information and the transmission rate of the transmission link to be improved based on the second configuration information, so that the transmission rate of the transmission link can meet the needs of practical applications.

[0016] Furthermore, since the first memory only stores the first configuration information, the configuration information occupies less storage space, saving storage space in the first memory and thus reducing its size, which in turn reduces the size of the PCIe device. And since the second memory stores the second configuration information, the configuration information in the second memory can be flexibly adjusted according to the transmission rate requirements of the transmission link in actual applications, improving the flexibility of link training. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a PCIe device provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of another PCIe device provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of information storage provided in an embodiment of this application;

[0021] Figure 4 This is a flowchart of a link training method provided in an embodiment of this application;

[0022] Figure 5 This is a flowchart illustrating an information reading process provided in an embodiment of this application;

[0023] Figure 6 This is a flowchart of a link training method provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0027] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] With the development of electronic technology, the PCIe protocol is also undergoing iterative upgrades, resulting in increasingly higher transmission rates for PCIe devices. Currently, PCIe devices require link training to ensure that the transmission link achieves the desired transmission rate.

[0029] PCIe devices include an MP (Micro Processor), an eFuse (Electronic Fuse), and a link training module. The eFuse has data storage capabilities; by applying high voltage or high current to the eFuse to blow (or connect) the fuse, the circuit state of the eFuse is changed, thus storing fixed data. The eFuse is a one-time programmable memory used to permanently store unchangeable data, and its storage space is typically small, ranging from a few kilobytes to tens of kilobytes.

[0030] In related technologies, all configuration information used for link training is stored in the eFuse. The MP reads the configuration information from the eFuse and sends it to the link training module, which then trains the transmission link based on the configuration information.

[0031] However, with the iterative upgrades of the PCIe protocol, the amount of configuration information is increasing, leading to a growing consumption of eFuse storage space. Furthermore, due to the one-time programmable nature of eFuse, new configuration information cannot be written into it, resulting in poor flexibility in link training. To address this, this application provides a PCIe device that not only saves eFuse storage space but also improves the flexibility of link training.

[0032] like Figure 1 As shown, Figure 1This is a schematic diagram of a PCIe device provided in an embodiment of this application. The PCIe device 100 is an external device that communicates with electronic devices using a PCIe interface. For example, the PCIe device 100 can be any of the following: a network card, a Redundant Arrays of Independent Disks (RAID) card, a graphics card, a Peripheral Component Interconnect (PCI) Solid State Drive (SSD) card, a Graphics Processing Unit (GPU) card, a sound card, and an accelerator card, etc. This embodiment of the application does not specifically limit the type of PCIe device 100.

[0033] Optionally, the PCIe device 100 is connected to the Central Processing Unit (CPU). In this case, the PCIe device 100 can be considered a peripheral of the CPU. The PCIe device 100 can be integrated with the CPU on the circuit board of the electronic device, or it can be fixed in the PCIe slot on the CPU's circuit board. Both the PCIe device 100 and the CPU start with the system. By training the transmission link between the CPU and the PCIe device 100, the transmission rate of the transmission link is made to approach the desired transmission rate, thereby enabling high-speed data transmission between the CPU and the PCIe device 100.

[0034] PCIe device 100 includes a first memory 101. The first memory 101 is a device for storing data, programs, etc., and can be any of non-volatile memory, read-only memory, random access memory, etc. Optionally, the first memory 101 is eFuse.

[0035] PCIe device 100 also includes processor 102. Processor 102 is a device used to execute program instructions, process data, control system operation, etc. This application embodiment does not limit the type of processor 102. In practical applications, processor 102 can be a CPU or a small system including a CPU, memory, flash memory, and interface devices, etc. Optionally, processor 102 is an MP (Multi-Level Processor).

[0036] The PCIe device 100 also includes a link training module 103. The link training module 103 is a functional module used to receive configuration information of the transmission link, initialize the transmission link, and configure the transmission rate of the transmission link. Under the control of the Link Training and Status State Machine (LTSSM), the link training module 103 can automatically complete processes such as parameter negotiation, state synchronization, and error recovery of the transmission link, thereby realizing link training. This application embodiment does not limit the structure or function of the link training module 103. In practical applications, the link training module 103 may also have other functions such as data storage and data transmission. Depending on the application scenario requirements, the link training module 103 may be configured to include devices such as registers, transceivers, and processors.

[0037] In this embodiment, the processor 102 is connected to the first memory 101 and the link training module 103. The first memory 101 is used to store first configuration information, and the processor 102 is used to read the first configuration information from the first memory 101 and send the first configuration information to the link training module 103.

[0038] The first configuration information is used to configure the transmission link's transmission rate as the first transmission rate. The first transmission rate can be the transmission rate corresponding to any version of the PCIe protocol. For example, the PCIe protocol has multiple versions, which are named PCIe Gen1 to PCIe Gen6 in chronological order of release. With the iterative upgrades of the PCIe protocol, the transmission rate has also gradually increased. Currently, the transmission rate corresponding to PCIe Gen1 is 2.5 GT / s (Gigabit Transmission per second), PCIe Gen2 is 5.0 GT / s, PCIe Gen3 is 8.0 GT / s, PCIe Gen4 is 16 GT / s, PCIe Gen5 is 32 GT / s, and PCIe Gen6 is 64 GT / s. The first transmission rate can be the transmission rate corresponding to any version of the PCIe protocol from PCIe Gen1 to PCIe Gen6. For example, the first transmission rate could be the transmission rate corresponding to PCIe Gen1, which is 2.5GT / s, or the transmission rate corresponding to PCIe Gen2, which is 5.0GT / s, or even the transmission rate corresponding to PCIe Gen3, which is 8.0GT / s.

[0039] As mentioned above, with the iterative upgrades of the PCIe protocol, the transmission rate is also gradually increasing. Typically, PCIe devices follow a step-by-step speed increase rule, gradually increasing from a transmission rate of 2.5GT / s to 64GT / s, or even higher. That is, starting from an initial transmission rate of 2.5GT / s, through training and negotiation, the transmission link's transmission rate is increased to 5.0GT / s, and through further training and negotiation, the transmission rate is gradually increased to 8.0GT / s, 16GT / s, 32GT / s, 64GT / s, and so on. In some embodiments, PCIe devices can skip stages of speed increase; for example, starting from an initial transmission rate of 2.5GT / s, the transmission rate is first increased to 5.0GT / s, and then directly jumped from 5.0GT / s to 32GT / s for balanced training, thus shortening the training time. In some embodiments, a PCIe device can start with a transfer rate corresponding to any version of the PCIe protocol and increase it. For example, a PCIe device can start with an initial transfer rate of 5.0 GT / s, undergo a 32 GT / s equalization adjustment, and then increase the transfer rate to 64 GT / s. Based on this, the first transfer rate can be the transfer rate corresponding to the first version of the PCIe protocol, i.e., the transfer rate of PCIe Gen1 (2.5 GT / s), or it can be the transfer rate corresponding to any version of the PCIe protocol. For example, the first transfer rate can be the transfer rate corresponding to the second version of the PCIe protocol, i.e., the transfer rate of PCIe Gen2 (5.0 GT / s).

[0040] The first configuration information consists of parameters related to the PCIe protocol corresponding to the first transmission rate. It is understood that the first configuration information differs depending on the first transmission rate, and this embodiment does not limit the content of the first configuration information. Taking a first transmission rate of 2.5GT / s corresponding to PCIe Gen1 as an example, the first configuration information includes parameters such as bit locking, character locking, link width, and signal polarity. Taking a first transmission rate of 5.0GT / s corresponding to PCIe Gen2 as another example, the first configuration information also includes identification parameters used to characterize training negotiation for a transmission rate of 5.0GT / s.

[0041] Since the first memory 101 stores the first configuration information, and the processor 102 is connected to the first memory 101 and the link training module 103, the processor 102 can read the first configuration information from the first memory 101 and send the first configuration information to the link training module 103.

[0042] like Figure 2 As shown, Figure 2A PCIe device is provided. In this example, the processor 102 is MP201, and the first memory 101 is eFuse204. MP201 is connected to eFuse204 and link training module 209. MP201 reads first configuration information from eFuse204 and sends the first configuration information to link training module 209. Optionally, the first configuration information is parameters related to PCIe Gen1 and / or parameters related to PCIe Gen2.

[0043] In one possible implementation, the first configuration information includes at least one first sub-information, and the link training module includes a distribution unit and at least one third register. The distribution unit is connected to the processor and the at least one third register. The distribution unit is used to receive at least one first sub-information and distribute it to at least one third register; the third register is used to store the first sub-information.

[0044] The first sub-information is information related to a specific function of the PCIe device within the first configuration information. For example, the first sub-information may include Tx Preset, which is a predefined combination of equalization parameters from the PCIe transmitter, including parameters such as pre-emphasis and deemphasis. During the EQ (Equalization) phase of link training, Tx Preset is traversed first to achieve coarse adjustment, and based on the coarse adjustment, fine adjustment is performed as needed to ensure that the transmission link achieves the desired transmission rate.

[0045] Since processor 102 is connected to link training module 103, and link training module 103 includes a distribution unit and various third registers, and the distribution unit is connected to processor 102, processor 102 can send the first configuration information to the distribution unit after reading the first configuration information from the first memory 101. The first configuration information includes at least one first sub-information, each of which is a value to be written to a third register. The distribution unit is connected to each third register and can distribute any first sub-information to the corresponding third register; the distribution method will not be described in detail here. The third register receives the first sub-information and stores it.

[0046] like Figure 2 As shown, the link training module 209 includes a distribution unit 206 and a third register group 207. The third register group 207 includes at least one third register. Figure 2 The diagram shows that the third register group 207 includes third registers Fuse_strap0 through 4. In practical applications, the third register group 207 may include more or fewer third registers.

[0047] MP201 is connected to eFuse204 and distribution unit 206, and distribution unit 206 is connected to each of the third registers. Based on this, MP201 reads first configuration information from eFuse204, which includes parameters related to PCIe Gen1 and / or parameters related to PCIe Gen2. MP201 sends the first configuration information to distribution unit 206, and distribution unit 206 distributes the first configuration information to the third registers Fuse_strap0 to 4.

[0048] The link training module 209 further includes a link training unit 208, which is used to receive configuration information of the transmission link, initialize the transmission link, and configure the transmission rate of the transmission link. Its internal structure and specific functions are not limited here. Each third register is connected to the link training unit 208. The third register is used to stably and effectively store the first sub-information before link training. The storage space of the third register is not limited here; in practical applications, any two third registers can correspond to the same or different sizes of storage space. Optionally, the storage space of the third register is several hundred bits.

[0049] Optionally, the PCIe device further includes a fourth register, which is connected to the processor and the link training module. The processor is used to write a second reset signal into the fourth register, the second reset signal being used to reset the link training module; the fourth register is used to store the second reset signal; the link training module is used to read the second reset signal from the fourth register and perform a reset operation based on the second reset signal; the processor is also used to read first configuration information from the first memory if the link training module is successfully reset.

[0050] like Figure 2 As shown, the PCIe device 200 also includes COLD_RESETB_PCIE210, which is the fourth register. COLD_RESETB_PCIE210 is connected to MP201 and to the link training module 209. Optionally, COLD_RESETB_PCIE210 is connected to the distribution unit 206, the third register group 207, and the link training unit 208. The storage space of the fourth register is not limited here.

[0051] In this embodiment, the processor 102 can write the second reset signal into a fourth register so that the fourth register stores the second reset signal. The second reset signal is used to reset the link training module 103. In practical applications, if the second reset signal is high, it indicates that the link training module 103 is reset; if the second reset signal is low, it indicates that the link training module 103 is not reset. For example, MP201 writes 1 into COLD_RESETB_PCIE210, where 1 represents the second reset signal PCIe Cold Reset being at a high level.

[0052] The link training module 103 reads the second reset signal from the fourth register and performs a reset operation based on the second reset signal. The content of the reset operation is not limited here. By performing a reset operation on the link training module 103, the link training module 103 is started. Optionally, the processor 102 acquires the status signal of the link training module 103 in real time. This status signal indicates whether the link training module 103 is in the started state. For example, a high level status signal indicates that the link training module 103 is in the started state; a low level status signal indicates that the link training module 103 is in the unstarted state.

[0053] The link training module 103 has been successfully reset, meaning it is now in the startup state. Upon successful reset, the processor 102 can read the first configuration information from the first memory 101 and send it to the link training module 103.

[0054] In the embodiments of this application, such as Figure 1 As shown, the PCIe device 100 is connected to the second memory 104. The second memory 104 is used to store second configuration information, and the processor 102 is also used to read the second configuration information from the second memory 104 and send the second configuration information to the link training module 103.

[0055] The second configuration information is used to upgrade the transmission link's transmission rate from the first transmission rate to the second transmission rate. Based on the iterative upgrades of the PCIe protocol, the transmission rate is also gradually increasing. Therefore, the PCIe protocol version corresponding to the second transmission rate is an upgraded version of the PCIe protocol version corresponding to the first transmission rate. The second transmission rate can be the transmission rate corresponding to any version of the PCIe protocol. For example, the first transmission rate is the transmission rate corresponding to PCIe Gen1 or 2, and the second transmission rate is the transmission rate corresponding to any of PCIe Gen3 to 6.

[0056] The second configuration information consists of parameters related to the PCIe protocol corresponding to the second transmission rate. It is understood that the second configuration information will differ depending on the second transmission rate, and this application does not limit the content of the second configuration information. For example, if the second transmission rate is 8.0 GT / s corresponding to PCIe Gen3, the second configuration information includes parameters such as sender pre-emphasis, receiver gain, and block locking.

[0057] Since the second memory 104 stores the second configuration information, and the processor 102 is connected to the second memory 104 and the link training module 103, the processor 102 can read the second configuration information from the second memory 104 and send the second configuration information to the link training module 103.

[0058] like Figure 2 As shown, PCIe device 200 is connected to Flash 300, where Flash 300 is the secondary memory 104. Flash 300 is a non-volatile memory that supports multiple reads and writes. In practical applications, the required secondary configuration information can be flexibly written according to application needs. For example, parameters related to any of PCIe Gen3 to 6 can be written to Flash 300 according to the actual application requirements. Alternatively, with the release of new version protocols, parameters related to the new version protocol can be written (e.g., parameters related to PCIe Gen7).

[0059] Flash300 is connected to MP201. MP201 can read the second configuration information from Flash300 and send the second configuration information to the link training module 209.

[0060] Optionally, the PCIe device 200 and Flash 300 are connected via SPI (Serial Peripheral Interface). In this example, the PCIe device 200 may include a control module 205. The control module 205 is a module used to manage the data read / write timing and data transmission process during communication between the PCIe device 200 and Flash 300. Its structure and specific implementation principle are not limited here. The control module 205 is connected to MP201 and Flash 300, thereby realizing an indirect connection between MP201 and Flash 300. MP201 can send a read command to the control module 205. The control module 205 reads the second configuration information from Flash 300 based on the read command and sends the second configuration information to MP201, thereby enabling MP201 to send the second configuration information to the link training module 209.

[0061] It is understandable that connecting PCIe device 200 and Flash 300 via SPI is only one possible implementation. In practical applications, there may be other connection methods. For example, PCIe device 200 and Flash 300 can be connected via an integrated circuit bus.

[0062] In one possible implementation, the first configuration information includes first enable information, which indicates whether a state machine is enabled. The state machine is used to control the link training module 103 to perform link training. The processor 102 is used to read second configuration information from the second memory 104 when the first enable information indicates that the state machine is not enabled.

[0063] In this embodiment, the state machine refers to the LTSSM mentioned above, which is used to control the execution process of link training. The processor 102 can send a first enable message to the link training module 103 to control whether the state machine is enabled. In practical applications, if the first enable signal is high, it indicates that the state machine is enabled (i.e., the state machine is started); if the first enable signal is low, it indicates that the state machine is not enabled (i.e., the state machine is not started or is stopped from starting).

[0064] Optionally, the processor 102 sends each first sub-information to the distribution unit, and the distribution unit distributes each first sub-information to the corresponding third register. The first sub-information includes first enable information, and each third register contains a register for storing the first enable information. For example, the third register includes the Fuse_Strap_LTSSM_ENABLE register, which stores the first enable information. If the first enable information is high (i.e., 1), the first enable information represents an enabled state machine; if the first enable information is low (i.e., 0), the first enable information represents a disabled state machine.

[0065] If the first enabling information indicates that the state machine is enabled, then the LTSSM is started, and the link training module 103 can perform link training on the transmission link based on the first configuration information under the control of the LTSSM, so that the transmission rate of the transmission link approaches the first transmission rate. If the first enabling information indicates that the state machine is disabled, then the processor 102 reads the second configuration information from the second memory 104.

[0066] By sending first configuration information to the link training module, and the first enable information in the first configuration information indicating that LTSSM is not enabled, the processor reads second configuration information from the second memory, thereby realizing the control of the transmission rate of the transmission link according to the needs of the actual application and improving the flexibility of link training.

[0067] In one possible implementation, the link training module 103 includes at least one first register, and the second configuration information includes at least one second sub-information. Each second sub-information includes a register address of a first register and a value to be written to the first register. The processor 102 is configured to read the i-th second sub-information from the second memory 104 and send the value of the i-th second sub-information to the first register indicated by the register address in the i-th second sub-information. The first register indicated by the register address in the i-th second sub-information is used to store the value of the i-th second sub-information, where i is a positive integer not greater than the number of second sub-information.

[0068] This application does not limit the number or storage space of the first registers. In practical applications, any two first registers can correspond to storage spaces of the same or different sizes. Optionally, the storage space of the first registers is several hundred bits.

[0069] The second configuration information includes at least one second sub-information, and the number of second sub-information is less than or equal to the number of first registers. For example, if the link training module 103 includes 6 first registers, then the number of second sub-information is less than or equal to 6. Each second sub-information includes the register address of a first register and the value to be written to the first register; different second sub-information corresponds to different first registers.

[0070] Optionally, any second sub-information exists in the form of a key-value pair, where the key represents the register address of the first register and the value represents the value to be written to the first register. Alternatively, the second configuration information exists in the form of a table, which includes multiple rows, each row containing at least two cells. Each row corresponds to one second sub-information, with the register address of the first register and the value to be written to the first register occupying two cells in that row.

[0071] like Figure 3 As shown, the table area labeled 301 represents the second configuration information. The second configuration information 301 includes six rows, each storing one piece of second sub-information. Each row contains two cells: the first cell contains REGx_VALUE (where x is any positive integer from 1 to 6), representing the value to be written to the first register; the second cell contains REGx_ADDR, representing the register address of the first register. It can be understood that... Figure 3 Six second sub-information items are shown. In practical applications, the number of second sub-information items can be more or less, and no limitation is made here.

[0072] Processor 102 can read any one of the second sub-information from the second memory 104. For ease of description, any one of the second sub-information is denoted as the i-th second sub-information. The i-th second sub-information includes a register address and a value. Processor 102 determines the first register indicated by the register address and writes the value into the first register.

[0073] like Figure 2 As shown, the link training module 103 includes a link training unit 208, which includes various first registers indicated by the register address REGx_ADDR. MP201 is connected to the link training unit 208. Based on this, MP201 can read the i-th second sub-information from Flash 300, determine the first register indicated by the register address included in the i-th second sub-information, and write the value included in the i-th second sub-information into the first register. For example, if the i-th second sub-information includes the register address REG2_ADDR, then MP201 can write the value REG2_VALUE into the first register indicated by the register address REG2_ADDR.

[0074] By writing the corresponding value into the first register indicated by the register address, the second configuration information is accurately distributed to each first register, ensuring that the link training can be executed normally.

[0075] In an exemplary embodiment, the second memory 104 is further configured to store quantity information, which indicates the quantity of the second sub-information; the processor 102 is configured to read the quantity information from the second memory 104, and read the i-th second sub-information from the second memory 104 when the quantity indicated by the quantity information meets the conditions.

[0076] This application embodiment does not limit the quantity condition indicated by the quantity information. For example, the quantity condition indicated by the quantity information being satisfied refers to: the quantity of the second sub-information being not 0, or the quantity of the second sub-information being not less than a pre-configured quantity threshold, or the quantity of the second sub-information being not less than the parameter value specified by the version of the PCI protocol corresponding to the second transmission rate. The processor 102 reads the quantity information from the second memory 104. If the quantity condition indicated by the quantity information is satisfied, it sequentially reads each piece of second sub-information from the second memory 104 and sends each piece of second sub-information to the link training module 103. It is understood that the quantity of second sub-information read by the processor 102 is less than or equal to the quantity indicated by the quantity information.

[0077] Optionally, the second memory 104 stores a table. The table includes multiple rows, one row for storing quantity information, and the remaining rows for storing various second sub-information.

[0078] For example, the second memory 104 stores as follows Figure 3 The table shown contains Table Size + 1 rows, where Table Size represents the number of second sub-information items. For example, in... Figure 3 In this context, Table Size can be equal to 6, indicating that there are 6 pieces of second sub-information. Assuming that Table Size+1 rows are denoted as row 0 to row 1, then: row 0 is used to store quantity information, and rows 1 to 1 are used to store each piece of second sub-information.

[0079] Each row consists of two cells, each storing one byte of data. For ease of description, these two cells are referred to as Byte0 and Byte1. For row 0, either Byte0 or Byte1 stores quantity information. Optionally, row 0 can be considered a table header, containing only one cell that stores quantity information. For rows 1 through ByteSize, Byte0 stores the register address REGx_ADDR (x takes any positive integer from 1 to TableSize), and Byte1 stores the value REGx_VALUE, which is the value of the first register indicated by the register address to be written.

[0080] Processor 102 first reads the 0th row of data from the table in the second memory 104. The 0th row of data is used to store the quantity information Table Size. If the quantity information Table Size is not 0, processor 102 reads the quantity from the 1st row to the 1st row of Table Size in sequence. For each row of data, processor 102 writes the value REGx_VALUE into the first register indicated by the register address REGx_ADDR.

[0081] By reading the second sub-information from the second memory when the quantity of the second sub-information indicated by the quantity information meets the condition, the probability of reading failure is reduced and the success rate of link training is improved.

[0082] Optionally, the link training module 103 includes a second register and a link training unit. The link training unit includes at least one first register, and the second register is connected to the processor 102 and the link training unit. The processor 102 is used to write a first reset signal into the second register, and the first reset signal is used to reset the link training unit. The second register is used to store the first reset signal. The link training unit is used to read the first reset signal from the second register and perform a reset operation based on the first reset signal. The processor 102 is also used to read the i-th second sub-information from the second memory 104 when the link training unit is successfully reset.

[0083] The processor 102 can write the first reset signal into the second register so that the second register stores the first reset signal. The first reset signal is used to reset the link training unit. In practical applications, if the first reset signal is high, the first reset signal indicates that the link training unit is reset; if the first reset signal is low, the first reset signal indicates that the link training unit is not reset.

[0084] The link training unit reads the first reset signal from the second register and performs a reset operation based on the first reset signal. The content of the reset operation is not limited here. By performing a reset operation on the link training unit, the link training unit is started. Optionally, the processor 102 acquires the status signal of the link training unit in real time, which indicates whether the link training unit is in the started state. For example, a high level status signal indicates that the link training unit is in the started state; a low level status signal indicates that the link training unit is in the unstarted state.

[0085] A successful reset of the link training unit indicates that the link training unit is in the startup state. Upon successful reset, the processor 102 can read the second configuration information from the second memory 104. The link training unit includes at least one first register, and the second configuration information includes at least one second sub-information. The processor 102 writes the value in each second sub-information to the first register indicated by that register address, based on the register address in each second sub-information.

[0086] like Figure 2 As shown, the link training module 209 includes HARD_RESETB_PCIE211 and link training unit 208. HARD_RESETB_PCIE211 is a second register, and the storage space of the second register is not limited in this embodiment. HARD_RESETB_PCIE211 is connected to MP201 and link training unit 208.

[0087] The following is combined Figure 2Let's elaborate. Specifically, the link training module 209 includes HARD_RESETB_PCIE211 and a link training unit 208. HARD_RESETB_PCIE211 is a second register used to store the first reset signal PCIe HardReset. HARD_RESETB_PCIE211 is connected to MP201 and the link training unit 208. MP201 writes a 1 to HARD_RESETB_PCIE211, where 1 represents the first reset signal PCIe Hard Reset being at a high level. The link training unit 208 reads the PCIe Hard Reset from HARD_RESETB_PCIE211. Since PCIe Hard Reset is at a high level, it indicates that the link training unit 208 is being reset; therefore, the link training unit 208 begins to perform a reset operation. After detecting that the link training unit 208 has been successfully reset, MP201 reads the second configuration information from Flash 300. Each second sub-information in the second configuration information includes the value REGx_VALUE and the register address REGx_ADDR. The link training unit 208 includes a first register indicated by the register address REGx_ADDR. MP201 writes the value REGx_VALUE into the first register.

[0088] Optionally, the PCIe device 100 further includes a third memory, which is connected to the processor 102. The processor 102 is used to read second configuration information from the second memory 104 and send the second configuration information to the third memory; the third memory is used to store the second configuration information; the processor 102 is also used to read the i-th second sub-information from the third memory.

[0089] The third memory is a device used to store data, programs, etc., and can be any of non-volatile memory, random access memory, etc. Optionally, the third memory is SRAM (Static Random-Access Memory).

[0090] The third memory is connected to the processor 102. The processor 102 first reads the second configuration information from the second memory 104 and writes it into the third memory. Then, it reads each piece of second sub-information from the third memory and writes each piece of second sub-information into its corresponding first register. Since both the third memory and the processor are located inside the PCIe device, while the second memory is located outside the PCIe device, the processor's efficiency in reading data from the third memory is higher than that in reading data from the second memory. By storing the second configuration information in the third memory, the processor can quickly read the second configuration information required for link training when link training is needed, thus improving the efficiency of link training.

[0091] like Figure 2 As shown, the PCIe device 100 also includes an SRAM 203, which is a third memory and is connected to the MP 201. The PCIe device 100 is connected to the Flash 300. The MP 201 reads the second configuration information from the Flash 300 and writes the second configuration information into the SRAM 203. Subsequently, when link training needs to be performed, the MP 201 reads the second configuration information from the SRAM 203 and sends the second configuration information to the link training unit 208.

[0092] Since the processor 102 reads the first configuration information from the first memory 101 and sends the first configuration information to the link training module 103, and the processor 102 reads the second configuration information from the second memory 104 and sends the second configuration information to the link training module 103, the link training module 103 is used to receive the first configuration information and the second configuration information, and to perform link training on the transmission link based on the first configuration information and the second configuration information.

[0093] In PCIe devices, link training is required for the transmission link to bring its transmission rate closer to the desired transmission rate. In this example, the link training module 103 first trains the transmission link based on first configuration information to bring its transmission rate closer to a first transmission rate. Then, the link training module 103 trains the transmission link based on second configuration information to improve its transmission rate, bringing it closer to a second transmission rate.

[0094] In one possible implementation, the processor 102 is further configured to send a second enable information to the link training module 103, the second enable information indicating whether the state machine is enabled, the state machine being used to control the link training module 103 to perform link training; the link training module 103 is configured to perform link training on the transmission link based on the first configuration information and the second configuration information when the second enable information indicates that the state machine is enabled.

[0095] The processor 102 can send a second enable message to the link training module 103 to control whether LTSSM is enabled. In practical applications, if the second enable signal is high, it indicates that LTSSM is enabled (i.e., LTSSM is started); if the second enable signal is low, it indicates that LTSSM is not enabled (i.e., LTSSM is not started or is stopped). If the second enable signal indicates that LTSSM is enabled, the link training module 103 performs link training on the transmission link based on the first configuration information and the second configuration information.

[0096] Optionally, the link training module 103 includes a register for storing second enable information, such as the Fuse_Strap_LTSSM_ENABLE register. The processor 102 can write the second enable information into the Fuse_Strap_LTSSM_ENABLE register. The Fuse_Strap_LTSSM_ENABLE register is connected to the link training unit, which reads the second enable information from the Fuse_Strap_LTSSM_ENABLE register. If the second enable information is high, the link training unit performs link training on the transmission link based on the first configuration information and the second configuration information.

[0097] By sending a second enable message to the link training module, and with the second enable message indicating that LTSSM is enabled, link training is performed on the transmission link based on the first and second configuration information. This enables the configuration of the transmission link's transmission rate according to the needs of actual applications, thus improving the flexibility of link training.

[0098] A detailed embodiment is provided below. Figure 2 As shown, the PCIe device 200 includes a control module 205, an MP 201 (corresponding to the processor mentioned above), a ROM (Read-Only Memory) 202, an SRAM 203 (corresponding to the third memory mentioned above), an eFuse 204 (corresponding to the first memory mentioned above), a link training module 209, and a COLD_RESETB_PCIE 210 (corresponding to the fourth register mentioned above). These devices are interconnected through the internal bus of the PCIe device 200. Optionally, the PCIe device 200 may also include other modules, the structure and function of which are not limited here. The link training module 209 includes a distribution unit 206, a third register group 207, a link training unit 208, and HARD_RESETB_PCIE211 (corresponding to the second register mentioned above). The distribution unit 206, link training unit 208, and HARD_RESETB_PCIE211 are all connected to MP201 via an internal bus. The distribution unit 206 is connected to the third register group 207, which includes at least one third register. Each third register is connected to the link training unit 208. For example, the third register group 207 includes third registers Fuse_Strap0 to 4, which are connected to the link training unit 208. The link training unit 208 includes at least one first register, whose address can be represented as REGx_ADDR (where x is a positive integer). Furthermore, the PCIe device 200 is connected to the CPU 400.

[0099] based on Figure 2 The PCIe device 200 shown in this embodiment is based on, as described above. Figure 4 The illustrated process implements link training. Specifically, the process includes:

[0100] Step 401: Power on the PCIe device.

[0101] Optionally, the PCIe device 200 is located on the system motherboard, which also includes a Flash 300 and a CPU 400. The PCIe device 200, Flash 300, and CPU 400 are interconnected via a bus located outside the PCIe device 200 and can be referred to as an external bus. The CPU 400 is connected to the power pin of the PCIe device 200, and the CPU 400 powers on the PCIe device 200 through the power pin.

[0102] Step 402: Perform a reset operation based on the reset signal of the PCIe device.

[0103] CPU 400 releases a reset signal to PCIe device 200, which is used to reset PCIe device 200. Specifically, if the reset signal is high, it indicates that PCIe device 200 is being reset; if the reset signal is low, it indicates that PCIe device 200 is not being reset. If PCIe device 200 receives a high-level reset signal, it performs a reset operation to start PCIe device 200.

[0104] Step 403: MP executes the boot program in ROM, writes 1 to COLD_RESETB_PCIE, releases PCIe ColdReset, and the link training module performs a reset operation.

[0105] ROM 202 stores the boot code, a program used to start the PCIe device 200. MP 201 reads the boot code from ROM 202 and runs it. By running the boot code, MP 201 writes a 1 to COLD_RESETB_PCIE210, where 1 represents the high level of the second reset signal PCIe Cold Reset. The link training module 209 performs a reset operation based on the second reset signal PCIe Cold Reset to start the link training module 209.

[0106] Step 404, MP stores the first configuration information in eFuse into each of the third registers.

[0107] eFuse204 stores the first configuration information. MP201 reads the first configuration information from eFuse204 and sends it to distribution unit 206. Distribution unit 206 writes the first configuration information into third register group 207. The first configuration information includes at least one first sub-information, and third register group 207 includes at least one third register. MP201 sends each first sub-information and its corresponding register address to distribution unit 206. The register address corresponding to each first sub-information represents the third register used to store the first sub-information. Distribution unit 206 distributes each first sub-information to the corresponding third register according to its register address. Taking third register group 207 as an example, which includes third registers Fuse_Strap0 to 4, distribution unit 206 can write the corresponding first sub-information into each of the third registers Fuse_Strap0 to 4.

[0108] Step 405: Determine if Fuse_Strap_LTSSM_ENABLE is 1.

[0109] The first sub-information includes the first enable information, which is stored in the Fuse_Strap_LTSSM_ENABLE register. Figure 2 (Not shown) This register is a third register; for example, the third register Fuse_Strap3 is the Fuse_Strap_LTSSM_ENABLE register. For ease of distinction, the Fuse_Strap_LTSSM_ENABLE register can be called the destination register, and the third register includes the destination register. In the Fuse_Strap_LTSSM_ENABLE register, the first enable information can be 1, which is a high level, indicating that LTSSM is enabled; the first enable information can also be 0, which is a low level, indicating that LTSSM is not enabled.

[0110] Step 406: If Fuse_Strap_LTSSM_ENABLE is 1, write 1 to HARD_RESETB_PCIE to release PCIe Hard Reset, and the link training unit performs a reset operation.

[0111] With LTSSM enabled, MP201 writes a 1 to HARD_RESETB_PCIE211. This 1 represents a high-level first reset signal (PCIe Hard Reset), which is used to reset the link training unit 208. Specifically, a high level PCIe Hard Reset indicates a reset of the link training unit 208; a low level indicates no reset. The link training unit 208 reads the first reset signal (PCIe Hard Reset) from HARD_RESETB_PCIE211. Since the first reset signal (PCIe Hard Reset) is high, the link training unit 208 performs a reset operation to start the link training unit 208.

[0112] Step 407: The link training unit performs link training.

[0113] After the link training unit 208 is successfully started, under the control of the LTSSM, it performs link training on the transmission link based on the first configuration information. The transmission link is the link between the link training unit 208 and the CPU 400, used for data transmission. After training, the transmission rate of the transmission link approaches the first transmission rate corresponding to the first configuration information. For example, if the first configuration information includes parameters related to PCIe Gen1, the transmission rate of the transmission link will approach 2.5 GT / s after training. Or, if the first configuration information includes parameters related to PCIe Gen2, the transmission rate of the transmission link will approach 5.0 GT / s after training.

[0114] Step 408: When Fuse_Strap_LTSSM_ENABLE is 0, MP sends the second configuration information to the link training unit 208. Specifically, step 408 includes the following steps.

[0115] 1. MP loads the table from Flash to SRAM.

[0116] Flash300 stores such as Figure 3 The table is shown below. MP201 sends a read request to control module 205. Based on the read request, control module 205 reads the table from Flash 300 and sends the table back to MP201. MP201 stores the table in SRAM 203.

[0117] 2. MP writes 1 to HARD_RESETB_PCIE to release PCIe Hard Reset, and the link training unit performs a reset operation.

[0118] MP201 writes 1 into HARD_RESETB_PCIE211. The 1 represents the first reset signal PCIe Hard Reset which is at a high level. The first reset signal PCIe Hard Reset is used to reset the link training unit 208. The link training unit 208 reads the first reset signal PCIe Hard Reset from HARD_RESETB_PCIE211. Since the first reset signal PCIe Hard Reset is at a high level, the link training unit 208 performs a reset operation to start the link training unit 208.

[0119] 3. The MP distributes the second configuration information to each first register.

[0120] Specifically, as Figure 5 shown, after MP201 writes 1 into HARD_RESETB_PCIE211, based on the fact that the first reset signal PCIe Hard Reset is at a high level, the link training unit 208 performs a reset operation to start the link training unit 208.

[0121] When the link training unit 208 is successfully reset, MP201 reads the table as Figure 3 shown. The table includes the quantity information Table Size. If the quantity information Table Size is 0, MP201 directly writes 1 into the Fuse_Strap_LTSSM_ENABLE register. If the quantity information Table Size is not 0, then: let x = 1, MP201 reads the first second sub - information from the table. The first second sub - information includes the register address REG1_ADDR and the value REG1_VALUE. MP201 writes the value REG1_VALUE into the first register indicated by the register address REG1_ADDR, and determines whether x is greater than or equal to the quantity information Table Size; if x < Table_Size, let x = x + 1, MP201 reads the second second sub - information from the table. The second second sub - information includes the register address REG2_ADDR and the value REG2_VALUE. MP201 writes the value REG2_VALUE into the first register indicated by the register address REG2_ADDR, and determines whether x is greater than or equal to the quantity information Table Size; if x < Table_Size, repeat the previous operation. If x ≥ Table_Size, MP201 writes 1 into the Fuse_Strap_LTSSM_ENABLE register.

[0122] 4. MP writes 1 in Fuse_Strap_LTSSM_ENABLE.

[0123] MP201 writes 1 to the Fuse_Strap_LTSSM_ENABLE register. 1 is a high level, indicating that LTSSM is enabled.

[0124] Step 407: The link training unit performs link training.

[0125] After enabling LTSSM, the link training unit 208, under the control of LTSSM, performs link training on the transmission link based on the first configuration information and the second configuration information. During training, the link training unit 208 first performs link training on the transmission link based on the first configuration information to make the transmission rate of the transmission link approach the first transmission rate corresponding to the first configuration information. For example, if the first configuration information includes parameters related to PCIe Gen2, then after training, the transmission rate of the transmission link will approach 5.0 GT / s. Next, the link training unit 208 performs link training on the transmission link based on the second configuration information to make the transmission rate of the transmission link approach the second transmission rate corresponding to the second configuration information. For example, if the second configuration information includes parameters related to PCIe Gen6, then after training, the transmission rate of the transmission link will approach 64 GT / s.

[0126] In the above technical solution, the PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The processor reads first configuration information from the first memory and sends it to the link training module, and reads second configuration information from the second memory and sends it to the link training module. The link training module performs link training on the transmission link based on the first and second configuration information, thereby configuring the transmission rate of the transmission link based on the first configuration information and improving the transmission rate of the transmission link based on the second configuration information, so that the transmission rate of the transmission link can meet the needs of practical applications.

[0127] Furthermore, since the first memory only stores the first configuration information, the configuration information occupies less storage space, saving storage space in the first memory and thus reducing its size, which in turn reduces the size of the PCIe device. And since the second memory stores the second configuration information, the configuration information in the second memory can be flexibly adjusted according to the transmission rate requirements of the transmission link in actual applications, improving the flexibility of link training.

[0128] Figure 6The diagram shows a flowchart of a link training method provided in an embodiment of this application. The method is executed by the PCIe device mentioned above. The PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The first memory stores first configuration information, and the second memory stores second configuration information. The first configuration information is used to configure the transmission link's transmission rate to a first transmission rate, and the second configuration information is used to increase the transmission link's transmission rate from the first transmission rate to a second transmission rate. Figure 6 As shown, the method includes the following steps.

[0129] Step 601: The processor reads the first configuration information from the first memory and sends the first configuration information to the link training module;

[0130] Step 602: The processor reads the second configuration information from the second memory and sends the second configuration information to the link training module;

[0131] Step 603: Receive first configuration information and second configuration information through the link training module, and perform link training on the transmission link based on the first configuration information and second configuration information.

[0132] In one possible implementation, the link training module includes at least one first register, and the second configuration information includes at least one second sub-information, each second sub-information including the register address of a first register and the value to be written to the first register;

[0133] Step 602 includes:

[0134] The processor reads the i-th second sub-information from the second memory and sends the value of the i-th second sub-information to the first register indicated by the register address in the i-th second sub-information;

[0135] The second configuration information is received through the link training module, including:

[0136] The value of the i-th second sub-information is stored in the first register indicated by the register address in the i-th second sub-information, where i is a positive integer not greater than the number of second sub-information.

[0137] In one possible implementation, the second memory is also used to store quantity information, which indicates the quantity of the second sub-information;

[0138] The processor reads the i-th second sub-information from the second memory, including:

[0139] The processor reads quantity information from the second memory, and if the quantity indicated by the quantity information meets the conditions, it reads the i-th second sub-information from the second memory.

[0140] In one possible implementation, the link training module includes a second register and a link training unit, the link training unit includes at least one first register, and the second register is connected to the processor and the link training unit.

[0141] The method also includes:

[0142] The processor writes the first reset signal into the second register. The first reset signal is used to reset the link training unit.

[0143] The first reset signal is stored in the second register;

[0144] The link training unit reads the first reset signal from the second register and performs a reset operation based on the first reset signal.

[0145] The processor reads the i-th second sub-information from the second memory, including:

[0146] If the processor successfully resets the link training unit, it reads the i-th second sub-information from the second memory.

[0147] In one possible implementation, the PCIe device also includes a third memory, which is connected to the processor.

[0148] The processor reads the i-th second sub-information from the second memory, including:

[0149] The processor reads the second configuration information from the second memory and sends the second configuration information to the third memory.

[0150] The second configuration information is stored in a third memory.

[0151] The processor reads the i-th second sub-information from the third memory.

[0152] In one possible implementation, the first configuration information includes first enable information, which indicates whether the state machine is enabled. The state machine is used to control the link training module to perform link training.

[0153] The processor reads the second configuration information from the second memory, including:

[0154] The processor reads the second configuration information from the second memory when the first enable information represents an disabled state machine.

[0155] In one possible implementation, link training is performed on the transmission link based on the first configuration information and the second configuration information, including:

[0156] The processor sends a second enable message to the link training module. The second enable message indicates whether the state machine is enabled. The state machine is used to control the link training module to perform link training.

[0157] With the second enabling information representing the enabling state machine, the link training module performs link training on the transmission link based on the first configuration information and the second configuration information.

[0158] In one possible implementation, the first configuration information includes at least one first sub-information, and the link training module includes a distribution unit and at least one third register, with the distribution unit connected to the processor and at least one third register.

[0159] The first configuration information is received through the link training module, including:

[0160] The distribution unit receives at least one first sub-information and distributes the at least one first sub-information to at least one third register.

[0161] Each first sub-information is stored in each third register.

[0162] In one possible implementation, the PCIe device also includes a fourth register, which is connected to the processor and the link training module.

[0163] The method also includes:

[0164] The processor writes the second reset signal into the fourth register. The second reset signal is used to reset the link training module.

[0165] The second reset signal is stored in the fourth register;

[0166] The link training module reads the second reset signal from the fourth register and performs a reset operation based on the second reset signal.

[0167] The processor reads the first configuration information from the first memory, including:

[0168] If the link training module is successfully reset, the processor reads the first configuration information from the first memory.

[0169] In the above technical solution, the PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The processor reads first configuration information from the first memory and sends it to the link training module, and reads second configuration information from the second memory and sends it to the link training module. The link training module performs link training on the transmission link based on the first and second configuration information, thereby configuring the transmission rate of the transmission link based on the first configuration information and improving the transmission rate of the transmission link based on the second configuration information, so that the transmission rate of the transmission link can meet the needs of practical applications.

[0170] Furthermore, since the first memory only stores the first configuration information, the configuration information occupies less storage space, saving storage space in the first memory and thus reducing its size, which in turn reduces the size of the PCIe device. And since the second memory stores the second configuration information, the configuration information in the second memory can be flexibly adjusted according to the transmission rate requirements of the transmission link in actual applications, improving the flexibility of link training.

[0171] The above-described link training method and PCIe device are based on the same inventive concept, and the technical features described in the PCIe device description also apply to the above-described method embodiments. For specific details, please refer to the technical features described in the PCIe device description; for brevity, they will not be repeated here.

[0172] This application also provides a chip including a PCIe device 701. The PCIe device 701 has been described above and will not be repeated here. Optionally, as... Figure 7 As shown, the chip also includes a central processing unit 702, a bus 704, and a second memory 703. The PCIe device 701, the central processing unit 702, and the second memory 703 are interconnected via the bus 704. The structure and function of each device have been described above and will not be repeated here.

[0173] It should be noted that bus 704 is a bus located outside of PCIe device 701, and is the external bus mentioned above. In practical applications, the chip may only include PCIe device 701, with the central processing unit 702, bus 704, and secondary memory 703 located outside the chip.

[0174] Typically, the chip also includes input and output interfaces, which are interconnected with the PCIe device 701, the central processing unit 702, and the secondary memory 703 via bus 704. The input interface is used to receive data sent to the chip, and the output interface is used to output data generated by the chip.

[0175] This application also provides an electronic device, such as... Figure 8 As shown, the electronic device includes the chip 801 mentioned above. Optionally, the electronic device also includes a memory 802, a transceiver 803, and a bus 804, which are interconnected via the bus 804. The bus 804 is located outside the chip 801 and is a different bus from the bus 704. The memory 802 is used to store data, and the transceiver 803 is used to receive and transmit data.

[0176] Electronic devices may include terminal devices and servers. Terminal devices can be any electronic product capable of human-computer interaction with a user through one or more methods such as a keyboard, touchpad, remote control, voice interaction, or handwriting device. For example, a terminal device can be a mobile phone or a computer, where mobile phones include, but are not limited to, smartphones, foldable phones, slider phones, or flip phones, and computers include, but are not limited to, tablets, laptops, desktop computers, PPCs (Pocket PCs), or PCs (Personal Computers). In practical applications, terminal devices may also include smart speakers, smartwatches, PDAs (Personal Digital Assistants), wearable devices, smart car systems, smart TVs, etc. A server may be a single server or a server cluster consisting of multiple servers; this application embodiment does not limit this. Furthermore, the functions of the terminal device and the server are not limited herein.

[0177] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0178] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A PCIe device, characterized in that, The PCIe device includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The first memory is used to store first configuration information, and the second memory is used to store second configuration information. The first configuration information is used to configure the transmission link to a first transmission rate, and the second configuration information is used to increase the transmission link's transmission rate from the first transmission rate to the second transmission rate. The processor is configured to read the first configuration information from the first memory and send the first configuration information to the link training module; wherein, the first configuration information includes first enable information, the first enable information representing whether the state machine is enabled, and the state machine is configured to control the link training module to perform link training. The processor is further configured to read second configuration information from the second memory and send the second configuration information to the link training module when the first enable information indicates that the state machine is not enabled; the second memory is a non-volatile memory. The link training module is configured to receive the first configuration information and the second configuration information, perform link training on the transmission link based on the first configuration information to make the transmission rate of the transmission link approach the first transmission rate, and perform link training on the transmission link based on the second configuration information to improve the transmission rate of the transmission link so that the transmission rate of the transmission link approaches the second transmission rate.

2. The PCIe device according to claim 1, characterized in that, The link training module includes at least one first register, and the second configuration information includes at least one second sub-information, each second sub-information including the register address of a first register and the value to be written to the first register; The processor is configured to read the i-th second sub-information from the second memory and send the value of the i-th second sub-information to the first register indicated by the register address in the i-th second sub-information; The first register indicated by the register address in the i-th second sub-information is used to store the value in the i-th second sub-information, where i is a positive integer not greater than the number of the second sub-information.

3. The PCIe device according to claim 2, characterized in that, The second memory is also used to store quantity information, which indicates the quantity of the second sub-information; The processor is configured to read the quantity information from the second memory, and, if the quantity indicated by the quantity information meets the conditions, read the i-th second sub-information from the second memory.

4. The PCIe device according to claim 2, characterized in that, The link training module includes a second register and a link training unit. The link training unit includes at least one first register. The second register is connected to the processor and the link training unit. The processor is configured to write a first reset signal into the second register, wherein the first reset signal is configured to reset the link training unit; The second register is used to store the first reset signal; The link training unit is used to read the first reset signal from the second register and perform a reset operation based on the first reset signal; The processor is further configured to read the i-th second sub-information from the second memory when the link training unit is successfully reset.

5. The PCIe device according to claim 2, characterized in that, The PCIe device also includes a third memory, which is connected to the processor; The processor is configured to read second configuration information from the second memory and send the second configuration information to the third memory; The third memory is used to store the second configuration information; The processor is also configured to read the i-th second sub-information from the third memory.

6. The PCIe device according to any one of claims 1 to 5, characterized in that, The processor is further configured to send a second enable information to the link training module, the second enable information indicating whether the state machine is enabled, and the state machine being configured to control the link training module to perform link training. The link training module is used to perform link training on the transmission link based on the first configuration information and the second configuration information when the state machine is enabled by the second enabling information.

7. The PCIe device according to any one of claims 1 to 5, characterized in that, The first configuration information includes at least one first sub-information, and the link training module includes a distribution unit and at least one third register, wherein the distribution unit is connected to the processor and the at least one third register; The distribution unit is configured to receive the at least one first sub-information and distribute the at least one first sub-information to the at least one third register; The third register is used to store the first sub-information.

8. The PCIe device according to any one of claims 1 to 5, characterized in that, The PCIe device also includes a fourth register, which is connected to the processor and the link training module. The processor is configured to write a second reset signal into the fourth register, wherein the second reset signal is configured to reset the link training module; The fourth register is used to store the second reset signal; The link training module is used to read the second reset signal from the fourth register and perform a reset operation based on the second reset signal; The processor is further configured to read the first configuration information from the first memory when the link training module is successfully reset.

9. A link training method, characterized in that, The method is executed by a PCIe device, which includes a first memory, a processor, and a link training module. The PCIe device is connected to a second memory. The first memory stores first configuration information, and the second memory stores second configuration information. The first configuration information configures the transmission link's transmission rate to a first transmission rate, and the second configuration information increases the transmission link's transmission rate from the first transmission rate to a second transmission rate. The method includes: The processor reads the first configuration information from the first memory and sends the first configuration information to the link training module; wherein, the first configuration information includes first enable information, the first enable information representing whether the state machine is enabled, and the state machine is used to control the link training module to perform link training. When the first enable information indicates that the state machine is not enabled, the processor reads the second configuration information from the second memory and sends the second configuration information to the link training module. The second memory is a non-volatile memory. The link training module receives the first configuration information and the second configuration information, performs link training on the transmission link based on the first configuration information to make the transmission rate of the transmission link approach the first transmission rate, and performs link training on the transmission link based on the second configuration information to improve the transmission rate of the transmission link to make the transmission rate of the transmission link approach the second transmission rate.

10. The method according to claim 9, characterized in that, The link training module includes at least one first register, and the second configuration information includes at least one second sub-information, each second sub-information including the register address of a first register and the value to be written to the first register; The step of reading the second configuration information from the second memory through the processor and sending the second configuration information to the link training module includes: The processor reads the i-th second sub-information from the second memory and sends the value of the i-th second sub-information to the first register indicated by the register address in the i-th second sub-information; The link training module receives the second configuration information, including: The value of the i-th second sub-information is stored in the first register indicated by the register address in the i-th second sub-information, where i is a positive integer not greater than the number of the second sub-information.

11. The method according to claim 10, characterized in that, The second memory is also used to store quantity information, which indicates the quantity of the second sub-information; The step of reading the i-th second sub-information from the second memory via the processor includes: The processor reads the quantity information from the second memory, and if the quantity indicated by the quantity information meets the conditions, it reads the i-th second sub-information from the second memory.

12. The method according to claim 10, characterized in that, The link training module includes a second register and a link training unit. The link training unit includes at least one first register. The second register is connected to the processor and the link training unit. The method further includes: The processor writes a first reset signal into the second register, and the first reset signal is used to reset the link training unit. The first reset signal is stored in the second register; The link training unit reads the first reset signal from the second register and performs a reset operation based on the first reset signal. The step of reading the i-th second sub-information from the second memory via the processor includes: If the link training unit is successfully reset, the processor reads the i-th second sub-information from the second memory.

13. The method according to claim 10, characterized in that, The PCIe device also includes a third memory, which is connected to the processor; The step of reading the i-th second sub-information from the second memory via the processor includes: The processor reads the second configuration information from the second memory and sends the second configuration information to the third memory. The second configuration information is stored in the third memory; The processor reads the i-th second sub-information from the third memory.

14. The method according to any one of claims 9 to 13, characterized in that, The link training based on the first configuration information and the second configuration information includes: The processor sends a second enable message to the link training module. The second enable message indicates whether the state machine is enabled. The state machine is used to control the link training module to perform link training. The link training module performs link training on the transmission link based on the first configuration information and the second configuration information, when the state machine is enabled by the second enabling information.

15. The method according to any one of claims 9 to 13, characterized in that, The first configuration information includes at least one first sub-information, and the link training module includes a distribution unit and at least one third register, wherein the distribution unit is connected to the processor and the at least one third register; Receiving the first configuration information through the link training module includes: The distribution unit receives the at least one first sub-information and distributes the at least one first sub-information to the at least one third register. Each first sub-information is stored in each third register.

16. The method according to any one of claims 9 to 13, characterized in that, The PCIe device also includes a fourth register, which is connected to the processor and the link training module. The method further includes: The processor writes a second reset signal into the fourth register, and the second reset signal is used to reset the link training module. The second reset signal is stored in the fourth register; The link training module reads the second reset signal from the fourth register and performs a reset operation based on the second reset signal. The step of reading the first configuration information from the first memory via the processor includes: If the link training module is successfully reset, the processor reads the first configuration information from the first memory.

17. A chip, characterized in that, The chip includes a PCIe device as described in any one of claims 1 to 8.

18. An electronic device, characterized in that, The electronic device includes the chip as described in claim 17.

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