A network-on-chip system, a data transmission method, an electronic device and a storage medium

Abstract

The present disclosure relates to the technical field of computer, and particularly relates to an on-chip network system and a data transmission method, an electronic device and a storage medium, the system comprising a master port, a router and a slave port, at least one of the master port and the router being provided with a buffer, wherein: a first master port transmits first data to the slave port based on a first transmission path, the first transmission path comprising a first router; a second master port transmits second data to the slave port based on a second transmission path, in the case that the second transmission path comprises the first router and the first router is transmitting the first data, the second data is temporarily stored in the buffer of the first router and / or an upstream node of the first router in the second transmission path; and the first router transmits the second data temporarily stored in the buffer to the slave port in the interval of the first master port transmitting the first data. The embodiment of the present disclosure can effectively improve the link utilization rate.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an on-chip network system and data transmission method, electronic device and storage medium. Background Technology

[0002] Network-on-Chip (NoC) has become the core interconnect architecture for enabling efficient communication between multiple processing cores and memory units in complex Systems-on-Chip (SoCs). NoC includes various topologies, with common topologies such as Mesh, Torus, and Butterfly.

[0003] In existing NoC topologies, to save chip area, wiring is often minimized, which can lead to multiple data transmission paths sharing a single node. That is, multiple independent data transmission tasks (e.g., from the first master port to the first slave port, and from the second master port to the second slave port) need to share the same router node on their transmission paths. This situation is particularly severe in Butterfly-structured NoCs.

[0004] Once a shared router is occupied by a data transmission task, that task often needs to transmit multiple data packets in stages, while other transmission tasks that need to pass through this router must wait for the current task to finish. This congestion leads to data transmission delays and reduced throughput. Summary of the Invention

[0005] In view of this, this disclosure proposes an on-chip network system, including at least two master ports, at least one router, and at least one slave port, wherein the master ports, router, and slave ports are connected by links, and at least one of the master ports and the router is provided with a buffer, wherein:

[0006] The first master port transmits first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router;

[0007] The second main port transmits second data to the slave port based on the second transmission path. If the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path.

[0008] The first router, during the interval of transmitting the first data on the first main port, acquires the second data temporarily stored in the buffer and transmits it to the slave port.

[0009] In one possible implementation, if the second data temporarily stored in the buffer forms a logically complete data packet, the first router interrupts the data transmission on the first master port and retrieves the second data temporarily stored in the buffer to transmit to the slave port.

[0010] In one possible implementation, if the transmission of the first data is interrupted, the first main port temporarily stores the subsequently received first data in the buffer of the first router and / or the upstream node of the first router in the first transmission path.

[0011] In one possible implementation, the first router, while transmitting logically complete second data, if the first data in the buffer forms a logically complete data packet, continues to transmit the second data, and transmits the first data after the second data transmission is completed.

[0012] In one possible implementation, the first router, while transmitting first data and receiving a data transmission request from the second main port, sends a first waiting signal to the upstream node of the second transmission path;

[0013] Upon receiving the first waiting signal, the upstream node temporarily stores the second data in its own buffer in response to the first waiting signal.

[0014] In one possible implementation, if the buffer of the first router is unavailable while it is transmitting the first data and receives a data transmission request from the second main port, the first router sends a second waiting signal to the directly connected upstream node of the second transmission path.

[0015] If the directly connected upstream node is also unavailable, it continues to send a second waiting signal to its own directly connected upstream node until the second waiting signal reaches the target node that can temporarily store data.

[0016] The target node, in response to the second waiting signal, temporarily stores the second data in its own buffer.

[0017] In one possible implementation, the buffer's capacity is configured to store at least one logically complete data packet, which consists of N physical data packets transmitted, where N is a positive integer.

[0018] The capacity of the buffer is configured as the product of the number of transmissions N and the maximum data size of the physical data packet in a single transmission.

[0019] According to another aspect of this disclosure, a data transmission method is provided, applied to any of the above-described on-chip network systems, the on-chip network system including at least two master ports, at least one router, and at least one slave port, the master ports, router, and slave ports being connected via links, and at least one of the master ports and the router being provided with a buffer, the method comprising:

[0020] The first master port transmits first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router;

[0021] The second main port transmits second data to the slave port based on the second transmission path. If the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path.

[0022] The first router, during the interval of transmitting the first data on the first main port, acquires the second data temporarily stored in the buffer and transmits it to the slave port.

[0023] According to one aspect of this disclosure, an electronic device is provided, including: any of the above-described on-chip network systems.

[0024] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0025] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0026] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0027] In this embodiment of the disclosure, when the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path. During the interval between the transmission of the first data at the first primary port, the temporarily stored second data is retrieved from the buffer and transmitted to the secondary port. This allows the network to maintain partial data transmission capacity during path conflicts, rather than being completely blocked. By utilizing the intervals naturally generated during the transmission of the first data, the system can effectively improve link utilization and reduce latency caused by resource contention.

[0028] In this way, the second data utilizes the inherent bubble in the transmission of the first data to quickly jump the queue, without waiting for the entire path to be completely idle or requiring additional physical channels. During the jumping process, the first data is only delayed by a few cycles, but the overall idle time that would otherwise be unusable is eliminated, thus improving link utilization. Although this disclosure does not add additional physical channels, its transmission efficiency is equivalent to transmitting data in addition to the original normal channel, while also adding a past channel for data transmission. The jumping behavior is triggered only when the bubble exists and does not compromise the integrity of the first data. Subsequent downstream nodes can still receive and reassemble all the data packets of the first data in order, ensuring transmission correctness while achieving lower average latency.

[0029] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0031] Figure 1 This is an architecture diagram of an on-chip network system provided in an embodiment of this disclosure.

[0032] Figure 2 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown.

[0033] Figure 3 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown.

[0034] Figure 4 An architecture diagram of an on-chip network system according to an embodiment of the present disclosure is shown.

[0035] Figure 5 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown.

[0036] Figure 6 This is a block diagram illustrating an apparatus for data transmission according to an exemplary embodiment. Detailed Implementation

[0037] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0038] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0039] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0040] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0041] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0042] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0043] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0044] As mentioned earlier, existing on-chip networks are prone to congestion when multiple data transmission tasks share the same router due to the uniqueness of the path, resulting in increased network latency, decreased throughput, and reduced reliability.

[0045] like Figure 1 As shown, Figure 1This diagram illustrates an architecture of an on-chip network system provided in an embodiment of this disclosure. Taking the Butterfly structure as an example, it shows that each input port (0 to 7 on the left) is connected to an output port (0 to 7 on the right) through a series of routers. In this structure, router nodes (such as 00, 01, 10, etc.) play a crucial intermediary role, responsible for forwarding data from the input ports to the corresponding output ports. However, due to the reduction in cabling, these router nodes often become common points for multiple data transmission paths.

[0046] Specifically, suppose there are two independent data transmission tasks: one is to transmit data from the first master port (e.g., port 0 on the left) to the first slave port (e.g., port 0 on the right), and the other is to transmit data from the second master port (e.g., port 1 on the left) to the second slave port (e.g., port 1 on the right). Both tasks may need to pass through the same router node, such as router 00, along their transmission paths.

[0047] In this scenario, if one data transmission task (such as the task from the first master port to the first slave port) has already started using router 00, then the other task (the task from the second master port to the second slave port) must wait until router 00 is released. This waiting causes a delay in data transmission because the second task cannot proceed simultaneously; it must wait for the first task to complete before it can begin.

[0048] Furthermore, this congestion can also lead to a decrease in the overall network throughput. Throughput refers to the amount of data a network can process per unit of time. When multiple tasks have to wait because they share a router node, the overall data processing capacity of the network is affected, resulting in reduced throughput.

[0049] This situation is particularly pronounced in Butterfly-structured NoC architectures because this structure is designed to minimize cabling, making it easier for multiple paths to share the same router node. In other topologies such as mesh and ring lights, situations can also arise where all paths are occupied, causing new transmission tasks to wait, leading to reduced throughput.

[0050] Figure 2 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown. Figure 2 As shown in the diagram, this illustrates a typical master-slave architecture. This architecture includes a master port, a router, and a slave port. The master port connects to the master device, and the slave port connects to the slave device.

[0051] The master device is the party that initiates communication and is responsible for generating the data to be transmitted. In a NoC system, the master device may be a processor core or a module that initiates the request.

[0052] The master port is the interface between the master device and the NoC system. It is responsible for packaging the data generated by the master device and sending it to the NoC system via a router. The master port typically contains the necessary logic and buffers to support data serialization and buffering.

[0053] A router is a key component in a NoC system. It is responsible for forwarding data from one port to another based on the destination address of the data packets. It can forward data packets from different ports to the correct output port. In a NoC system, there are often multiple routers, and a single transmission path may contain more than a dozen routers.

[0054] The slave port is another interface in a NoC system, located on the slave device side. The slave port is responsible for receiving data packets from the router and passing them to the slave device.

[0055] A slave device is the receiving party in a communication process. It can be a storage unit, a processing core, or any module that needs to receive data. The slave device receives data through a port and performs corresponding operations, such as storing data or processing instructions.

[0056] During data transmission, a complete data transmission path is initiated by the master device, transmitted through the master port and router, and finally reaches the slave device. This architecture is used in NoC systems to achieve efficient communication between multiple processing cores and storage units. In the embodiments disclosed herein, by setting buffers at critical nodes, data flow can be effectively managed, transmission latency can be reduced, and the overall network performance can be improved.

[0057] Figure 3 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown. Figure 3 As shown, Figure 3This paper demonstrates the topology of an on-chip network system based on the Butterfly architecture. This structure includes multiple master ports (Mst0_port, Mst1_port, Mst2_port, Mst3_port) and slave ports (Slv0_port, Slv1_port, Slv2_port, Slv3_port), which are interconnected via a router. Each master port and slave port is connected to the master device (Mst0, Mst1, Mst2, Mst3) and the slave device (Slv0, Slv1, Slv2, Slv3), respectively.

[0058] exist Figure 3 In the architecture shown, the data transmission paths are predetermined, and each master port has a unique path to its corresponding slave port. For example, Mst0_port is directly connected to Slv0_port via a series of routers. This design reduces wiring and saves chip area, but multiple data transmission tasks may share the same router node.

[0059] For example, suppose there are two independent data transfer tasks: transferring data from Mst0 to Slv0; and transferring data from Mst1 to Slv1. Under normal circumstances, these two tasks can be performed in parallel because they transfer data through different paths. However, a problem arises if the Mst0 to Slv0 transfer task initially uses the first router, and the Mst1 to Slv1 transfer task also needs to pass through this router.

[0060] When the first router is occupied by the Mst0 to Slv0 transmission task, the Mst1 to Slv1 transmission task must wait. This waiting will cause a delay in data transmission because Mst1 cannot start transmitting at the same time and must wait for Mst0's task to complete before it can start.

[0061] If both Mst0_port and Mst1_port need to transmit data through the same router (such as the router in the upper left of the diagram), then this router will become a bottleneck. If this router is processing data transmission from Mst0_port, then data transmission from Mst1_port must wait until the router has completely finished transmitting from Mst0_port.

[0062] Based on this, this disclosure proposes an improved on-chip network system. By setting buffers at key nodes to temporarily store data and transmitting the temporarily stored data during the router's transmission intervals, time bubbles in data transmission can be effectively eliminated, data transmission latency reduced, and on-chip network performance improved. The system structure, workflow, and technical effects of this disclosure will be described in detail below with reference to the accompanying drawings and through several embodiments.

[0063] Figure 4 An architecture diagram of an on-chip network system according to an embodiment of the present disclosure is shown. Figure 4 As shown, the on-chip network system 10 includes at least two master ports 11, at least one router 12, and at least one slave port 13. The master ports, routers, and slave ports are connected by links. At least one of the master ports and the routers is equipped with a buffer 14, wherein:

[0064] The first master port 11-1 transmits first data to the slave port 13 based on the first transmission path, wherein the first transmission path includes the first router 12-1;

[0065] The second main port 11-2 transmits the second data to the slave port 13 based on the second transmission path. If the second transmission path includes the first router 1211 and the first router 12-1 is transmitting the first data, the second data is temporarily stored in the buffer of the first router 121 and / or the upstream node of the first router 12-1 in the second transmission path.

[0066] The first router 12-1, during the interval of transmitting the first data on the first main port 11-1, acquires the second data temporarily stored in the buffer and transmits it to the slave port.

[0067] The on-chip network system 10 may include at least two master ports 11, at least one router 12, and at least one slave port 13. The master device, as the starting point for data transmission in the network, is used to generate data to be transmitted and control the initiation of data transmission. Master port 11 serves as the interface between the master device and the network, used to connect data generated by the master device to the network transmission link. Slave port 13 serves as the interface between the network and the slave device, used to receive data transmitted from the network. The slave device, as the endpoint of data transmission, is used to process or store the received data.

[0068] The main port 11, router 12, and slave port 13 are interconnected via physical or logical links to form a data transmission channel. These links support the transmission of data packets and control signals and allow status interaction between nodes.

[0069] A buffer 14 is provided at least in one of the main port 11 and the router 12. The buffer 14 serves as a temporary storage unit, providing temporary storage space when data cannot be immediately transmitted to downstream nodes, preventing data loss due to path congestion, and providing flexibility for data scheduling.

[0070] During system operation, the first master device initiates data transmission to a slave device through the first master port 11-1, forming the first transmission path. This path includes the first router 12-1, which is located between the first master port 11-1 and the slave port, and is responsible for receiving and forwarding the first data. Multiple routers can be located between the first master port and the slave port, which will not be elaborated here.

[0071] When the first router 12-1 is processing the first data, if the second transmission path initiated by the second master device through the second master port 11-2 also needs to pass through the first router 12-1, the system can temporarily store the second data in the buffer of the first router 12-1, or in the buffer of a node upstream of the first router 12-1 in the second transmission path. Subsequently, the first router 12-1 can retrieve and forward the temporarily stored second data from the buffer during the idle period of transmitting the first data.

[0072] It should be noted that the first primary port and the second primary port are different ports among the at least two primary ports, the first router is a router among the at least one router, and the first router is a router shared by the first transmission path and the second transmission path. The slave ports in the first transmission path and the second transmission path can be the same port among the at least one slave port, or they can be different ports.

[0073] In practical implementations, buffers can be integrated into the master port or router, or into the slave port, as part of the data path. Buffers receive data from upstream nodes and pass the data to downstream nodes when output conditions are met. Each buffer can have independent storage read / write control logic, enabling it to dynamically adjust data access timing based on network conditions.

[0074] The buffer can manage data storage according to the first-in, first-out (FIFO) principle, maintaining the integrity of data packet order. The buffer's storage space can be divided into multiple storage units, each used to store data for one basic transmission unit. For example, the buffer can consist of a register array, a small static random access memory, or a chain of triggers, and its depth can be configured according to network load characteristics, as detailed in the possible implementations provided in this disclosure.

[0075] The operating status of the buffer can be characterized by corresponding status signals. When the remaining space of the buffer is lower than the threshold, a backpressure signal can be sent to the adjacent upstream node to notify it to suspend data transmission.

[0076] When temporarily storing the second data, if the buffer of the first router itself is available, the second data can be directly temporarily stored in the buffer of the first router; if the buffer of the first router is unavailable (e.g., full or busy), the second data is temporarily stored in the buffer of the upstream node. For details, please refer to the possible implementation methods provided in this disclosure, which will not be elaborated here.

[0077] Upstream nodes are network devices that are closer to the source in the direction of data transmission, such as intermediate routers between the first main port and the first router, or the first main port itself. These nodes are equipped with buffers to provide space for temporary data storage.

[0078] In on-chip networks, the initial data is often broken down into several packets and sent sequentially. These packets need to wait for routing calculations, arbitration responses, and link establishment. These waiting periods manifest as discontinuous transmission windows, or bubbles. Whenever a packet leaves the current router before the next packet arrives, the output port experiences a brief idle period, during which the link is not utilized for effective data transmission.

[0079] The second data is buffered in the buffer closest to the shared router before being sent. When the controller detects that the transmission window of the first data is idle, it immediately reads the header data packet of the second data and initiates forwarding. Since the second data is already in a ready state, it does not need to go through the request, arbitration and establishment process. Therefore, it can occupy the link and jump the queue within one clock cycle.

[0080] Once queue interruption begins, scheduling of subsequent data packets for the first data can be paused, and the first router can be temporarily allocated to the second data. Once the tail data packet of the second data leaves the router, reading of the first data can be resumed, and the previously interrupted transmission can continue.

[0081] For example, the first master device can be a central processing unit core, and its target slave device can be a shared memory unit; the second master device can be an image processing unit, and its target slave device can be a display controller. When both need to communicate through the first router, this system uses a buffering and scheduling mechanism to enable image data to be forwarded during the gaps in processor data transmission, thereby improving overall network throughput and real-time response.

[0082] In this embodiment of the disclosure, when the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path. During the interval between the transmission of the first data at the first primary port, the temporarily stored second data is retrieved from the buffer and transmitted to the secondary port. This allows the network to maintain partial data transmission capacity during path conflicts, rather than being completely blocked. By utilizing the intervals naturally generated during the transmission of the first data, the system can effectively improve link utilization and reduce latency caused by resource contention.

[0083] In this way, the second data utilizes the inherent bubble in the transmission of the first data to quickly jump the queue, without waiting for the entire path to be completely idle or requiring additional physical channels. During the jumping process, the first data is only delayed by a few cycles, but the overall idle time that would otherwise be unusable is eliminated, thus improving link utilization. Although this disclosure does not add additional physical channels, its transmission efficiency is equivalent to transmitting data in addition to the original normal channel, while also adding a past channel for data transmission. The jumping behavior is triggered only when the bubble exists and does not compromise the integrity of the first data. Subsequent downstream nodes can still receive and reassemble all the data packets of the first data in order, ensuring transmission correctness while achieving lower average latency.

[0084] In one possible implementation, if the second data temporarily stored in the buffer forms a logically complete data packet, the first router interrupts the data transmission on the first master port and retrieves the second data temporarily stored in the buffer to transmit to the slave port.

[0085] The second data is also split into several data packets during transmission and sent sequentially. To distinguish them from logically complete data packets, these split data packets are referred to as physical data packets. A logically complete data packet represents an independent transmission transaction, and downstream slave ports can respond based on this transaction without waiting for subsequent physical data packets. A logically complete data packet can contain multiple physical data packets. These physical data packets contain complete header and footer identifiers, routing information, and payload data units. Slave devices can process logically complete data packets independently without waiting for subsequent physical data packets.

[0086] The physical data packets obtained after the second data split are written to the buffer sequentially along the second transmission path. Each transmission corresponds to a physical data packet, and the buffer records the packet sequence number and tail identifier during the writing process. When the tail identifier is carried by the physical data packet of the Nth transmission, the buffer concatenates the physical data packets of the previous N transmissions in order to form a logically complete data packet.

[0087] In one example, a logically complete data packet consists of 64 transmitted physical data packets, each 256 bits long; in another example, a logically complete data packet consists of 128 transmitted physical data packets, each 512 bits long. Regardless of the value of N, once the Nth transmitted physical data packet is written to the buffer, the buffer combines all stored physical data packets into a logically complete data packet and sends a readiness signal to the first router, enabling the first router to retrieve the data packet and forward it downstream.

[0088] If the second data temporarily stored in the buffer forms a logically complete data packet, the first router interrupts data transmission on the first master port and retrieves the second data temporarily stored in the buffer to transmit to the slave port. The interruption process is executed by the scheduler inside the first router: after the scheduler detects the ready indicator signal, it suspends reading physical data packets from the first master port, allocates the first router to the second data, and then reads all physical data packets in the buffer sequentially and sends them downstream; when the last physical data packet is sent, the transmission of the previously suspended first data can be resumed.

[0089] In this embodiment of the disclosure, by adopting a dynamic scheduling mechanism based on data packet integrity, the on-chip network system can interrupt the data transmission of the first master port through the first router when the second data temporarily stored in the buffer forms a logically complete data packet, and obtain the second data temporarily stored in the buffer to transmit to the slave port, thereby effectively reducing the transmission delay of the complete data packet, enabling the slave device to receive the complete data packet first and perform service processing, and improving the slave device's ability to process real-time services.

[0090] In one possible implementation, if the transmission of the first data is interrupted, the first main port temporarily stores the subsequently received first data in the buffer of the first router and / or the upstream node of the first router in the first transmission path.

[0091] In an on-chip network system, when the first data being transmitted by the first master port is interrupted by the first router, the first master port can adjust its subsequent data processing flow. At this time, the first master port temporarily stores the subsequently received first data in a buffer unit in the network. These buffer units can be located in the first router itself or in other nodes upstream of the first router in the first transmission path.

[0092] When the first router interrupts the transmission of the first data, it will notify the upstream node through the corresponding control mechanism. After receiving the interruption indication, the first main port will no longer send subsequent data directly to the already occupied transmission path, but will instead guide it to an available buffer space for temporary storage. The specific location of temporary storage depends on the availability and load of each buffer in the network, and can be found in the possible implementation methods provided in this disclosure, which will not be elaborated here.

[0093] In this embodiment of the disclosure, when the first main port is interrupted in transmitting the first data, the subsequently received first data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the first transmission path. This allows the system to maintain the integrity of data transmission while flexibly responding to temporary interruptions in the transmission path. Subsequently, when the second data transmission is completed, the system can quickly read the data from the buffer to resume the transmission of the first data. The first router does not need to initiate a handshake with the first main port again, nor does it need to spend time establishing a transmission link with the first main port. Therefore, there are no transmission bubbles, thereby improving the overall transmission efficiency and reliability.

[0094] In one possible implementation, the first router, while transmitting logically complete second data, if the first data in the buffer forms a logically complete data packet, continues to transmit the second data, and transmits the first data after the second data transmission is completed.

[0095] In an on-chip network system, while the first router is transmitting logically complete second data, the system can continuously monitor the data status of other buffers in the network. At this time, if the first data in the buffers of the first router or other nodes happens to form a logically complete data packet, the first router can maintain the current second data transmission process until it is completed, without immediately switching to the transmission of the first data.

[0096] In this scenario, the first router employs a sequential scheduling strategy. Even if the first data has formed a complete data packet, the first router will still prioritize completing the currently ongoing second data transmission task. Completing the entire transmission process of the second data helps avoid the overhead of frequent task switching while ensuring the integrity of each data transmission task.

[0097] For example, when the first router is transmitting a complete frame of data from the image processing unit, if the processor request data in the buffer also forms a complete data packet at this time, the first router will continue to complete the transmission of the current frame of data before starting to transmit the processor request data. In another example, assuming the second data is a critical instruction packet from the storage controller and the first data is a batch data block, this scheduling method can ensure that the complete transmission of critical instructions is not interrupted.

[0098] In this embodiment, when the first router is transmitting logically complete second data, if the first data in the buffer forms a logically complete data packet, the second data is continuously transmitted. After the second data transmission is completed, the first data is transmitted. This allows the system to maintain the integrity of the transmission task while effectively avoiding efficiency losses caused by frequent task switching. This sequential scheduling strategy helps reduce transmission fragmentation, improves link utilization, and ensures that each complete data packet has a continuous transmission opportunity, thereby improving overall network throughput and transmission efficiency, especially exhibiting good performance stability when processing multiple real-time data streams.

[0099] In one possible implementation, the first router, while transmitting first data and receiving a data transmission request from the second main port, sends a first wait signal to the upstream node of the second transmission path; the upstream node receiving the first wait signal, in response to the first wait signal, temporarily stores the second data in its own buffer.

[0100] The first wait signal is a flow control signal used to coordinate data transmission. This signal is generated by the router under specific conditions to notify upstream nodes to adjust their data transmission behavior. An upstream node refers to a network device located closer to the source of the signaling node on the data transmission path, such as a main port or intermediate router located before the first router in a second transmission path.

[0101] When the first router is transmitting the first data and simultaneously receives a data transmission request from the second main port, the first router can send a first wait signal to the upstream node of the second transmission path. This signal indicates that the first router cannot process the second data immediately and the upstream node needs to postpone data transmission.

[0102] Upon receiving the first wait signal, the upstream node will perform the corresponding operation as indicated by the signal. Specifically, the upstream node will respond to the first wait signal by temporarily storing the second data to be transmitted in its own buffer.

[0103] The buffer of the upstream node itself, which is used for the second data temporary storage, is a buffer integrated or connected to the node that directly receives the first waiting signal. This buffer, physically and logically, forms a unified control unit with the node and is the core component for the node to perform data scheduling and management. Each network device processes the first waiting signal sent to its local machine and independently makes decisions and actions based on the state of its own buffer.

[0104] The first wait signal propagates upstream hop by hop along the transmission path, against the direction of data transmission. Each time the first wait signal arrives at an upstream node, the node's control logic checks the current state of its own buffer. If the response conditions required by the signal are met, the node will activate its internal data path control logic, intercepting the subsequent arrival of the second data that should have been forwarded downstream, and storing it in its own buffer space.

[0105] For example, in a transmission path consisting of a second master device, router A, and a first router, if the first router sends a first wait signal to router A because it is transmitting the first data, then router A will immediately store the subsequent second data packet in its own buffer after receiving the signal.

[0106] By proactively sending control signals upstream when the first router detects congestion risk, the system can achieve forward transmission of pressure. Upon receiving the signal, upstream nodes promptly adjust their data transmission behavior to avoid sending data to already congested nodes, thus forming an effective congestion control closed loop.

[0107] For example, when the first router is processing a long data stream from the processor core, if the image processing unit simultaneously initiates a data transmission request, the first router can send a first wait signal to the main port corresponding to the image processing unit. After receiving the signal, the main port will temporarily store the image data to be transmitted in its local buffer.

[0108] In another example, if there are multiple intermediate routers on the second transmission path, the first router can send a first wait signal to its directly connected upstream router, and then the router will temporarily store the second data in its own buffer.

[0109] In this embodiment of the disclosure, when the first router is transmitting the first data and receives a data transmission request from the second main port, it sends a first waiting signal to the upstream node of the second transmission path. The upstream node that receives the first waiting signal responds to the first waiting signal and temporarily stores the second data in its own buffer, so that the system can achieve effective forward congestion control and avoid data accumulation or loss at congested nodes.

[0110] In one possible implementation, if the buffer of the first router is unavailable while it is transmitting the first data and receives a data transmission request from the second main port, the first router sends a second waiting signal to the directly connected upstream node of the second transmission path. If the buffer of the directly connected upstream node is also unavailable, the directly connected upstream node continues to send the second waiting signal to its own directly connected upstream node until the second waiting signal reaches the target node that can temporarily store the data. In response to the second waiting signal, the target node temporarily stores the second data in its own buffer.

[0111] The second wait signal is generated by the first router when its output port is occupied and its own buffer is unavailable. This signal is transmitted between adjacent nodes on the transmission path to coordinate data caching among multiple nodes, specifically the target node whose buffer is available. A directly connected upstream node is a device in the network topology that is directly connected to the current node and closer to the data source, such as the router upstream of the first router or its main port.

[0112] When the first router is transmitting the first data and simultaneously receives a data transmission request from the second main port, if the first router's own buffer is unavailable, it can send a second wait signal to the directly connected upstream node on the second transmission path. This signal indicates that the current node's buffer is unavailable or does not exist, and the upstream node needs to temporarily store the data.

[0113] Upon receiving the second waiting signal, the directly connected upstream node first determines whether it has a buffer or checks the availability of its own buffer. If the node does not have a buffer, or its buffer is full or unavailable, it will continue to forward the second waiting signal to its directly connected upstream nodes. This signal transmission process can continue, forming a cascading backpressure transmission mechanism, until the signal reaches a target node with available buffer space.

[0114] The target node is the network device that ultimately receives and responds to the second wait signal, and it has available buffer space. When the second wait signal arrives at the target node, the target node will respond to the signal indication and temporarily store the second data to be transmitted in its own buffer, waiting for a subsequent transmission opportunity.

[0115] In a specific scenario, assuming the second transmission path includes three levels of routers, if the buffers of all three routers are unavailable, the second waiting signal can start from the first router and be passed level by level until it reaches the second main port, where the second main port temporarily stores the second data in its local buffer.

[0116] In this embodiment, when the first router is transmitting first data and receives a data transmission request from the second main port, if the buffer of the first router is unavailable, it sends a second waiting signal to the directly connected upstream node of the second transmission path. If the directly connected upstream node's own buffer is also unavailable, it continues to send the second waiting signal to its own directly connected upstream node until the second waiting signal reaches the target node that can temporarily store the data. The target node responds to the second waiting signal and temporarily stores the second data in its own buffer, enabling the system to achieve effective distributed buffer resource management, avoiding overall performance degradation caused by local congestion, and optimizing the utilization efficiency of global buffer resources, especially exhibiting good fault tolerance and stability under high load conditions.

[0117] In one possible implementation, the buffer's capacity is configured to store at least one logically complete data packet, which consists of N physical data packets transmitted, where N is a positive integer; the buffer's capacity is configured as the product of the number of transmissions N and the maximum data size of a single physical data packet.

[0118] The buffer capacity configuration needs to take into account the actual transmission characteristics of the data packets. A logically complete data packet is a data unit with complete semantics at the protocol layer. It is the basic data unit for business processing by the device and usually includes a start identifier, routing information, payload, and end identifier. During transmission, it may be split into multiple physical data packets for transmission.

[0119] A physical data packet is the basic unit of network transmission, and its size is usually determined by the link bandwidth or protocol specifications. A logically complete data packet can be composed of N physical data packets, where N is a positive integer. Each physical data packet contains part of the content of the logical data packet, and all physical data packets must be combined in sequence to reconstruct a complete logical data packet.

[0120] In this implementation, the buffer capacity configuration needs to meet the requirement of storing the entire logical data packet. Specifically, the buffer capacity can be set as the product of the number of transmissions N and the maximum data size of the physical data packet in a single transmission, to ensure that the buffer can hold at least one complete logical data packet, providing the necessary storage space for data scheduling.

[0121] The buffer capacity configuration method disclosed herein is based on the consideration of data packet integrity. By allocating sufficient storage space to each buffer, it can be ensured that logical data packets are not fragmented and stored in different buffers during transmission. This allows data packets to maintain their integrity when encountering transmission conflicts or needing temporary storage, facilitating subsequent scheduling and transmission.

[0122] For example, if a logical data packet consists of 4 physical data packets, and the maximum data size of each physical data packet is 64 bytes, then the buffer capacity can be configured to 256 bytes.

[0123] In a specific application scenario, when the processor initiates a cache line read request, the corresponding logical data packet may contain 8 physical data packets, each of which can carry up to 64 bits of data. In this case, the buffer capacity can be configured to 512 bytes.

[0124] In this embodiment, the buffer capacity is configured to store at least one logically complete data packet, which consists of N transmitted physical data packets. The buffer capacity is configured as the product of the number of transmissions N and the maximum data size of a single transmitted physical data packet. This allows the system to provide sufficient temporary storage space for complete data packets, ensuring the integrity of the data packets during transmission. This enables network nodes to effectively handle the temporary storage and forwarding of logical data packets, avoiding packet fragmentation or transmission congestion due to insufficient buffer capacity, thereby improving the reliability and efficiency of data transmission.

[0125] In the on-chip network system provided in this disclosure, the slave port can also be equipped with a buffer to optimize the integrity and efficiency of data transmission. The slave port buffer is used to temporarily store incoming data, providing buffer space for data reception by the slave device and ensuring that data can still be reliably received when the slave device's processing capacity is limited.

[0126] When data packets arrive at the target slave port via network transmission, the slave device may not be able to receive the data immediately due to processing other tasks. At this time, the slave port buffer can temporarily store these arriving data packets to prevent data loss due to the receiver not being ready. This allows the slave device to obtain data at its own pace without having to maintain strict real-time synchronization with the network transmission.

[0127] The buffer at the slave port also helps to smooth out bursts of data traffic. When multiple packets arrive at the same slave port almost simultaneously, the buffer provides queuing space, allowing the packets to be processed by the slave device in order. This buffered queuing mechanism is particularly suitable for handling concurrent data access requests from different sources, ensuring the sequential integrity of data processing.

[0128] For example, when the slave device is a memory controller, the slave port buffer can temporarily store memory access request packets from multiple processor cores, enabling the memory controller to process these requests in an orderly manner. In another example, if the slave device is a display controller, the slave port buffer can store image data frames that are about to be displayed, ensuring the continuity and stability of the display output.

[0129] Furthermore, the port buffer also works in conjunction with the flow control mechanism in the network. When the port buffer is nearing full capacity, it can notify the upstream node to slow down the data transmission rate through a reverse acknowledgment signal, forming an end-to-end flow control closed loop. This prevents data loss caused by buffer overflow and optimizes the overall network bandwidth utilization efficiency.

[0130] In this embodiment of the disclosure, by setting a buffer at the slave port directly connected to the slave device, the system can provide the last-level data buffer at the network transmission terminal, effectively alleviating the rate mismatch problem between the source and destination, and improving the reliability of data transmission and the overall system performance.

[0131] The following describes an embodiment of a specific application scenario provided in this disclosure, such as... Figure 5 As shown, Figure 5 A schematic diagram of a master-slave architecture according to an embodiment of the present disclosure is shown. Figure 5 As shown, Figure 5 The topology of an on-chip network system based on the Butterfly architecture is shown.

[0132] In the diagram, master devices 0, 1, 2, and 3 are connected to the router via master ports 0, 1, 2, and 3, respectively. The router connects to slave devices 0, 1, 2, and 3. The triangles inside the router represent buffers used to temporarily store data packets that have not yet been forwarded. The master ports, router, and slave ports are connected via links, forming a typical transmission path in a butterfly topology.

[0133] In an exemplary scenario, master device 0 sends first data to slave device 0, and master device 1 sends second data to slave device 1. The two transmission paths intersect within the router. When the first data occupies the router's output port first, the sub-packets of the second data are sequentially written into the buffer shown in the triangle. After the tail sub-packet of the first data leaves the output port, the router immediately reads the second data from the buffer and continues to forward it downstream. In this way, the router uses the buffer to absorb the waiting time caused by the intersection, allowing the second data to be transmitted in queue without adding extra physical channels, thereby reducing transmission bubbles and improving link utilization.

[0134] It's worth noting that in this example, a buffer can also be set up on the slave port to provide temporary storage space for received data. When the router completes forwarding and delivers the data packet to the slave port, if the slave device cannot immediately extract the entire payload within the current clock cycle, the slave port can sequentially write the arriving sub-packets into the buffer and continue maintaining the write pointer. Once the slave device completes its internal processing and releases the receive window, the slave port reads the sub-packets from the buffer in a first-in-first-out order and delivers them to the slave device's subsequent logic. Therefore, the downstream processing delay can be absorbed by the buffer on the slave port side, preventing reverse pressure from being passed to the router's output port, thus ensuring continuous data transmission throughout the entire transmission link and improving the overall system throughput.

[0135] According to another aspect of this disclosure, a data transmission method is provided, applied to any of the above-described on-chip network systems, the on-chip network system including at least two master ports, at least one router, and at least one slave port, the master ports, router, and slave ports being connected via links, and at least one of the master ports and the router being provided with a buffer, the method comprising:

[0136] The first master port transmits first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router;

[0137] The second main port transmits second data to the slave port based on the second transmission path. If the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path.

[0138] The first router, during the interval of transmitting the first data on the first main port, acquires the second data temporarily stored in the buffer and transmits it to the slave port.

[0139] According to another aspect of this disclosure, a data transmission apparatus is provided, applied to any of the above-described on-chip network systems, the on-chip network system including at least two master ports, at least one router, and at least one slave port, the master ports, router, and slave ports being connected via links, and at least one of the master ports and the router being provided with a buffer, the apparatus comprising:

[0140] The first transmitting module is used to control the first master port to transmit first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router;

[0141] The second sending module is used to control the second master port to transmit the second data to the slave port based on the second transmission path. When the second transmission path includes the first router and the first router is transmitting the first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path.

[0142] The transmission module is used to control the interval at which the first router transmits first data at the first master port, and to obtain the second data temporarily stored in the buffer and transmit it to the slave port.

[0143] According to one aspect of this disclosure, an electronic device is provided, including: any of the above-described on-chip network systems.

[0144] According to one aspect of this disclosure, an electronic device is provided, including: any of the above-described on-chip network systems.

[0145] In some embodiments, the specific implementation of the method provided in this disclosure can be referred to the description of the system embodiments above, and for the sake of brevity, it will not be repeated here.

[0146] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0147] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0148] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0149] Figure 6 This is a block diagram illustrating an apparatus for data transmission according to an exemplary embodiment. For example, apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 6 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0150] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0151] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0152] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0153] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0154] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0155] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0156] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0157] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0158] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0159] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An on-chip network system, characterized in that, It includes at least two master ports, at least one router, and at least one slave port, wherein the master ports, routers, and slave ports are connected by links, and at least one of the master ports and the router is equipped with a buffer, wherein: The first master port transmits first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router; The second main port transmits second data to the slave port based on the second transmission path. If the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path. The first router, during the interval of transmitting the first data on the first main port, acquires the second data temporarily stored in the buffer and transmits it to the slave port; The first router, while transmitting the first data and receiving a data transmission request from the second main port, sends a first waiting signal to the upstream node of the second transmission path; Upon receiving the first waiting signal, the upstream node temporarily stores the second data in its own buffer in response to the first waiting signal.

2. The system according to claim 1, characterized in that: If the second data temporarily stored in the buffer forms a logically complete data packet, the first router interrupts the data transmission on the first master port and retrieves the second data temporarily stored in the buffer to transmit to the slave port.

3. The system according to claim 1, characterized in that: In the event that the transmission of the first data is interrupted, the first main port will temporarily store the subsequently received first data in the buffer of the first router and / or the upstream node of the first router in the first transmission path.

4. The system according to claim 3, characterized in that: If the first data in the buffer forms a logically complete data packet while the first router is transmitting logically complete second data, it will continue to transmit the second data and transmit the first data after the second data transmission is completed.

5. The system according to claim 1, characterized in that: If the buffer of the first router is unavailable while it is transmitting the first data and receives a data transmission request from the second main port, the first router sends a second waiting signal to the directly connected upstream node of the second transmission path. If the directly connected upstream node is also unavailable, it continues to send a second waiting signal to its own directly connected upstream node until the second waiting signal reaches the target node that can temporarily store data. The target node, in response to the second waiting signal, temporarily stores the second data in its own buffer.

6. The system according to claim 1, characterized in that, The buffer is configured to store at least one logically complete data packet, which consists of N physical data packets transmitted, where N is a positive integer. The capacity of the buffer is configured as the product of the number of transmissions N and the maximum data size of the physical data packet in a single transmission.

7. A data transmission method, characterized in that, Applied to the on-chip network system according to any one of claims 1 to 6, the on-chip network system comprising at least two master ports, at least one router, and at least one slave port, wherein the master ports, router, and slave ports are connected via links, and at least one of the master ports and the router is provided with a buffer, the method comprising: The first master port transmits first data to the slave port based on the first transmission path, wherein the first transmission path includes the first router; The second main port transmits second data to the slave port based on the second transmission path. If the second transmission path includes the first router and the first router is transmitting first data, the second data is temporarily stored in the buffer of the first router and / or the upstream node of the first router in the second transmission path. The first router, during the interval of transmitting the first data on the first main port, acquires the second data temporarily stored in the buffer and transmits it to the slave port; The first router, while transmitting the first data and receiving a data transmission request from the second main port, sends a first waiting signal to the upstream node of the second transmission path; Upon receiving the first waiting signal, the upstream node temporarily stores the second data in its own buffer in response to the first waiting signal.

8. An electronic device, characterized in that, include: The on-chip network system according to any one of claims 1-6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method of claim 7.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 7.

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