A design method of RDL layer of integrated circuit back-end layout

Abstract

The application discloses a kind of RDL layer design methods of integrated circuit back-end layout, comprising the following steps: S1. digital back-end layout wiring data preparation: by establishing design base environment, for providing accurate physical basis for power network;S2. create bump: by optimizing power / ground bump physical layout, for power / ground network allocation provides structured carrier;S3. allocate power and ground attribute: by establishing power network logical division, for subsequent convex / concave RDL interlocking structure provides foundation;S4. with power bump as center planning corresponding RDL layer: by constructing power transmission backbone network, form low impedance power path;S5. with ground bump as center planning corresponding RDL layer: by constructing ground return network, to reduce power / ground loop area, inhibit noise coupling;S6. create power / ground RDL layer and through: by power or ground wire global through eliminating current bottleneck, realize global low impedance interconnection.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit design, and more specifically, to an RDL layer design method for the back-end layout of integrated circuits. Background Technology

[0002] As modern integrated circuit process nodes continue to evolve to advanced processes of 3nm and below, the number of transistors on a chip is increasing explosively, while the threshold voltage of transistors is constantly decreasing, making the design of power supply networks face increasingly stringent challenges. Parasitic voltage drop (IR drop) and electromigration (EM) effects in the power supply network are significantly aggravated, which not only leads to a decrease in chip timing performance, but also seriously threatens the long-term reliability and lifespan of devices.

[0003] As a key layer in the back-end layout of digital integrated circuits, the RDL (Redistribution Layer) undertakes the core function of efficiently interconnecting bumps, internal pads, and internal power supply networks. Its layout quality directly determines power integrity, signal integrity, and overall chip stability.

[0004] However, in current integrated circuit back-end design practices, the design methodology of the RDL layer lacks clear and systematic guidance, the design process is relatively vague, and it fails to fully consider universally applicable layout rules; the space layout utilization rate is generally low, failing to meet the maximum density requirements allowed by the manufacturing process; the power distribution efficiency is insufficient, the power path impedance is too high, which can easily cause local voltage fluctuations to exceed the process specifications, resulting in transistor operating point offset and functional abnormalities; in addition, uneven space layout leads to unbalanced current distribution, further exacerbating the risk of electromigration, increasing the possibility of short circuits or open circuits in metal lines, and ultimately affecting the stability and reliability of chip power supply.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] The purpose of this application is to provide an RDL layer design method for integrated circuit back-end layout, which improves the systematicness and space utilization of RDL layer layout, reduces power path impedance, reduces noise coupling, and improves current distribution uniformity, thereby enhancing power integrity and chip reliability.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0008] An RDL layer design method for integrated circuit back-end layout includes the following steps:

[0009] S1. Digital back-end layout and wiring data preparation:

[0010] By establishing a design foundation environment, an accurate physical basis is provided for power networks;

[0011] S2. Create a bump:

[0012] By optimizing the physical layout of power / ground bumps, a structured carrier is provided for power / ground network distribution;

[0013] S3. Assign power and ground attributes:

[0014] By establishing a logical partition of the power network, a foundation is laid for the interlocking structure of the subsequent convex / concave RDL;

[0015] S4. Plan the corresponding RDL layer with the power supply bump as the center:

[0016] By constructing a power transmission backbone network, a low-impedance power path is formed.

[0017] S5. Plan the corresponding RDL layer centered on the land bump:

[0018] By constructing a grounded return network, the power / ground loop area is reduced, and noise coupling is suppressed;

[0019] S6. Create and connect the power / ground RDL layer:

[0020] By globally connecting the power or ground wires, current bottlenecks are eliminated, achieving global low-impedance interconnection.

[0021] Furthermore, the specific method for step S1 is as follows:

[0022] Importing netlists, constraints, and process design documents; planning chip size; standard cell placement stage; I / O cell placement stage; and IP cell placement stage.

[0023] Furthermore, the specific method for step S2 is as follows:

[0024] Determine the number and shape of bumps according to process requirements, set the starting coordinates and X / Y direction spacing, set the placement type to horizontal staggered and diamond arrangement, set the staggered offset value according to the Pythagorean theorem, and set the full_chip mode.

[0025] Furthermore, the specific method for step S3 is as follows:

[0026] Select the odd-numbered item bump and assign it the power attribute to connect to the power RDL layer; select the even-numbered item bump and assign it the ground attribute to connect to the ground RDL layer.

[0027] Furthermore, the specific method for step S4 is as follows:

[0028] First, select the bump in the R45 direction and create a top-to-bottom symmetrical convex RDL layer with the center point. Surround the selected bump and form interconnections. Then, select the bump in the R135 direction and create a top-to-bottom symmetrical convex RDL layer with the center point. Surround the selected bump and form interconnections.

[0029] Furthermore, the specific method for step S5 is as follows:

[0030] Select the bump in the R45 direction and create a symmetrical concave RDL layer with the center point. Surround the selected bump and form interconnections. Select the bump in the R135 direction and create a symmetrical concave RDL layer with the center point. Surround the selected bump and form interconnections.

[0031] Furthermore, in step S5, the R45 direction bump refers to the ground bump at a 45° angle to the horizontal axis in the diamond arrangement, and the R135 direction bump refers to the ground bump at a 135° angle to the horizontal axis; by creating symmetrical concave RDL layers for the ground bumps in both orthogonal directions, the continuity and consistency of the omnidirectional grounding return path are achieved.

[0032] Furthermore, in step S5, the upper and lower symmetrical concave RDL layers are inwardly recessed metal interconnect structures that form a closed surrounding structure around the ground bump and interconnect with other RDL layers of the same properties to form a low-impedance ground return channel; the upper and lower symmetrical concave RDL layers and the convex structure of the power supply RDL layer form a physical interlock, reducing layout gaps and enhancing structural continuity.

[0033] Furthermore, the specific method for step S6 is as follows:

[0034] Configure the layers, lengths, widths, spacing, directions, starting coordinates, and starting direction sequences of power and ground lines to achieve global connectivity of power or ground lines through parameterized configuration.

[0035] Furthermore, the starting coordinates are symmetrically laid out with the chip's geometric center as the origin to ensure uniform current diffusion; the direction adopts a grid-like or radial routing strategy to reduce loop area; the starting direction sequence adopts an alternating routing strategy to avoid local overload and current concentration caused by dense routing of adjacent lines in the same direction; and finally, automated global connectivity of the power / ground RDL layer is achieved through parameterized configuration tools.

[0036] In summary, the present invention has the following beneficial effects:

[0037] By optimizing the physical layout of power / ground bumps, constructing interlocking structures, and achieving global connectivity through structured steps, this approach effectively solves the problems of lack of systematic guidance in layout, low space utilization, excessively high power path impedance, and unbalanced current distribution in existing technologies. It improves the systematic nature and space utilization of RDL layer layout, reduces power path impedance, reduces noise coupling, and improves current distribution uniformity, thereby enhancing power integrity and chip reliability. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating a power supply RDL layer design method for a digital integrated circuit according to the present invention.

[0039] Figure 2 This is a schematic diagram of the bump creation method of the power supply RDL layer design method of a digital integrated circuit according to the present invention.

[0040] Figure 3 This is a schematic diagram of the method for interleaved bump selection and attribute assignment in the power supply RDL layer design method of a digital integrated circuit according to the present invention.

[0041] Figure 4 This is a schematic diagram of a power supply bump-based RDL layer design method for a digital integrated circuit according to the present invention.

[0042] Figure 5 This is a schematic diagram of a ground bump-based design method for the power supply RDL layer of a digital integrated circuit according to the present invention.

[0043] Figure 6 This is a schematic diagram of the method for creating global power line and ground line RDL layers in the power supply RDL layer design method of a digital integrated circuit according to the present invention.

[0044] Figure 7 This is a schematic diagram illustrating the final implementation effect of the power supply RDL layer design method for a digital integrated circuit according to the present invention.

[0045] Explanation of the labels in the diagram:

[0046] 1-Preparation of Digital Back-End Layout and Routing Data

[0047] 2-Creating the bump method

[0048] 3- Select the bump and assign power and ground attributes.

[0049] 4- Design the RDL layer with the power bump as the center.

[0050] 5- Design RDL layers centered on the ground bump

[0051] 6- Create global power and ground RDL layers and implement connectivity.

[0052] 7-Creating a bump

[0053] 8. Select the appropriate R45 and R135 type bump units.

[0054] 9-Set specific parameters for bump placement

[0055] 10- Set specific layout type and mode

[0056] 11- Interleaved selection of bumps

[0057] 12- Select the odd-numbered item "bump" and assign it power properties.

[0058] 13 - Select the even-numbered item (bump) and assign it the "ground" attribute.

[0059] 14- Interconnection between power bump and power RDL layer

[0060] 15-Ground bump and ground RDL layer interconnection

[0061] 16- Design the corresponding RDL layer with the power supply bump as the center.

[0062] 17-Select the power bump unit in the R45 direction.

[0063] 18-Select the power bump unit in direction R135.

[0064] 19- Design symmetrical convex RDL layers with R45-direction power bump units and implement interconnection.

[0065] 20- Design symmetrical convex RDL layers with R135-direction power bump units and implement interconnection.

[0066] Implementation effect diagram of the 21-R45 direction power bump unit corresponding to the RDL layer

[0067] Implementation effect diagram of the 22-R135 direction power bump unit corresponding to the RDL layer

[0068] 23-Design the corresponding RDL layer with the ground bump as the center.

[0069] 24 - Select the bump unit in the R45 direction.

[0070] 25 - Select the bump unit in the R135 direction.

[0071] 26- Design symmetrical concave RDL layers with bump cells in the R45 direction and implement interconnection.

[0072] 27- Design symmetrical concave RDL layers with bump cells in the R135 direction and implement interconnection.

[0073] Implementation effect diagram of the 28-R45 direction bump unit corresponding to the RDL layer

[0074] Implementation effect diagram of the bump unit in the 29-R135 direction corresponding to the RDL layer

[0075] 30 - Create power and ground wires

[0076] 31- Select the RDL layer according to the process document rules and set it to vertical direction.

[0077] 32-Setting up power and ground modes

[0078] 33-Setting and adding specific configuration parameters for power and ground wires

[0079] Final design and implementation effect diagram of 34-RDL layer interconnection Detailed Implementation

[0080] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to the figures and specific embodiments.

[0081] like Figure 1 As shown, the present invention proposes an RDL layer design method for integrated circuit back-end layout, which includes the following steps:

[0082] S1. Digital back-end layout and wiring data preparation:

[0083] By establishing a design foundation environment, an accurate physical basis is provided for power networks;

[0084] S2. Create a bump:

[0085] By optimizing the physical layout of power / ground bumps, a structured carrier is provided for power / ground network distribution;

[0086] S3. Assign power and ground attributes:

[0087] By establishing a logical partition of the power network, a foundation is laid for the interlocking structure of the subsequent convex / concave RDL;

[0088] S4. Plan the corresponding RDL layer with the power supply bump as the center:

[0089] By constructing a power transmission backbone network, a low-impedance power path is formed.

[0090] S5. Plan the corresponding RDL layer centered on the land bump:

[0091] By constructing a grounded return network, the power / ground loop area is reduced, and noise coupling is suppressed;

[0092] S6. Create and connect the power / ground RDL layer:

[0093] By globally connecting the power or ground wires, current bottlenecks are eliminated, achieving global low-impedance interconnection.

[0094] In practical applications, digital back-end placement and routing data preparation can be understood as the process of providing necessary input information for subsequent design. This can be achieved by importing external design files, manually configuring design parameters, or automatically generating initial placement data, primarily to ensure the accuracy and consistency of the design environment. The specific implementation of bump creation can include generating a regularly arranged bump array based on chip size and process requirements, or using an irregular distribution to adapt to specific power requirements. Its purpose is to provide physical connection points for power and ground networks. The process of assigning power and ground attributes can be automated through algorithms, such as classifying and marking bumps based on preset rules, or implemented through manual specification. Its main function is to provide a logical basis for subsequent RDL layer design. Planning the corresponding RDL layer centered on the power bump can be achieved by defining a multi-level power network topology, such as using a tree structure or a mesh structure, to reduce the impedance of the power path. Planning the corresponding RDL layer centered on the ground bump can be achieved by designing symmetrical return paths, such as using a ring structure or a cross-connection structure, to reduce the loop area between power and ground. The process of creating and connecting power / ground RDL layers can be achieved by setting uniform routing rules, such as defining globally consistent line width and spacing parameters, or by optimizing routing strategies by region. Its main function is to eliminate local current bottlenecks.

[0095] The innovation of this application lies in optimizing the RDL layer design through a systematic process, from basic environment construction to global interconnect implementation, collaboratively solving the power integrity problem. Specifically, S1 to S3 complete data preparation and logic partitioning, providing support for subsequent steps; S4 and S5 construct the backbone and return paths for the power and ground networks respectively, forming a complementary interlocking structure to reduce loop area; S6 integrates the results of the preceding steps through global connectivity, eliminating local bottlenecks, thereby improving space utilization and solving the electromigration problem. Furthermore, this method reduces power path impedance and voltage drop by optimizing the layout and interconnection of the power and ground networks, and alleviates the electromigration problem through uniform spatial layout, thus meeting the design requirements of high-density, high-performance integrated circuits.

[0096] The working principle of this application is as follows:

[0097] First, by preparing digital back-end layout and routing data, a basic design environment is established, providing an accurate physical basis for the power network. This step ensures that subsequent steps can be carried out in a reliable design environment, avoiding layout deviations caused by inaccurate environments, thus laying a solid foundation for the implementation of the overall solution.

[0098] Furthermore, bumps are created and their physical layout is optimized to provide a structured carrier for power and ground network allocation. This step improves the efficiency of spatial layout by rationally planning the location and distribution of bumps, while providing physical support for the subsequent logical partitioning of power and ground networks, and helping to reduce power path impedance.

[0099] When allocating power and ground attributes, a logical partitioning of the power network provides the foundation for the interlocking structure of subsequent convex and concave RDL layers. This logical partitioning reduces interference between networks, enhances the efficiency of power allocation, and creates conditions for constructing low-impedance paths and return networks in subsequent steps.

[0100] Therefore, an RDL layer is planned around the power bump, forming a low-impedance power path by constructing a power transmission backbone network. This design directly reduces the impedance of the power path, alleviates the voltage drop problem, and ensures the stability of the chip's power supply. Simultaneously, an RDL layer is planned around the ground bump, reducing the loop area between power and ground by constructing a ground return network, suppressing noise coupling, and thus improving signal integrity.

[0101] Finally, by creating power and ground RDL layers and achieving global connectivity, the current bottleneck was eliminated, resulting in globally low-impedance interconnects. This step integrates the results of the preceding steps, solves the electromigration problem, ensures the uniformity and low impedance characteristics of the overall layout, thereby improving space utilization and ensuring stable chip operation.

[0102] In summary, the various technical features work closely together, from front-end data preparation to global interconnection, to collaboratively solve power integrity and signal integrity issues, thereby improving the utilization and uniformity of RDL layer layout and reducing power path impedance.

[0103] This application further proposes the following specific method for step S1 in the above-mentioned RDL layer design method for integrated circuit back-end layout:

[0104] Importing netlists, constraints, and process design documents; planning chip size; standard cell placement stage; I / O cell placement stage; and IP cell placement stage.

[0105] Specifically, importing a netlist refers to introducing circuit connection logic information into the design environment. This can be implemented using Verilog or EDIF netlist formats, aiming to clarify the connection relationships between circuit components. Constraint files are configuration files that define design rule boundaries. They can be implemented using SDC or TCL script formats, aiming to specify design requirements such as timing and area. Process design files are technical documents containing manufacturing parameters. They can be implemented using LEF / DEF or GDSII formats, aiming to provide the process information required for physical implementation. Planning chip size refers to setting the spatial framework based on the physical boundary requirements of the target chip. This can be achieved through manual input or automated tools, aiming to provide precise spatial constraints for layout. Standard cell placement refers to the basic structural arrangement of the core logic area based on the cell's electrical characteristics. This can be implemented using a row-column layout or a hybrid layout, aiming to optimize power distribution uniformity. I / O cell placement refers to locating cell positions based on the characteristics of input / output interfaces. This can be implemented using a ring layout or a grouped layout, aiming to reduce signal path noise coupling. IP unit placement refers to the integrated layout based on the characteristics of pre-designed modules. It can be implemented using a partitioned layout or a hierarchical layout, with the aim of ensuring efficient connectivity between critical modules and the power network.

[0106] This solution systematically defines the implementation process of step S1. First, it imports netlists, constraints, and process design files as initial inputs. These three elements work together to ensure subsequent steps are based on complete and consistent design information. Then, chip size planning is performed to provide a precise spatial framework for layout, supporting the realization of maximum density rules in process manufacturing. In the standard cell placement stage, the basic structure of the core logic region is formed, directly affecting the uniformity of power distribution. The I / O cell placement stage optimizes boundary signal paths and enhances signal integrity. Finally, in the IP cell placement stage, efficient connectivity between critical modules and the power network is ensured, suppressing electromigration effects. Each operation step revolves around the systematic preparation of data. By clearly defining the operation sequence, the ambiguous environment setup is transformed into executable and verifiable specific steps, fundamentally improving the accuracy of the power network's physical foundation.

[0107] The above technical solutions effectively solve the problems of ambiguity and lack of systematicity in the data preparation process, ensure the accuracy of the physical foundation of the power network, thereby improving the space layout utilization, reducing power path impedance, reducing the risk of electromigration, and ensuring the stable operation of the chip.

[0108] This application further proposes the following specific method for step S2 in the above-mentioned RDL layer design method for integrated circuit back-end layout:

[0109] Determine the number and shape of bumps according to process requirements, set the starting coordinates and X / Y direction spacing, set the placement type to horizontal staggered and diamond arrangement, set the staggered offset value according to the Pythagorean theorem, and set the full_chip mode.

[0110] Specifically, process requirements refer to the constraints on bump size, density, and distribution during manufacturing. These can be defined based on the technical specifications of current advanced process nodes, aiming to ensure that the bump design strictly matches manufacturing capabilities and avoid short circuit or open circuit risks caused by size or density mismatches. Starting coordinates and X / Y direction spacing refer to the initial position of the bump in the chip plane and its horizontal and vertical spacing. These can be precisely set to achieve globally controllable distribution, thereby optimizing current density distribution and reducing local hotspots. Placement type refers to the arrangement of bumps in the chip plane, which can be implemented using horizontal staggered or diamond-shaped arrangements. The purpose is to fully utilize spatial geometry to increase placement density while constructing an interlocking structure for the power / ground network. The stagger offset value refers to the horizontal offset between adjacent rows in a diamond arrangement. This can be precisely calculated using mathematical principles such as the Pythagorean theorem, aiming to optimize the relative positional relationship between bumps to reduce power / ground loop area. Full chip mode refers to a global layout mode that covers the entire chip area. It can be implemented using a unified parameter configuration method to ensure the consistency of layout parameters and avoid overall imbalance caused by local optimization.

[0111] In detail, this method effectively improves the accuracy and uniformity of bump physical arrangement by systematically defining key parameters of bump layout. First, the number and shape of bumps are determined according to process requirements, providing a reliable physical basis for subsequent layout. Second, by setting the starting coordinates and X / Y direction spacing, a globally controllable distribution of bump positions is achieved, homogenizing current density and mitigating electromigration effects. Third, a combination of lateral staggered and diamond-shaped arrangements significantly increases bump density, approaching the maximum design density tolerated by the process, while enhancing layout stability. Furthermore, the Pythagorean theorem is used to accurately calculate the staggered offset values, optimizing the relative positional relationship between bumps and effectively suppressing noise coupling. Finally, by setting the full_chip mode, global consistency of layout parameters is ensured, achieving uniform power distribution and low-impedance interconnection. Based on this, this method, combined with the design foundation environment established in step S1, further optimizes the physical basis of the power network, thereby solving the problems of low space utilization and high power path impedance.

[0112] The above technical solutions not only improve the space utilization of the bump layout, but also significantly reduce the power path impedance, effectively alleviate voltage drop and electromigration problems, and provide a reliable guarantee for the stable operation of the chip.

[0113] This application further proposes to select odd-numbered items and assign them power attributes to connect to the power RDL layer, and select even-numbered items and assign them ground attributes to connect to the ground RDL layer.

[0114] Specifically, odd-numbered bumps refer to bumps with odd-numbered serial numbers in the overall bump layout. This is achieved by uniformly numbering all bumps and then selecting those that meet the odd-numbered condition. This allocation method aims to ensure that power-related bumps are evenly distributed across the entire chip area, thus avoiding the problem of excessively high local current density. Even-numbered bumps refer to bumps with even-numbered serial numbers in the overall bump layout. This is also achieved by uniformly numbering all bumps and then selecting those that meet the even-numbered condition. The purpose of this allocation method is to create a regular alternation pattern between ground-related bumps and power-related bumps, thereby optimizing the physical layout of the power and ground networks.

[0115] The above technical solution first divides bumps into odd-numbered and even-numbered categories based on sequence numbering rules, assigning them power and ground attributes respectively. This systematic allocation method ensures a uniform spacing distribution of power and ground bumps across the entire chip, effectively mitigating the risk of electromigration caused by current concentration. Simultaneously, this alternating allocation mechanism provides a uniform physical basis for the interlocking structures of subsequent convex and concave RDL layers, reducing the loop area between power and ground, thereby suppressing noise coupling. Furthermore, the uniform distribution of power and ground bumps further improves the utilization rate of the space layout and reduces power path impedance by balancing current paths, enhancing the chip's power integrity and reliability. This technical solution, together with the power network logic partitioning and subsequent RDL layer planning involved in the aforementioned steps, forms a close technical link, jointly solving the voltage drop and electromigration problems and meeting the design requirements of high-density, high-performance integrated circuits.

[0116] This application further proposes a specific implementation method for planning the corresponding RDL layer centered on the ground bump in the RDL layer design method for the back-end layout of the aforementioned integrated circuit. First, select the bump in the R45 direction and create a vertically symmetrical concave RDL layer with the center point, surrounding the selected bump and forming interconnections; then select the bump in the R135 direction and create a vertically symmetrical concave RDL layer with the center point, surrounding the selected bump and forming interconnections.

[0117] Specifically, the R45-direction bump refers to a convex point at a 45-degree angle to the horizontal axis in a diamond-shaped arrangement. Its selection is based on the fact that this direction best matches the physical layout characteristics of the power network, thereby reducing layout gaps caused by directional inconsistencies. In practical applications, the specific location of the R45-direction bump can be determined through coordinate definitions or geometric algorithms in the process documentation. Its purpose is to optimize space utilization and ensure precise alignment between the RDL layer and the power network. The R135-direction bump can be understood as a convex point at a 135-degree angle to the horizontal axis in a diamond-shaped arrangement. Its function is similar to the R45-direction bump, but it covers the power network requirements in another direction, thus achieving seamless interconnection of the global power network. The symmetrical concave RDL layer refers to an inwardly recessed structured metal layer. Its design purpose is to form an interlocking structure with the convex RDL layer, enhancing the continuity of the overall layout and reducing the risk of current concentration. In practical applications, such structures can be generated using parametric design tools. The key is to ensure the symmetry of the concave RDL layer and its precise matching with the bump.

[0118] The above technical solution effectively solves the problem of uneven RDL layout by clearly defining the selection of bump direction and the specific implementation method of RDL layer shape. First, a symmetrical concave RDL layer is created for the R45 direction bump, ensuring a high degree of matching between RDL planning and physical layout, avoiding layout gaps caused by directional inconsistencies, and thus significantly improving space utilization. Second, by surrounding and interconnecting the selected bump, the integrity of the grounding connection and the uniformity of current distribution are ensured, eliminating local current bottlenecks. The same approach is applied to the R135 direction bump, further covering all ground bump directions and achieving a continuous interconnection of the global grounding network. On this basis, the interlocking structure design of the concave and convex RDL layers not only reduces layout gaps but also enhances structural continuity, reduces the risk of current concentration, and thus effectively mitigates electromigration effects. In addition, by constructing a ground return network, the loop area between power supply and ground is reduced, noise coupling is suppressed, and ultimately, low impedance and high reliability of power transmission are ensured.

[0119] In summary, the above technical solutions, through systematic steps and structured design methods, significantly optimize the spatial layout and electrical performance of the RDL layer, meeting the requirements of high-density, high-performance integrated circuit design.

[0120] This application further proposes the following technical solutions:

[0121] Select the bump in the R45 direction and create a symmetrical concave RDL layer with the center point. Surround the selected bump and form interconnections. Select the bump in the R135 direction and create a symmetrical concave RDL layer with the center point. Surround the selected bump and form interconnections.

[0122] Specifically, the R45-direction bump refers to a protrusion at a 45-degree angle to the horizontal axis in a diamond-shaped layout. It can be achieved by adjusting the spacing and position based on process design rules, aiming to ensure a strict match between the RDL layer design and the physical layout, avoiding current path conflicts due to directional deviations. The R135-direction bump refers to a protrusion at a 135-degree angle to the horizontal axis in a diamond-shaped layout. It can also be optimized through process rules, aiming to cover all critical directions to ensure global consistency of the grounding network. The symmetrical concave RDL layer can be understood as a metal interconnect structure with a specific geometry, formed through precise photolithography and deposition processes. Its purpose is to form an interlocking mechanism with the convex design of the power RDL layer, thereby improving space utilization and balancing current distribution.

[0123] In detail, this technical solution systematically optimizes the layout uniformity and electrical performance of the ground return network by customizing a concave RDL layer structure for the ground bump direction. First, selecting the bump in the R45 direction is based on its diamond-shaped geometric characteristics, ensuring a strict match between the RDL layer design and the physical layout, avoiding local impedance increases caused by directional deviations. Second, the design of creating symmetrical concave RDL layers around the center point utilizes the complementarity between the concave structure and the convex design of the power RDL layer, significantly improving space utilization and balancing current distribution, thereby effectively mitigating electromigration risks. Furthermore, the step of surrounding and interconnecting the selected bump achieves a low-impedance continuous path by completely enclosing the bump, significantly shortening the ground return distance, reducing the power / ground loop area, and enhancing noise suppression capabilities. Finally, the same treatment applied to the bump in the R135 direction covers all critical directions, ensuring global consistency of the ground network across the entire chip area, eliminating directional defects, and further consolidating power integrity and signal stability.

[0124] Based on this, the above technical solution, together with the aforementioned steps, solves the problems of uneven impedance distribution in the ground return path, ineffective loop area compression, and insufficient noise coupling suppression. By combining bump design in the R45 and R135 directions, not only is the uniformity of the spatial layout improved, but the power path impedance is also significantly reduced, meeting the design requirements of high-density, high-performance integrated circuits.

[0125] This application further proposes the following specific method for step S6: setting the layer, length, width, spacing, direction, starting coordinates and starting direction sequence of power lines and ground lines, and realizing global connection of power or ground lines through parameterized configuration.

[0126] Specifically, layering refers to selecting appropriate metal layers for routing based on process characteristics. This can be achieved using multi-layer metal structures, aiming to optimize current carrying capacity distribution and avoid local impedance concentration caused by high resistivity layers. Length refers to controlling the line length according to chip size and layout requirements. This can be achieved by dynamically adjusting the routing path, aiming to minimize resistance accumulation effects and prevent voltage drops due to excessively long conductors from failing to meet process requirements. Width refers to increasing the line width based on current density requirements. This can be achieved using a gradient width design, aiming to reduce resistance per unit length, increase the upper limit of current carrying capacity, and mitigate the risk of metal line failure due to electromigration effects. Spacing refers to determining the distance between lines based on process manufacturing rules. This can be achieved using a non-uniform spacing design, aiming to prevent electromagnetic interference and short circuits while maintaining a high-density layout, balancing space utilization and reliability. Direction refers to optimizing the routing direction based on the power / ground network topology. This can be achieved using a mesh or radial routing method, aiming to reduce power / ground loop area and suppress the impact of noise coupling on signal integrity. The starting coordinates refer to the precise location of the routing start point based on the chip's geometric center. This can be achieved using a symmetrical layout to ensure layout symmetry and uniform current distribution, avoiding electromigration problems caused by localized current concentration. The starting direction sequence refers to the defined starting order based on the routing path planning. This can be achieved using an alternating routing strategy to make the current distribution more uniform, prevent localized overload caused by improper sequence, and reduce the risk of electromigration.

[0127] The above technical solution ensures precise global connectivity by systematically configuring key physical parameters of power / ground lines, effectively eliminating current bottlenecks, reducing power path impedance, and improving voltage drop and electromigration issues. Setting the layer allows for the selection of appropriate metal layers based on process characteristics, optimizing current carrying capacity distribution; setting the length allows for flexible adjustment of line length according to chip size and layout requirements, minimizing resistance accumulation effects; setting the width increases line width based on current density requirements, reducing resistance per unit length; setting the spacing determines the distance between lines in conjunction with manufacturing rules to prevent electromagnetic interference and short circuits; setting the direction optimizes routing based on power / ground network topology, reducing power / ground loop area; setting the starting coordinates precisely locates the routing start point based on the chip's geometric center, ensuring layout symmetry; setting the starting direction sequence defines the starting sequence in conjunction with routing path planning, making current distribution more uniform. Through parameterized configuration, global connectivity of power or ground lines is achieved. Based on the coordinated setting of the above parameters, seamless connection of power or ground lines is ensured throughout the entire chip, completely eliminating current bottlenecks and achieving global low-impedance interconnection, thereby improving power integrity and chip reliability.

[0128] Based on this, the above technical solution, together with steps S1 to S5, forms a complete RDL layer design flow. By establishing a basic design environment to provide an accurate physical foundation for the power network, optimizing the physical layout of power / ground bumps, establishing the logical partitioning of the power network, constructing the power transmission backbone network and the ground return network, and ultimately achieving global low-impedance interconnection, the space layout utilization and power distribution efficiency are significantly improved, the voltage drop and electromigration problems are solved, and the stable operation of the chip is guaranteed.

[0129] Example

[0130] Reference Figures 1-7 This invention provides an RDL layer design method for integrated circuit back-end layout. Step 1 is to prepare digital back-end layout routing data. Step 2 is to create bumps based on step 1. Step 3 is to select different bumps and assign them power or ground attributes based on step 2. Step 4 is to design an RDL layer centered on the power bump. Step 5 is to design an RDL layer centered on the ground bump. Step 6 is to create power and ground RDL layers according to process rules based on steps 4 and 5, and finally achieve through interconnection.

[0131] Step 1, digital back-end layout and routing data preparation, includes importing netlists, constraints, and process design documents, planning chip size, standard cell placement stage, IO cell placement stage, and IP cell placement stage.

[0132] Step 2 involves creating a bump method 7, selecting the corresponding R45 and R135 type cells 8 according to the rules. In this embodiment, N55_N40_N28_80P_Oval_Cu_bump_R45 and N55_N40_N28_80P_Oval_Cu_bump_R135 are used, which are elliptical in shape. The commands are create_bump -cell N55_N40_N28_80P_Oval_Cu_bump_R45 and create_bump-cell N55_N40_N28_80P_Oval_Cu_bump_R135. The specific parameters for bump placement 9 are set, including the starting position, direction, and spacing. The commands are -loc {570 620} -loc_type cell_lowerleft -orientation R0 -pitch{400 129.03} -start_from `lower_left` sets the stagger type to horizontal arrangement, the stacking method, the stagger offset value, and sets the full_chip mode to 10. The command is `-pattern_full_chip -stagger_type odd_rows -stagger_offset 200 -allow_overlap_control keep_existing_bumps`.

[0133] Step 3, selecting bumps and assigning power and ground attributes, includes interleaving the selection of bumps 11, selecting odd-numbered bumps such as bump1, bump3, and bump5 and assigning power attribute 12, with the command `select_bump -bumps {bump1bump3 bump5},assignPGBumps -nets VDD -selected`; and selecting even-numbered bumps such as bump2, bump4, and bump6 and assigning ground attribute 13, with the command `select_bump -bumps {bump2 bump4 bump6},assignPGBumps -nets VSS -selected`.

[0134] Step 4 involves designing a corresponding RDL layer 16 centered on the power supply bump. First, select the bump cell 17 in the R45 direction using the command `select_bump -bump_cell {N55_N40_N28_80P_Oval_Cu_bump_R45} -nets VDD`. Create a symmetrical convex RDL layer with its center point, surrounding and interconnecting the bump 19, achieving the desired effect (illustration 21). Taking the left vertical RDL layer as an example, the commands are: `set left_width 30 set right_width 30 set top_width30 set bottom_width 30 set center_width 30 set bump_size 72.448 set space 2,set center_x [dbGet [dbGet selected].bump_shape_center_x],set center_y [dbGet[dbGet selected].bump_shape_center_y] add_shape -layer AP -width $left_width-status FIXED -shape STRIPE -pathSeg [expr $center_x -` (($bump_size+$left_width) / 2+space)] [expr $center_y-($bump_size / 2+$space+$bottom_width)] [expr $center_x - (($bump_size+$left_width) / 2+$space)] [expr $center_y+($bump_size / 2+$space+$top_width)] -net VDD. For the remaining RDL layers, modify the parameters of the above commands according to the actual location. Then select the bump cell 18 in the R135 direction, and use the command select_bump -bump_cell {N55_N40_N28_80P_Oval_Cu_bump_R135} -nets VDD. Create a symmetrical convex RDL layer around its center point, surrounding and interconnecting it 20, achieving the effect shown in Figure 22. The command is the same as for the power bump cell in the R45 direction.

[0135] Step 5 designs the corresponding RDL layer 23 centered on the bump. First, select the bump cell 24 in the R45 direction using the command `select_bump -bump_cell {N55_N40_N28_80P_Oval_Cu_bump_R45} -nets VSS`. Create a symmetrical concave RDL layer with its center point, surrounding and interconnecting the bump 26, achieving the desired effect (illustration 28). Taking the left vertical RDL layer as an example, the command is: `set left_width 30 set right_width 30 set top_width 30 set bottom_width 30 set center_width 30 set bump_size 72.448 set space 2 setcenter_x [dbGet [dbGet selected].bump_shape_center_x],set center_y [dbGet[dbGet selected].bump_shape_center_y],add_shape -layer AP -width $left_width-status FIXED -shape STRIPE -pathSeg [expr`. $center_x-(($bump_size+$left_width) / 2+$space)] [expr $center_y-($bump_size / 2+$space+$bottom_width)-118.85][expr $center_x-(($bump_size+$left_width) / 2+$space)] [expr $center_y+($bump_size / 2+$space+$top_width)+118.85] -net VSS. For the remaining RDL layers, modify the parameters of the above command according to the actual location. Then select element 25 in the R135 direction, and use the command select_bump -bump_cell {N55_N40_N28_80P_Oval_Cu_bump_R135} -nets VSS to create a symmetrical concave RDL layer around its center point, surrounding and interconnecting it 27, achieving the effect shown in diagram 29. The command is the same as the bump element in the R45 direction above.

[0136] Step 6, creating power and ground wires and achieving continuity according to process rules, includes: 30. Creating power and ground wires; 31. The RDL layer is defined vertically in the current process file, so it is specified as vertical; 32. Setting the mode for adding power and ground wires; 33. Setting the power and ground wires as a group and specific control parameters to form continuity; 44. Selecting power and ground wires as a group; 35. Selecting the power and ground wires as a group; 6. Selecting the width as 22µm; 7.55µm spacing; 40.0µm group spacing; 400µm group spacing; 400µm group spacing; 6.0µm starting coordinates and starting direction; 7.0µm starting coordinates and starting direction; 8.0µm starting coordinates and starting direction.

[0137] After completing steps 1 through 6 in sequence, the final result is illustrated in the diagram below. Figure 7 As shown, the power lines (VDD) and ground lines (VSS) together form a mortise and tenon structure similar to that in wooden components. At the same time, the power lines (VDD) and ground lines (VSS) are globally interconnected to form a robust RDL layer power supply network, which effectively addresses the voltage drop (IR) and electromigration (EM) problems that often exist in the back-end design of digital integrated circuits, and provides stable voltage and current to the chip.

[0138] In this document, the terms "upper," "lower," "front," "back," "left," "right," "top," "bottom," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used for the clarity of expressing the technical solution and for the convenience of description, and therefore should not be construed as limiting the present invention.

[0139] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0140] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for designing an RDL layer for back-end layout of an integrated circuit, characterized in that, Includes the following steps: S1. Digital back-end layout and wiring data preparation: By establishing a design foundation environment, an accurate physical basis is provided for power networks; S2. Create a bump: By optimizing the physical layout of power / ground bumps, a structured carrier is provided for power / ground network distribution; S3. Assign power and ground attributes: By establishing a logical partition of the power network, a foundation is laid for the interlocking structure of the subsequent convex / concave RDL; First, select the bump in the R45 direction and create a top-to-bottom symmetrical convex RDL layer based on the center point of the single bump. Surround the selected bump and form an interconnection relationship. Then, select the bump in the R135 direction and create a top-to-bottom symmetrical convex RDL layer based on the center point of the single bump. Surround the selected bump and form an interconnection relationship. Select the bump in the R45 direction, and create a symmetrical concave RDL layer with the center point of the single bump as the reference. Surround the selected bump and form an interconnection relationship. Select the bump in the R135 direction, and create a symmetrical concave RDL layer with the center point of the single bump as the reference. Surround the selected bump and form an interconnection relationship. The convex RDL layer and the concave RDL layer complement each other in the two orthogonal diagonal directions R45 and R135 of the rhomboid arrangement, so that the power RDL layer and the ground RDL layer form a physical interlock. S4. Plan the corresponding RDL layer with the power supply bump as the center: By constructing a power transmission backbone network, a low-impedance power path is formed. S5. Plan the corresponding RDL layer centered on the land bump: By constructing a grounded return network, the power / ground loop area is reduced, and noise coupling is suppressed; The upper and lower symmetrical concave RDL layers are inwardly recessed metal interconnect structures that form a closed surrounding structure around the ground bump and interconnect with other RDL layers of the same properties to form a low-impedance ground return channel. The upper and lower symmetrical concave RDL layers and the convex structure of the power RDL layer form a physical interlock, reducing layout gaps and enhancing structural continuity. S6. Create and connect the power / ground RDL layer: By globally connecting the power or ground wires, current bottlenecks are eliminated, achieving global low-impedance interconnection.

2. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, The specific method for step S1 is as follows: Importing netlists, constraints, and process design documents; planning chip size; standard cell placement stage; I / O cell placement stage; and IP cell placement stage.

3. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, The specific method for step S2 is as follows: Determine the number and shape of bumps according to process requirements, set the starting coordinates and X / Y direction spacing, set the placement type to horizontal staggered and diamond arrangement, set the staggered offset value according to the Pythagorean theorem, and set the full_chip mode.

4. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, The specific method for step S3 is as follows: Select the odd-numbered item bump and assign it the power attribute to connect to the power RDL layer; select the even-numbered item bump and assign it the ground attribute to connect to the ground RDL layer.

5. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, In step S5, the R45 direction bump refers to the ground bump at a 45° angle to the horizontal axis in the diamond arrangement, and the R135 direction bump refers to the ground bump at a 135° angle to the horizontal axis. By creating symmetrical concave RDL layers for the ground bumps in both orthogonal directions, the continuity and consistency of the omnidirectional grounding return path are achieved.

6. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, In step S5, the upper and lower symmetrical concave RDL layers are inwardly recessed metal interconnect structures that form a closed surrounding structure around the ground bump and interconnect with other RDL layers of the same properties to form a low-impedance ground return channel. The symmetrical concave RDL layer and the convex structure of the power supply RDL layer form a physical interlock, reducing layout gaps and enhancing structural continuity.

7. The RDL layer design method for integrated circuit back-end layout according to claim 1, characterized in that, The specific method for step S6 is as follows: Configure the layers, lengths, widths, spacing, directions, starting coordinates, and starting direction sequences of power and ground lines to achieve global connectivity of power or ground lines through parameterized configuration.

8. The RDL layer design method for integrated circuit back-end layout according to claim 7, characterized in that, The starting coordinates are symmetrically laid out with the chip's geometric center as the origin to ensure uniform current diffusion; the directions adopt a grid-like or radial routing strategy to reduce loop area; the starting direction sequence adopts an alternating routing strategy to avoid local overload and current concentration caused by dense routing of adjacent lines in the same direction; and finally, automated global connectivity of the power / ground RDL layer is achieved through parameterized configuration tools.

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