一种高速CML时钟BUF电路
By using a self-feedback biased AC coupling circuit, the problems of performance degradation and insufficient noise suppression of high-speed CML clock circuits under low power supply voltage are solved, and clock signal transmission with high signal-to-noise ratio and high gain under low power supply voltage is realized.
CN121585158BActive Publication Date: 2026-07-17BRITE SEMICON SHANGHAI CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BRITE SEMICON SHANGHAI CORP
- Filing Date
- 2026-01-28
- Publication Date
- 2026-07-17
Smart Images
Figure CN121585158B_ABST
Abstract
本发明公开了一种高速CML时钟BUF电路，属于集成电路设计技术领域，包括差分输入对管、尾电流源、负载电阻网络以及反馈电阻网络。其中，反馈电阻网络连接于输出端与输入管栅极之间，形成自偏置结构，无需外接偏置电压，简化了电路结构，减少了芯片面积。同时，通过采用自反馈偏置及可选的分压负载电阻结构，本发明既能有效抑制电源噪声和低频器件噪声，又适用于低电源电压应用，提升了时钟通路的整体性能和可靠性。
Need to check novelty before this filing date? Find Prior Art