Memory system, memory controller, operating method, and storage medium

Abstract

The embodiment of the present disclosure provides a memory system, a memory controller, a memory and an operating method thereof, and relates to the technical field of semiconductors. The method comprises: performing a first programming operation on a first storage unit to execute first data, the first data being to be stored into the memory based on the first programming operation and a second programming operation; when power failure occurs, generating layer indication data based on the first data, and performing a third programming operation on a second storage unit to store the layer indication data. Thus, faster data storage is achieved, resources consumed by the storage operation are saved, storage time is shortened, and data backup during power failure is better achieved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory system, a memory controller, a memory, and a method of operating the same. Background Technology

[0002] Storage devices, such as NAND flash memory, can store multiple bits of information in multiple levels per cell to increase storage capacity and reduce the cost per bit. Flash memory is a low-cost, high-density, non-volatile memory. Flash memory can perform various operations, such as read operations, programming (write) operations, and erase operations. Summary of the Invention

[0003] This disclosure provides a memory system, a memory controller, a memory, an operating method, a computer-readable storage medium, and a computer program product.

[0004] According to one aspect of the present disclosure, a memory system is provided, comprising: a memory including a memory cell array and peripheral circuitry coupled to the memory cell array; and a memory controller coupled to the memory, wherein the memory controller is configured to: send a first programming operation command to the memory, wherein the first programming operation command includes first data and a first address, the first data being data to be stored in the memory based on a first programming operation and a second programming operation, the first address corresponding to a first memory cell; and, in response to a power outage, if the first programming operation has been completed, send a third programming operation command to the memory, wherein the third programming operation command includes the first data and a second address, the second address corresponding to a second memory cell; the peripheral circuitry is configured to: receive the first programming operation command from the memory controller, perform the first programming operation on the first memory cell of the memory to store the first data; receive the third programming operation command from the memory controller, generate level indicator data based on the first data; and perform a third programming operation on the second memory cell of the memory to store the level indicator data.

[0005] In one embodiment, the peripheral circuitry is configured to generate layer indication data based on the parity information of the first data.

[0006] In one embodiment, the peripheral circuit is configured to perform an XOR operation on the parity information of each page of the first data to generate the layer indicator data.

[0007] In one embodiment, the peripheral circuitry is configured to perform a single-level cell programming operation on the second storage cell of the memory to store the layer instruction data.

[0008] In one embodiment, the memory controller is further configured to: send a second programming operation command to the memory, the second programming operation command including the first data and the first address; and, in response to a power failure, send a fourth programming operation command to the memory if the second programming operation has not been completed, wherein the fourth programming operation command includes the first data and a third address, the third address corresponding to a third memory cell; the peripheral circuit is configured to: receive the second programming operation command from the memory controller, perform the second programming operation on the first memory cell of the memory to store the first data; and receive the fourth programming operation command from the memory controller, perform a single-level cell programming operation on the third memory cell of the memory to store the page data corresponding to the first data.

[0009] In one embodiment, the storage controller is configured to send a set feature command to the storage in response to a power failure. The set feature command includes a first parameter indicating that the coarse data backup function of the storage is enabled. The peripheral circuitry is configured to receive the set feature command from the storage controller and enable the coarse data backup function of the storage.

[0010] In one embodiment, the first storage unit is a three-level cell (TLC) or a four-level cell (QLC).

[0011] In one embodiment, the storage controller is configured to: upon power-on, send a setting characteristic command to the storage, the setting characteristic command including a second parameter indicating that coarse data recovery of the storage is enabled; send a first read operation command to the storage to obtain third and fourth data, the first read operation command including the first address; send a second read operation command to the storage to obtain layer indication data, the second read operation command including the second address; obtain the first data based on the layer indication data, the third data, and the fourth data; the peripheral circuit is configured to: receive the first read operation command from the storage controller, perform a third read operation on the first storage cell based on a first layer read voltage to obtain the third data, perform a fourth read operation on the first storage cell based on a second layer read voltage to obtain the fourth data; receive the second read operation command from the storage controller, and perform a second read operation on the second storage cell to obtain the layer indication data.

[0012] In one embodiment, the memory controller is configured to send a fifth programming operation command to the memory, the fifth programming operation command including the first data and the first address; the peripheral circuit is configured to receive the fifth programming operation command from the memory controller and perform the second programming operation on the first memory cell to store the first data.

[0013] In one embodiment, the memory controller is configured to send a sixth programming operation command to the memory, the sixth programming operation command including the first data and a fourth address, the fourth address corresponding to a fourth memory cell; the peripheral circuit is configured to receive the sixth programming operation command from the memory controller and perform a programming operation on the fourth memory cell to store the first data.

[0014] In one embodiment, the first layer read voltage is a read voltage determined based on the voltage distribution of the odd-numbered states; the second layer read voltage is a read voltage determined based on the voltage distribution of the even-numbered states.

[0015] In one embodiment, the storage controller is configured to: use the third data as the first data when the layer indication data indicates an odd state; and use the fourth data as the first data when the layer indication data indicates an even state.

[0016] In one embodiment, the storage controller is configured to: after sending a first programming operation command to the storage, send a status read command to the storage to obtain the execution result of the first programming operation; and determine whether the first programming operation has been completed based on the execution result of the first programming operation.

[0017] In one embodiment, a backup power supply is also included to provide power to the memory system in the event of a power outage.

[0018] In one embodiment, the backup power source is a capacitor.

[0019] According to another aspect of this disclosure, a storage controller is provided, comprising: a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform processing, the processing comprising: sending a first programming operation command to the memory, the first programming operation command including first data and a first address, wherein the first data is data to be stored in the memory based on a first programming operation and a second programming operation, and the first address corresponds to a first storage cell; and, in response to a power failure, if the first programming operation has been completed, sending a third programming operation command to the memory, the third programming operation command including the first data and a second address, wherein the second address corresponds to a second storage cell, such that the memory generates layer indication data based on the first data and performs a third programming operation on the second storage cell to store the layer indication data.

[0020] In one embodiment, the process includes generating layer indication data based on the parity information of the first data.

[0021] In one embodiment, the third programming operation is a single-level cell programming operation.

[0022] In one embodiment, the process includes: sending a second programming operation command to the memory, the second programming operation command including the first data and the first address; and in response to a power failure, if the second programming operation has not been completed, sending a fourth programming operation command to the memory, the fourth programming operation command including the first data and a third address, wherein the third address corresponds to a third storage cell, so that the memory performs a single-level cell programming operation on the third storage cell to store the page data corresponding to the first data.

[0023] In one embodiment, the process includes: in response to a power failure, sending a setting characteristic command to the memory, the setting characteristic command including a first parameter indicating that the coarse data backup function of the memory is enabled.

[0024] In one embodiment, the first storage unit includes a three-level cell (TLC) or a four-level cell (QLC).

[0025] In one embodiment, the process includes: upon power-up, sending a setting characteristic command to the memory, the setting characteristic command including a second parameter indicating that the coarse data recovery function of the memory is enabled; sending a first read operation command to the memory to obtain third data and fourth data, the first read operation command including the first address; sending a second read operation command to the memory to obtain layer indication data, the second read operation command including the second address; and obtaining the first data based on the layer indication data, the third data, and the fourth data.

[0026] In one embodiment, the process includes sending a fifth programming operation command to the memory, the fifth programming operation command including the first data and the first address, so that the memory performs the second programming operation on the first storage cell to store the first data.

[0027] In one embodiment, the process includes sending a sixth programming operation command to the memory, the sixth programming operation command including the first data and a fourth address corresponding to a fourth storage cell, so that the memory performs a programming operation on the fourth storage cell to store the first data.

[0028] In one embodiment, the process includes: sending a first programming operation command to the memory, then sending a status read command to the memory to obtain the execution status of the first programming operation; and determining whether the first programming operation has been completed based on the execution status of the first programming operation.

[0029] In one embodiment, obtaining the first data based on the layer indication data, the third data, and the fourth data includes: when the layer indication data indicates an odd state, using the third data as the first data; and when the layer indication data indicates an even state, using the fourth data as the first data.

[0030] In one embodiment, a backup power supply is also included to provide power to the memory system in the event of a power outage.

[0031] In one embodiment, the backup power source is a capacitor.

[0032] According to another aspect of this disclosure, a memory is provided, comprising: a memory cell array, and peripheral circuitry coupled to the memory cell array; the peripheral circuitry is configured to: receive a first programming operation command from a memory controller, the first programming operation command including first data and a first address, wherein the first data is data to be stored in the memory based on a first programming operation and a second programming operation, and the first address corresponds to a first memory cell; perform the first programming operation on the first memory cell to store the first data; in response to a power failure, if the first programming operation has been completed, receive a third programming operation command from the memory controller, the third programming operation command including the first data and a second address, wherein the second address corresponds to a second memory cell; generate layer indication data based on the first data; and perform a third programming operation on the second memory cell to store the layer indication data.

[0033] In one embodiment, the peripheral circuitry is configured to generate layer indication data based on the parity information of the first data.

[0034] In one embodiment, the peripheral circuitry is configured to perform an XOR operation on the parity information of each page of the first data to generate the layer indicator data.

[0035] In one embodiment, the peripheral circuitry is configured to perform a single-level cell programming operation on the second storage cell of the memory to store the layer instruction data.

[0036] In one embodiment, the peripheral circuitry is configured to: receive a second programming operation command from the memory controller, the second programming operation command including the first data and the first address; perform the second programming operation on the first memory cell to store the first data; in response to a power failure, if the second programming operation has not been completed, receive a fourth programming operation command from the memory controller, the fourth programming operation command including the first data and a third address, wherein the third address corresponds to a third memory cell; and perform a single-level cell programming operation on the third memory cell to store the page data corresponding to the first data.

[0037] In one embodiment, the peripheral circuitry is configured to receive a setting characteristic command from the memory controller in response to a power failure. The setting characteristic command includes a first parameter indicating that the coarse data backup function of the memory is enabled.

[0038] In one embodiment, the first storage unit is a three-level cell (TLC) or a four-level cell (QLC).

[0039] In one embodiment, the peripheral circuitry is configured to: upon power-up, receive a setting characteristic command from the memory controller, the setting characteristic command including a second parameter indicating that the coarse data recovery function of the memory is enabled; receive a first read operation command from the memory controller, the first read operation command including the first address; perform a third read operation on the first memory cell based on a first layer read voltage to obtain third data, and perform a fourth read operation on the first memory cell based on a second layer read voltage to obtain fourth data; receive the second read operation command from the memory controller, the second read command including the second address; perform a second read operation on the second memory cell to obtain layer indication data, so as to obtain the first data based on the layer indication data, the third data, and the fourth data.

[0040] In one embodiment, the peripheral circuitry is configured to: receive a fifth programming operation command from the memory controller, the fifth programming operation command including the first data and the first address; and perform the second programming operation on the first memory cell to store the first data.

[0041] In one embodiment, the peripheral circuitry is configured to: receive a sixth programming operation command from the memory controller, wherein the sixth programming operation command includes the first data and a fourth address, the fourth address corresponding to a fourth memory cell; and perform a programming operation on the fourth memory cell to store the first data.

[0042] In one embodiment, the first layer read voltage is a read voltage determined based on the voltage distribution of the odd-numbered states; the second layer read voltage is a read voltage determined based on the voltage distribution of the even-numbered states.

[0043] In one embodiment, obtaining the first data based on the layer indication data, the third data, and the fourth data includes: when the layer indication data indicates an odd state, using the third data as the first data; and when the layer indication data indicates an even state, using the fourth data as the first data.

[0044] In one embodiment, the peripheral circuit is configured to: after executing the first programming operation, receive a status read command from the storage controller, so that the storage controller obtains the execution status of the first programming operation, and determines whether the first programming operation has been completed based on the execution status of the first programming operation.

[0045] According to another aspect of this disclosure, a method for operating a memory is provided, comprising: receiving a first programming operation command from a memory controller, the first programming operation command including first data and a first address, wherein the first data is data to be stored in the memory based on a first programming operation and a second programming operation, and the first address corresponds to a first memory cell; performing the first programming operation on the first memory cell to store the first data; in response to a power failure, if the first programming operation has been completed, receiving a third programming operation command from the memory controller, the third programming operation command including the first data and a second address, wherein the second address corresponds to a second memory cell; generating layer indication data based on the first data; and performing a third programming operation on the second memory cell to store the layer indication data.

[0046] In one embodiment, generating layer indication data based on the first data includes: generating the layer indication data based on the parity information of the first data.

[0047] In one embodiment, generating the layer indicator data based on the parity information of the first data includes: performing an XOR operation on the parity information of each page of the first data to generate the layer indicator data.

[0048] In one embodiment, performing a third programming operation on the second storage cell of the memory to store the layer indication data includes: performing a single-layer cell programming operation on the second storage cell of the memory to store the layer indication data.

[0049] In one embodiment, the method further includes: receiving a second programming operation command from the memory controller, the second programming operation command including the first data and the first address; performing the second programming operation on the first memory cell to store the first data; in response to a power failure, if the second programming operation has not been completed, receiving a fourth programming operation command from the memory controller, the fourth programming operation command including the first data and a third address, wherein the third address corresponds to a third memory cell; and performing a single-level cell programming operation on the third memory cell to store the pages of data corresponding to the first data.

[0050] In one embodiment, the method further includes: in response to a power failure, receiving a setting characteristic command from the storage controller, the setting characteristic command including a first parameter indicating that the coarse data backup function of the storage is enabled, and enabling the coarse data backup function of the storage.

[0051] In one embodiment, the first storage unit is a three-level cell (TLC) or a four-level cell (QLC).

[0052] In one embodiment, the method further includes: upon power-on, receiving a setting characteristic command from the storage controller, the setting characteristic command including a second parameter indicating that the coarse data recovery function of the storage is enabled; receiving a first read operation command from the storage controller, the first read operation command including the first address; performing a third read operation on the first storage cell based on a first layer read voltage to obtain third data, and performing a fourth read operation on the first storage cell based on a second layer read voltage to obtain fourth data; receiving a second read operation command from the storage controller, the second read command including the second address; performing a second read operation on the second storage cell to obtain layer indication data, so as to obtain the first data based on the layer indication data, the third data, and the fourth data.

[0053] In one embodiment, the method further includes: receiving a fifth programming operation command from the storage controller, the fifth programming operation command including the first data and the first address; and performing the second programming operation on the first storage unit to store the first data.

[0054] In one embodiment, the method further includes: receiving a sixth programming operation command from the storage controller, wherein the sixth programming operation command includes the first data and a fourth address, the fourth address corresponding to a fourth storage unit; and performing a programming operation on the fourth storage unit to store the first data.

[0055] In one embodiment, the first layer read voltage is a read voltage determined based on the voltage distribution of the odd-numbered states; the second layer read voltage is a read voltage determined based on the voltage distribution of the even-numbered states.

[0056] In one embodiment, obtaining the first data based on the layer indication data, the third data, and the fourth data includes: when the layer indication data indicates an odd state, using the third data as the first data; and when the layer indication data indicates an even state, using the fourth data as the first data.

[0057] In one embodiment, the method further includes: after performing the first programming operation, receiving a status read command from the storage controller, so that the storage controller obtains the execution status of the first programming operation, and determines whether the first programming operation has been completed based on the execution status of the first programming operation.

[0058] According to another aspect of this disclosure, a computer-readable storage medium is provided that, when control instructions in the computer-readable storage medium are executed by a controller processor, enables the controller processor to perform the above-described operation method.

[0059] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program / instructions, characterized in that the computer program / instructions, when executed by a processor, implement the method described above.

[0060] By utilizing the technical solution disclosed herein, if a power failure occurs during multiple programming operations on the first data, the second programming operation will not be performed on the storage unit that has already completed the first programming operation. Instead, the layer indication information of the first data will be obtained, and the layer indication information of the first data will be stored in the second storage unit through a third programming operation. This enables faster data storage, saves resources consumed by storage operations, shortens storage time, and better achieves data backup during power failures.

[0061] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0062] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0063] Figure 1 A block diagram of an exemplary system having a memory is shown in one embodiment of this disclosure;

[0064] Figure 2A An exemplary block diagram of a memory system is shown;

[0065] Figure 2B An example block diagram of another memory system is shown;

[0066] Figure 2C An exemplary block diagram of yet another memory system is shown;

[0067] Figure 3 A schematic circuit diagram of a memory including peripheral circuitry provided in one embodiment of this disclosure is shown.

[0068] Figure 4 A schematic diagram of a peripheral circuit provided in one embodiment of this disclosure is shown;

[0069] Figure 5 A block diagram of a page buffer / sensor amplifier is shown;

[0070] Figure 6 A flowchart illustrating a memory system operation method according to one embodiment of this disclosure is shown;

[0071] Figure 7A A flowchart illustrating a storage controller operation method in one embodiment of this disclosure is shown;

[0072] Figure 7B A flowchart illustrating a memory operation method in one embodiment of this disclosure is shown;

[0073] Figure 8 A flowchart illustrating a storage controller operation method in another embodiment of this disclosure is shown;

[0074] Figure 9 A flowchart illustrating a memory operation method in another embodiment of this disclosure is shown;

[0075] Figure 10A A schematic diagram showing the programming state of a storage unit in one embodiment of this disclosure;

[0076] Figure 10B according to Figure 10A An exemplary diagram illustrating the programming state signaling of an embodiment of this disclosure is shown;

[0077] Figure 10C according to Figure 10A An exemplary diagram illustrating the programming state signaling of an embodiment of this disclosure is shown;

[0078] Figure 11 This illustrates a command sequence for a memory operation method according to an embodiment of the present disclosure;

[0079] Figure 12 A flowchart illustrating a storage controller operation method in yet another embodiment of this disclosure is shown;

[0080] Figure 13 A flowchart of a memory operation method is shown in yet another embodiment of this disclosure;

[0081] Figure 14 This illustrates a command sequence for a memory operation method according to an embodiment of the present disclosure;

[0082] Figure 15A This diagram illustrates the threshold voltage distribution after the first programming in one embodiment of the present disclosure.

[0083] Figure 15B This illustrates layer indicator data corresponding to different programming states in one embodiment of this disclosure;

[0084] Figure 15C This diagram illustrates the threshold voltage distribution after the first programming in one embodiment of the present disclosure, separated by parity.

[0085] Figure 16 A flowchart of a memory operation method is shown in yet another embodiment of this disclosure;

[0086] Figure 17 An example of 4-bit data is shown in one embodiment of this disclosure;

[0087] Figure 18 A flowchart illustrating a memory operation method in one embodiment of this disclosure is shown;

[0088] Figure 19A This diagram illustrates the selection of a first read voltage and a second read voltage in one embodiment of the present disclosure.

[0089] Figure 19B Examples of DL, L-, L+, and regenerated LP data in one embodiment of this disclosure are shown; and

[0090] Figure 20 A flowchart illustrating a memory system operation method according to one embodiment of this disclosure is shown. Detailed Implementation

[0091] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0092] The features, structures, or characteristics described in this disclosure can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0093] The accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus omitting repeated descriptions of them. Some block diagrams shown in the drawings do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in at least one hardware module or integrated circuit, or in different network and / or processor devices and / or microcontroller devices.

[0094] The flowchart shown in the accompanying drawings is merely illustrative and does not necessarily include all content and steps, nor does it require execution in the described order. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0095] In this specification, the terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of at least one element / component / etc.; the terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markings and are not a limitation on the number of objects.

[0096] Multi-pass programming is a technique used in memory devices to store multiple bits of information in memory cells. For example, two-pass programming involves a first pass controlling the threshold voltage of the memory cell from the erase state to an intermediate state (coarse programming), and a second pass controlling the threshold voltage from the intermediate state to the target storage state (fine programming), thus storing N bits of information in the memory cell. Multi-pass programming in memory devices involves multiple programming operations on the memory cells to improve the efficiency of storing multiple bits in the memory cells. In the event of a power failure, data undergoing programming may be lost, necessitating power-down processing of this data.

[0097] Figure 1 A schematic diagram of an exemplary system having a memory according to an embodiment of this disclosure is shown. Figure 1 As shown, system 100 can be a mobile phone, desktop computer, portable computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include host 108 and memory system 102 having one or more memories 104 and memory controller 106.

[0098] The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be coupled to a memory controller 106 and configured to send data to or receive data from the memory 104 via the memory controller 106. For example, the host 108 may send program data in a programming operation or receive read data in a read operation. The host 108 is configured to receive and send instructions and commands from and to the memory controller 106 of the memory system 102, and to perform or implement various functions and operations provided in this disclosure, which will be described below.

[0099] Memory 104 can be any memory disclosed in this disclosure, such as NAND flash memory, which includes a page buffer having multiple sections. Note that, for illustrative purposes, NAND flash memory is merely one example of a memory. Memory 104 can include any suitable non-volatile memory, such as NOR flash memory, ferroelectric random access memory (FeRAM), phase change memory (PCM), magnetic random access memory (MRAM), spin-transfer torque random access memory (STT-RAM), or resistive random access memory (RRAM), etc. In some implementations, memory 104 includes three-dimensional (3D) NAND flash memory.

[0100] The storage controller 106 may be implemented by the following: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0101] According to some implementations, storage controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Storage controller 106 can manage data stored in memory 104 and communicate with host 108. In some implementations, storage controller 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, storage controller 106 is designed to operate SSDs in high duty cycle environments or as a data storage device for mobile devices (e.g., smartphones, tablets, laptops, etc.) and as an embedded MultiMediaCard (eMMC) for enterprise storage arrays. Storage controller 106 can be configured to control the operation of memory 104 by providing instructions such as read instructions to memory 104, for example, read, erase, and program operations. For example, the storage controller 106 can be configured to provide read instructions to the peripheral circuitry of the memory 104 to control read operations. The storage controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection (GC), logical-to-physical address translation, wear leveling, etc. In some implementations, the storage controller 106 is also configured to handle error correcting codes (ECC) regarding data read from or written to the memory 104. The storage controller 106 can also perform any other suitable function, such as formatting the memory 104.

[0102] Storage controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, storage controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC (Multi Media Card) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E (Peripheral Component Interconnect Express) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0103] The storage controller 106 and one or more memories 104 can be integrated into various types of memories, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0104] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the storage controller 106 and the memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA (Personal Computer Memory Card International Association) card), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), an SD card, a UFS, etc. The memory card 202 may also include a connector for linking the memory card to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0105] Figure 2B A block diagram of another memory system is shown as an example. Figure 2BAs shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD (Solid State Drive) 206. The SSD 206 may also include a connection between the SSD 206 and a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0106] Figure 2C A schematic diagram of an exemplary memory controller having a memory system is shown in an embodiment of this disclosure. For example... Figure 2C As shown, the storage controller 106 is coupled to the host 108 and one or more storage devices 104, and is used to control the host 108 to send data to the storage device 104 or to read data from the storage device 104 and return it to the host 108. The storage controller 106 includes at least: a controller processor 210, a host interface controller 211, a flash memory controller 212, a controller memory 213, a buffer memory 214, and an ECC (Error Correction Code) module 215.

[0107] The controller processor 210 is the core component of the storage controller, responsible for executing the controller's control logic and algorithms, and handling functions such as command queuing, address mapping, garbage collection, data compression, and input / output control. The controller processor 210 can be implemented using an embedded processor or an FPGA.

[0108] The host interface controller 211, coupled to both the host 108 and the controller processor 210, serves as the communication interface between the host and the storage controller. It is responsible for data transmission between the two, including data reading and writing, as well as command reception and transmission. It typically supports various interfaces (such as SATA (Serial Advanced Technology Attachment) and PCIe) and protocols (such as AHCI (Advanced Host Controller Interface) and NVMe (Non-Volatile Memory Express)) and provides data transmission functionality.

[0109] The flash memory controller 212 is coupled to the storage device 104 and the controller processor 210 respectively. It is the communication interface component between the storage device and the storage controller and is responsible for implementing functions such as data reading, writing, erasing and address mapping.

[0110] The controller memory 213, coupled to the controller processor 210, is a storage area for storing controller instructions and data, providing fast read / write operations and real-time control functions. The controller memory typically uses storage media such as NOR flash, NAND flash, or RAM.

[0111] The buffer memory 214, coupled to the controller processor 210, is a component used for temporary data storage and can also be used to cache instructions and data. It typically employs high-speed storage devices such as DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) to improve the read / write performance of the storage controller and reduce latency.

[0112] ECC module 215 is used for error detection and correction of data read from the storage device. ECC verification data is stored in reserved space in storage device 104 for data verification.

[0113] In one embodiment, the memory system further includes a backup power supply 109 for providing power to the system in the event of an abnormal power failure. The backup power supply 109 may be a capacitor.

[0114] Figure 3 This diagram illustrates a schematic circuit diagram of a memory including peripheral circuitry according to an embodiment of the present disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308 of NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0115] In some embodiments, the peripheral circuit 302 is configured to perform the operation methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the operation methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0116] In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0117] In some embodiments, each storage cell 306 can store 1 bit of data, 2 bits of data, or more bits of data; that is, it can be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or a higher-level type. A p-level cell (where p is a positive integer) can have 2... p There are 10 states (e.g., one state corresponds to one threshold voltage distribution range), so p bits of data can be stored. Specifically, an SLC type storage cell can have 2 states, thus storing 1 bit of data; an MLC type storage cell can have 4 states, thus storing 2 bits of data; a TLC type storage cell can have 8 states, thus storing 3 bits of data; a QLC type storage cell can have 16 states, thus storing 4 bits of data, and so on. In 2... p The state can include one erase state and 2... p -1 programming state. P-layer cell type NAND flash memory can be programmed and / or read page by page. During programming operations, the p-layer cell type NAND flash memory cell is programmed to have 2... p Each state, and each storage unit, is programmed to 2... p When a state is in the target programming state, it is said to be in the target programming state. For example... Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0118] In some embodiments, the sources of memory strings 308 within the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). For example, all memory strings 308 within the same block 304 have an array common source (ACS). Figure 3 As shown, the storage string 308 can be organized into multiple blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, that is, all storage cells 306 on the same block 304 are erased simultaneously.

[0119] In some embodiments, the transistor of the DSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0120] like Figure 3 As shown, the memory cells 306 of the memory string 308 can be coupled via word lines (WL) 318, which selects which row of memory cells 306 is affected by read and program operations. Peripheral circuitry 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each memory cell 306 targeted for operation via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and by sensing voltage and / or current signals from each memory cell 306 targeted for operation. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0121] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of this disclosure. (See diagram below.) Figure 4 As shown, the peripheral circuitry 302 may include a page buffer / sensor amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, input / output (I / O) circuitry 416, and a data bus 418. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0122] In some embodiments, the page buffer / sensor amplifier 404 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic unit 412. For example, the page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. As another example, the page buffer / sensor amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412 and to select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0123] The row decoder / WL driver 408 can be configured to be controlled by the control logic unit 412 and to select / deselect block 304 of the memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / WL driver 408 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 can also select / deselect and drive SSG line 314 and DSG line 313. The voltage generator 410 can be configured to be controlled by the control logic unit 412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages, etc., to be supplied to the memory cell array 301.

[0124] Control logic unit 412 can be coupled to each part of peripheral circuitry 302 and is configured to control the operation of each part. Register 414 can be coupled to control logic unit 412 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer inputs from the host (…). Figure 4 The input / output circuit 416 receives control commands (not shown) and relays them to the control logic unit 412, and buffers status information received from the control logic unit 412 and relays it to the host. The input / output circuit 416 can also be coupled to the column decoder / bit line driver 406 via the data bus 418, and acts as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0125] Figure 5 An exemplary block diagram of a page buffer / sensor amplifier is shown. Figure 5 It can be Figure 4 An example of a page buffer / sensor amplifier 404 used to implement the methods provided in embodiments of this disclosure. Figure 5 As shown, the page buffer / sensor amplifier 404 may include a plurality of page buffer circuits 500, each page buffer circuit 500 being coupled to a corresponding bit line in the bit line 316. That is, each page buffer circuit 500 can be coupled to a corresponding memory string 308 via the corresponding bit line 316 and is configured to temporarily store, during programming operations, a fragment of multi-bit data for programming the corresponding selected memory cell (coupled to the select word line 318 and the bit line 316 coupled to the selected memory cell). Figure 5 Four data latch circuits, D1 508, D2 510, D3 512 and DC 514, are illustrated exemplarily. Each data storage circuit can be, for example, a latch, which can be used to temporarily store 4 bits of data to be programmed into the QLC memory cell. It should be understood that the number of data latch circuits can be adjusted according to the number of bits of data to be programmed into the memory cell.

[0126] Each page buffer circuit 500 may include a bias circuit 501 coupled to a corresponding bit line 316 and configured to be controlled by a control logic unit 412 to apply a bit line voltage to the corresponding selected memory cell coupled to the corresponding bit line 316 during programming operations. Each page buffer circuit 500 may also include multiple latch circuits for storing non-data page information (i.e., any information other than the data bits in a data page). Figure 5 As shown, in some embodiments, the page buffer circuit 500 may include a sense latch circuit DS 502 configured to latch data based on the current flowing through the bit line. The page buffer circuit 500 may also include a data latch circuit DL 504, which may be used to temporarily store generation layer indication data and to latch result information after a verification operation is performed following the application of 0V or V_3BL to the bit line 316.

[0127] Figure 6 A flowchart illustrating a memory system operation method according to one embodiment of this disclosure is shown.

[0128] like Figure 6As shown in step S602, the storage controller sends a first programming operation command to the memory. This first programming operation command includes first data and a first address. The first data is data to be stored in the memory based on the first programming operation and a second programming operation. The first address corresponds to a first storage cell. In one embodiment, the first programming operation is the first pass of a multi-pass programming operation, and the second programming operation is the second pass of a multi-pass programming operation. In another embodiment, the first programming operation is a coarse programming operation, and the second programming operation is a fine programming operation.

[0129] S604, the memory receives a first programming operation command from the memory controller, and performs a first programming operation on a first memory cell to store the first data. Upon receiving the first programming operation command, the memory determines the first memory cell based on the first address in the command and performs the first programming operation on the first memory cell. In one embodiment, the first programming operation is a first pass programming operation, such as a coarse programming operation. In one embodiment, the first memory cell is a three-level cell (TLC), a four-level cell (QLC), or a multi-level cell (MLC).

[0130] S606, in response to a power outage, if the first programming operation has been completed, the storage controller sends a third programming operation command to the memory, wherein the third programming operation command includes first data and a second address, the second address corresponding to the second storage cell. The power outage can be a normal power outage or an abnormal power outage. In one embodiment, the execution result of the first programming operation can be obtained through a read status command. For example, the execution result of the first programming operation can be obtained through a read status command before the power outage occurs; or, the execution result of the first programming operation can be obtained through a read status command after the power outage occurs.

[0131] S608, the memory receives a third programming operation command from the memory controller. The third programming operation command includes first data and a second address, and generates level indicator data based on the first data. In one embodiment, the level indicator data is generated based on parity information of the first data.

[0132] S610, the memory performs a third programming operation on the second storage cell to store the layer indication data. The memory determines the second storage cell based on the second address in the third programming operation command, performs the third programming operation on the second storage cell based on the layer indication data, and thus stores the layer indication data in the second storage cell. In one embodiment, the third programming operation is a Single Level Cell (SLC) programming operation.

[0133] In the above embodiments, if a power failure occurs during the multiple programming operations on the first data, the second programming operation will not be performed on the storage unit that has already completed the first programming operation. Instead, the layer indication information of the first data will be obtained, and the layer indication information of the first data will be stored in the second storage unit through a third programming operation. This enables faster data storage, saves resources consumed by storage operations, shortens storage time, and better achieves data backup during power failures. Furthermore, the third programming operation uses SLC programming, which has a short execution time and consumes fewer resources, which is beneficial for data backup.

[0134] In one embodiment, in the event of an abnormal power failure, the backup power supply 109 in the memory system (as shown in the figure) will provide power. Figure 2C (As shown) provides power to the system, thereby supporting the data backup work in the event of a power outage.

[0135] The following is through Figure 7A and Figure 7B The implementation of the operation method is described from the perspectives of the storage controller and the memory, respectively.

[0136] Figure 7A A flowchart illustrating a storage controller operation method according to one embodiment of this disclosure is shown. In this embodiment, during a power outage, the controller activates a coarse data backup function via a setting characteristic command to perform the set power-off backup process.

[0137] like Figure 7A As shown in step S702, the storage controller sends a first programming operation command to the memory. This first programming operation command includes first data and a first address. The first data is data to be stored in the memory based on the first programming operation and the second programming operation. The first address corresponds to a first storage cell. In one embodiment, the first programming operation and the second programming operation correspond to the first and second programming operations in two programming operations, respectively.

[0138] S704, the storage controller sends a read status command to the memory and receives the execution result of the first programming operation command returned by the memory. Based on the execution result, the storage controller determines that the first programming operation has been completed.

[0139] S706, in response to a power failure, the storage controller sends a set feature command to the storage device, the set feature command including a first parameter indicating that the coarse data backup function of the storage device is enabled.

[0140] S708, after the first programming operation has been completed, the storage controller sends a third programming operation command to the memory, wherein the third programming operation command includes first data and a second address, the second address corresponding to the second storage cell. In one embodiment, the third programming operation is a single-level cell programming operation.

[0141] Figure 7B A flowchart illustrating a memory operation method according to one embodiment of this disclosure is shown. In this embodiment, when power is lost, the memory receives a setting characteristic command to enable the coarse data backup function to perform the set power-off backup process.

[0142] like Figure 7B As shown, in step S701, the memory receives a first programming operation command from the memory controller. The first programming operation command includes first data and a first address. A first programming operation is then performed on a first memory cell to store the first data. In one embodiment, the first programming operation corresponds to the first programming operation in a two-stage programming process.

[0143] S703, the memory receives a read status command from the memory controller and returns the execution result of the first programming operation.

[0144] S705, in response to a power failure, the memory receives a setting characteristic command from the memory controller, the setting characteristic command including a first parameter indicating that the memory's coarse data backup function is enabled.

[0145] S707, the memory receives a third programming operation command from the memory controller and generates layer indication data based on the parity information of the first data. In one embodiment, the layer indication data is generated by performing an XOR operation on the parity information of each page of the first data.

[0146] S709, the memory performs a third programming operation on the second storage cell of the memory to indicate data at the storage layer. In one embodiment, the third programming operation is a single-layer cell programming operation.

[0147] In one embodiment, the physical addresses of the first storage unit and the second storage unit are stored in a predetermined location in the memory.

[0148] In the above embodiments, when a power failure occurs, the coarse data backup function of the memory is enabled by setting a characteristic command to perform the power failure processing flow; for the first unit that has performed the first programming operation but has not yet performed the second programming operation, the second programming operation is no longer performed, but the first data is stored in the second storage unit through the third programming operation, so that the processing speed is faster and the processing flow is accurate and clear.

[0149] Figure 8 A flowchart illustrating a storage controller operation method in another embodiment of this disclosure is shown.

[0150] like Figure 8 As shown, in S802, the storage controller sends a first programming operation command to the memory. This first programming operation command includes first data and a first address. The first data is data to be stored in the memory based on the first programming operation and the second programming operation. The first address corresponds to a first storage cell. In one embodiment, the first programming operation corresponds to the first programming operation in a series of programming operations.

[0151] In step S804, the memory controller sends a read status command to the memory and receives the execution result of the first programming operation command returned by the memory. Based on this execution result, the memory controller determines that the first programming operation has been completed.

[0152] S806, the memory controller sends a second programming operation command to the memory, wherein the second programming operation command includes first data and a first address. In one embodiment, the second programming operation corresponds to the second programming operation in a multi-pass programming operation.

[0153] S808, in response to a power failure, the storage controller sends a setting characteristic command to the memory, the setting characteristic command including a first parameter indicating that the coarse data backup function of the memory is enabled.

[0154] S810, the storage controller sends a read status command to the memory and receives the execution result of the second programming operation command returned by the memory. Based on the execution result, the storage controller determines that the second programming operation has not yet been completed and stops the second programming operation.

[0155] S812, the memory controller sends a fourth programming operation command to the memory, wherein the fourth programming operation command includes first data and a third address, the third address corresponding to a third memory cell. In one embodiment, the fourth programming operation is a single-level cell programming operation.

[0156] In the above embodiments, when a power failure is sent during the second programming operation, the execution of the second programming operation is stopped. The storage of the first data can be completed as quickly as possible through single-layer unit programming operations, which can complete the backup of the first data faster, reduce the time occupied by storing the first data, and reduce the resources consumed.

[0157] Figure 9 A flowchart illustrating a memory operation method in another embodiment of this disclosure is shown.

[0158] As shown in Figure 9, in step S901, the memory receives a first programming operation command from the memory controller. The first programming operation command includes first data and a first address. The first programming operation is then performed on a first memory cell to store the first data. In one embodiment, the first programming operation corresponds to a first pass programming operation.

[0159] S903, the memory receives a read status command from the memory controller and returns the execution result of the first programming operation.

[0160] S905, the memory receives a second programming operation command from the memory controller, and performs a second programming operation on the first memory cell to store the first data. In one embodiment, the second programming operation corresponds to a fine programming operation.

[0161] S907, in response to a power failure, the memory receives a setting characteristic command from the memory controller and enables the memory's coarse data backup function.

[0162] S909, if the second programming operation has not been completed, the second programming operation is terminated, and the memory receives a fourth programming operation command from the memory controller. The fourth programming operation command includes first data and a third address, and the third address corresponds to the third memory cell.

[0163] S911, the memory performs a single-level cell (SLC) programming operation on the third storage unit of the memory to store the page data corresponding to the first data. In one embodiment, the first data is TLC data, corresponding to 3 pages of data, and is stored through 3 third storage units. In another embodiment, the first data is QLC data, corresponding to 4 pages of data, and is stored through 4 third storage units.

[0164] In the above embodiments, when a power failure occurs, for storage units that have not yet completed the second programming operation, the second programming operation will not continue to be executed. Instead, the data of each page of the first data will be stored through a single-level unit programming operation. The execution time is short, which reduces the consumption of resources and ensures the accurate and timely storage of data.

[0165] Figure 10AThis diagram illustrates the programming state of a storage unit in one embodiment of the present disclosure. Figure 10A As shown, the memory includes multiple word lines WLn-1, WLn, WLn+1, where n is a natural number. Each word line contains multiple strings STR0, STR1, and STR2. Under normal circumstances, the first and second programming operations are performed in a zigzag sequence, such as coarse programming and fine programming. In the diagram, "C" represents the first programming operation (e.g., coarse programming), and "F" represents the second programming operation (e.g., fine programming). Strings STR0, STR1, and STR2 on word line WLn-1 have undergone second programming operations of 2F, 4F, and 6F (the first programming operation has also been completed); strings STR0, STR1, and STR2 on word line WLn have undergone first programming operations of 1C, 3C, and 5C, and are currently undergoing second programming operations of 8F, 10F, and 12F; strings STR0, STR1, and STR2 on word line WLn+1 have undergone first programming operations of 7C, 9C, and 11C, but have not yet undergone a second programming operation.

[0166] Figure 10B according to Figure 10A An exemplary programming state signaling diagram applying embodiments of this disclosure is shown. Figure 10B As shown, the storage controller sends the first programming operation command to the storage device in the order of 1C, 3C, 5C, 7C, 9C, 11C to perform the first programming address / data loading. After tPROG time, the controller returns the programming operation completion status RBn (Ready / Busy_n, R / B_n) to the storage controller. The storage controller sends the second programming operation command to the storage device in the order of 2F, 4F, 6F, 8F, 10F, 12F to perform the second programming address / data loading. After tPROG time, the controller returns the programming operation completion status RBn to the storage controller. In one embodiment, R / B_n reflects the logical AND of the SR[6] (status register bit 6) values ​​of the corresponding NAND target or all LUNs on the volume.

[0167] Figure 10C according to Figure 10A An exemplary programming state signaling diagram applying an embodiment of this disclosure is shown. In the worst-case scenario of a power failure, the first coarse program operation for all strings on a word line WLn has been completed, and the power failure occurs during the second coarse program operation for the first string on the word line. Figure 10CTaking the 8F power failure as an example, a power failure occurs during the second programming operation of 8F on word line WLn's STR0. For the 8F currently undergoing the second programming operation, because it alters the VT (threshold voltage) distribution after the coarse programming of 1C, it cannot be backed up using level indicator data. Therefore, SLC programming is performed on each page (e.g., the four pages in the QLC), consuming 4*tPROG(SLC) time (step 1S). The pages corresponding to 3C, 5C, and 7C have not yet undergone the second programming, and their data needs to be backed up. Programming is performed using the level indicator data provided in this disclosure. The memory controller inputs the data for each page (e.g., the four pages in the QLC), and the NAND generates level indicator data based on the page data. SLC programming is then performed on the level indicator data (steps 3S, 5S, 7S). The memory system uses a backup power supply (e.g., a capacitor) to complete the above SLC programming.

[0168] Figure 11 This illustrates a command sequence for a memory operation method according to an embodiment of the present disclosure. For example... Figure 11 As shown, during a power outage, the storage controller sends a setting characteristic command, for example, EFh E2h 01h 00h 00h 00h, to enable coarse data backup. Then, it sends the data of each page to the NAND flash memory via a third programming command. For example, the LP / MP / UP data is sent to the NAND flash memory via the command sequence 80h-1Ah, and the XP data is sent to the NAND flash memory via the command Dah-80h-10h. The address in the command indicates the second address (physical address) corresponding to the layer-indicating data programming, which corresponds to the second storage cell. The data indicated by this layer is stored by performing SLC programming operations on this second storage cell. In one embodiment, the address in the Dah-80h-10h command indicates the second address; in another embodiment, the address in one of the 80h-1Ah commands indicates the second address.

[0169] The operation of the storage controller and memory after power-on is described below with reference to the accompanying drawings.

[0170] Figure 12 A flowchart illustrating a storage controller operation method in yet another embodiment of this disclosure is shown.

[0171] like Figure 12 As shown in S1202, when power is on, the storage controller sends a setting characteristic command to the memory. The setting characteristic command includes a second parameter, which indicates that the coarse data recovery function of the memory is enabled.

[0172] S1204, the storage controller sends a first read operation command to the memory to obtain third and fourth data. This first read operation command includes a first address and a first storage cell corresponding to that address. After power-on, the storage controller can read the first and second addresses corresponding to the data to be recovered from predetermined locations in the memory.

[0173] S1206, the storage controller sends a second read operation command to the memory to obtain layer indication data. The second read operation command includes a second address, which corresponds to a second storage cell.

[0174] S1208, first data is obtained based on layer indicator data, third data, and fourth data. In one embodiment, when the layer indicator data indicates an odd number, the third data is used as the first data; when the layer indicator data indicates an even number, the fourth data is used as the first data. The method for obtaining the first data based on the layer indicator data, third data, and fourth data will be described in detail below with reference to the figures.

[0175] In one embodiment, the method further includes: S1210, the storage controller sends a fifth programming operation command to the memory, the fifth programming operation command including first data and a first address, so that the memory performs a second programming operation on the first storage cell to store the first data. That is, after power-on, the second programming operation can continue to be performed on the original first storage cell to complete the storage of the first data.

[0176] In the above embodiments, upon power-on, the third and fourth data are read from the first storage unit via the first address, and the layer instruction data is read from the second storage unit via the second address. The first data is then recovered based on the layer instruction data, the third data, and the fourth data, thus ensuring data recovery.

[0177] In one embodiment, after obtaining the recovered first data, the storage controller sends a sixth programming operation command to the memory. This sixth programming operation command includes the first data and a fourth address, which corresponds to a fourth storage cell. The memory receives the sixth programming operation command from the storage controller and performs a programming operation on the fourth storage cell to store the first data. The first data is stored in the fourth storage cell, which is different from the first storage cell.

[0178] Figure 13 A flowchart of a memory operation method is shown in yet another embodiment of this disclosure.

[0179] like Figure 13 As shown in S1302, when powered on, the memory receives a setting characteristic command sent by the memory controller. The setting characteristic command includes a second parameter, which indicates that the coarse data recovery function of the memory is enabled.

[0180] S1302, the memory receives a first read operation command from the memory controller, the first read operation command including a first address and a first memory cell corresponding to the first address.

[0181] S1304, the memory performs a third read operation on the first memory cell based on the first layer read voltage to obtain third data. The first layer read voltage is a read voltage determined according to the odd-state voltage distribution.

[0182] S1306, the memory performs a fourth read operation on the first memory cell based on the second-level read voltage to obtain fourth data. The second-level read voltage is a read voltage determined according to the voltage distribution of even-numbered states.

[0183] S1308, the memory receives a second read operation command from the memory controller. The second read operation command includes a second address, which corresponds to a second memory cell. The second read operation is performed on the second memory cell to obtain layer indication data.

[0184] In one embodiment, the order of steps S1308 and S1302 can be interchanged; that is, the second read operation command is sent first, followed by the first read operation command. The corresponding command sequence can be combined with the following... Figure 14 Please provide an explanation.

[0185] In the above embodiments, the threshold voltage distribution after the first programming operation is read from the first storage unit through the first read operation command, and the layer indicator data is read from the second storage unit through the second read operation command, thereby obtaining the backed-up third data, fourth data and layer indicator data for the recovery of the first data.

[0186] In one embodiment, upon power-up, the memory receives a configuration command from the memory controller. This configuration command includes a second parameter indicating that the memory's coarse data recovery function should be enabled. The memory can then read a first address and a second address from predetermined locations within the memory, read third data, fourth data, and layer indication data based on the first and second addresses, and recover the first data. In this embodiment, the memory can perform these operations, saving resources for the memory controller.

[0187] Figure 14 This illustrates a command sequence for a memory operation method according to an embodiment of the present disclosure. For example... Figure 14As shown, during the enable data recovery bit stage, a setting characteristic command is sent, for example, EFh E2h 02h 00h 00h 00h; during the SLC indication sensing stage, a second read operation command is sent, for example, Dah 00h addr2 30h, wherein the second read operation command includes a second address addr2, which corresponds to a second storage cell; during the coarse data recovery stage, a first read operation command is sent, for example, 00h addr1 30h, wherein the first read operation command includes a first address addr1.

[0188] Figure 15A This diagram illustrates the threshold voltage distribution after a first programming operation in one embodiment of this disclosure. The threshold voltage of a QLC memory cell is used as an example in this illustration. Figure 15A As shown, after the first programming operation (the first programming operation, such as coarse programming), the threshold voltage distribution of different programming states of the QLC memory cell is as follows: Figure 15A As shown, there is overlap between adjacent programming states (Pn, Pn+1).

[0189] As shown in the figure, the programming states after the first programming operation are separated into even and odd states, such as... Figure 15B As shown, the even-numbered programming state layer indicator data is set to 0, and the odd-numbered programming state layer indicator data is set to 1.

[0190] Figure 15C This diagram illustrates the threshold voltage distribution separated by parity states after a first programming operation in one embodiment of this disclosure. For Figure 15A The threshold voltage distributions for different programming states shown can be further analyzed by separating the programming states after the first programming operation according to their odd / even states, as follows: Figure 15C As shown, the programming states P0, ..., P14 of even-numbered states are separated, and the programming states P1, ..., P15 of odd-numbered states are separated.

[0191] Figure 16 A flowchart illustrating a memory operation method according to one embodiment of this disclosure is shown. (The connection will be made in conjunction with...) Figure 5 The page buffer in the document describes the operation processing.

[0192] like Figure 16 As shown, in S1602, the memory receives pages of data from the memory controller. For example, corresponding to a QLC memory cell, it can employ... Figure 11 The command sequence shown in the figure receives a total of 4 pages of data: LP, MP, UP, and XP.

[0193] S1604, the memory latches or caches the data for each page. After receiving the data for each page, the memory caches the data in the internal data latch of the page buffer in the external circuit, for example... Figure 5The page buffers D1, ..., DN-1 and DC latches are stored in the page buffer or in the cache of the peripheral circuit.

[0194] S1606, the memory generates layer indicator data based on the data of each page. The peripheral circuitry generates corresponding 1-page layer indicator data based on N pages of data (i.e., N bits of data). For example, Figure 17 A 4-bit data (having 16 values ​​represented in Gray Code form) according to an embodiment of this disclosure is shown. For each of the 16 values, the generation layer instructs the data DL as a parity check for the corresponding 4-bit binary value (i.e., LP, MP, UP, and XP). For example, for Figure 17 The LV0 value (1,1,1,1,1) in the data represents the parity of the layer indicator data DL, which is 0. In some embodiments, the page layer indicator data can be temporarily stored in the internal latch of the page buffer, for example... Figure 5 In the DL 504, the DL 504 is typically configured to store 3BL bias information.

[0195] S1608, the peripheral circuit performs a single-level cell programming operation on the 1-page layer indicator data to store the layer indicator data into a memory cell (e.g., the first cell) with a predetermined address in the memory cell array.

[0196] In the above embodiments, the generation and programming storage of the layer indicator data of the first data are completed by using a latch through an external circuit, which is convenient and improves programming efficiency.

[0197] Figure 18 A flowchart illustrating a memory operation method in one embodiment of this disclosure is shown.

[0198] like Figure 18 As shown, in step S1801, the memory reads layer indicator data in an SLC manner. In one embodiment, the memory's peripheral circuitry performs an SLC read operation to read the layer indicator data stored in the memory cell array, for example... Figure 19B The layer indicates the data DL.

[0199] S1803, Read L- of coarse-programmed page data. In one embodiment, the peripheral circuitry performs a first read operation based on multi-level cells (e.g., QLC based if N=4) to read N pages of coarse-programmed data from the memory cell array as L- (e.g., third data). In some embodiments, given a set of gray codes, each gray code representing an N-bit data corresponding to N pages of data, in order to read the 2-bit data corresponding to the N-bit data in the first read operation... N For the nth value among the given values, the external circuit sets the read voltage to a first value (e.g., the first layer read voltage), which is equal to 2.N The threshold voltage distribution center of the (n-1)th value of the n-th value.

[0200] S1805, Read L+ of coarsely programmed page data. In one embodiment, the peripheral circuitry performs a second read operation based on multi-level cells (e.g., QLC based if N=4) to read N coarsely programmed pages of data from the memory cell array as L+ (e.g., fourth data). In some embodiments, given a set of Gray codes, each Gray code representing an N-bit data corresponding to N pages of data, in order to read the 2-bit data corresponding to the N-bit data in the second read operation... N For the nth value among the given values, the external circuit sets the read voltage to a second value (e.g., the second set of read voltages), which is equal to 2. N The threshold voltage distribution center of the nth value of the n values.

[0201] S1807, based on layer indicator data, L- and L+, regenerate the data for each page.

[0202] In the above embodiment, with QLC storage unit, page data recovery time = 2tR_qlc + tR_slc. That is, the time for 2 QLC reads and the time for 1 SLC read.

[0203] The following is combined Figure 19A and 19B describe Figure 18 Implementation of data reading in the middle.

[0204] Figure 19A An example read voltage is shown when reading L- and L+ as described in S1803 and S1805 above, according to one embodiment of the present disclosure. Figure 19A Used to set the read voltage to read L- and L+ for reconstruction. Figure 19B The LP data is shown. For example, to perform a first read operation to read the third value (LV2) out of 16 values ​​of a 4-bit data set, the peripheral circuit sets the read voltage R2- to the center of the threshold voltage distribution of the second value (LV1) out of 16 values. As another example, to perform a second read operation to read the third value (LV2) out of 16 values ​​of a 4-bit data set, the peripheral circuit sets the read voltage R2+ to the center of the threshold voltage distribution of the third value (LV2) out of 16 values. Figure 19A As shown, the reading voltages of R8-, R8+, R14-, and R14+ can be set similarly.

[0205] Figure 19B Examples of DL, L-, L+, and regenerated LP data are shown in some embodiments of this disclosure. Figure 17The original LP data in the four pages of data (LP, MP, UP, and XP) is shown. As described in S1807 above, the peripheral circuit regenerates the LP data by performing the logic operation ~DL&L-+DL&L+. Figure 19B It shows Figure 19B The regenerated LP data in the last column and Figure 17 The LP data is matched. In some embodiments, MP, UP, and XP data can be in a similar manner to... Figure 19B The method shown is to restore the regenerated LP data. When regenerating each data point in the MP, UP, and XP data, the corresponding L- and L+ may differ. Figure 19B The L- and L+ shown can be obtained from Gray code associated with N-bit data of LP, MP, UP, XP data, for example... Figure 17 The Gray code in the code. The logical operations used to regenerate each of the MP, UP, and XP data can be the same as or different from the logical operations used for the LP data described above.

[0206] Figure 20 A flowchart illustrating a memory operation method in one embodiment of this disclosure is shown.

[0207] like Figure 20 As shown, when the S2000 is powered on, the coarse data recovery function is enabled by setting the characteristics command.

[0208] S2002, the memory reads each page of the third data from the third storage unit in SLC mode. The third data refers to the N-bit data of each page stored in SLC mode.

[0209] S2004 rewrites the data of each page of the third data into the storage device in a multi-level cell manner.

[0210] S2006, the memory reads the layer indicator data of the first data from the second storage cell in an SLC manner.

[0211] S2008, the memory reads the coarse voltage threshold distribution of the first memory cell. For example, using... Figure 18 The diagram shows S1803 and S1805 reading L- and L+ of the coarse programming page data.

[0212] S2010, the memory recovers the first data based on the layer indicator data and coarse voltage threshold distribution of the first data.

[0213] S2012, the memory performs a second programming operation on the first storage cell based on the recovered first data to store the first data.

[0214] In the above embodiments, by reconstructing the N pages of data from the stored layer indicator data and the coarsely programmed N pages of data, the peripheral circuitry does not need to obtain the N pages of data from the storage controller after the coarse programming of the N pages of data and before the fine programming of the N pages of information. This can save storage resources of the storage controller.

[0215] Table 1 below compares the data volume, time, and space consumption of different power failure data backup solutions:

[0216]

[0217] Table 1

[0218] Table 1 shows the space and time consumption for backup in this disclosed technical solution for a die architecture with 8 strings and 8 planes. As can be seen from Table 1, this solution has significant advantages.

[0219] The technical solution disclosed herein can reduce power-off backup time and power-off backup space, without affecting performance during normal operation, such as tR / tPROG / ESUM (Error Summary) parameters.

[0220] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a controller memory including instructions that can be executed by a controller processor of a storage controller to perform the above-described method. Optionally, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0221] In an exemplary embodiment, a computer program product is also provided, including a computer program / instructions that, when executed by a processor, implement the methods described above.

[0222] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0223] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0224] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0225] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0226] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0227] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory system, comprising: A memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; as well as A memory controller coupled to the memory, wherein the memory controller is configured to: Send a first programming operation command to the memory, wherein the first programming operation command includes first data and a first address, the first data is data to be stored in the memory based on the first programming operation and the second programming operation, and the first address corresponds to a first memory cell; In response to a power failure, if the first programming operation has been completed, a third programming operation command is sent to the memory, wherein the third programming operation command includes the first data and the second address, and the second address corresponds to the second storage unit; The peripheral circuit is configured as follows: Receive the first programming operation command from the storage controller, and perform the first programming operation on the first storage cell of the memory to store the first data; Receive the third programming operation command from the storage controller, and instruct data based on the first data generation layer; A third programming operation is performed on the second storage cell of the memory to store the layer instruction data.

2. The memory system according to claim 1, characterized in that, The peripheral circuit is configured as follows: The layer indicator data is generated based on the parity information of the first data.

3. The memory system according to claim 2, characterized in that, The peripheral circuit is configured as follows: The parity check information of each page of the first data is XORed to generate the layer indicator data.

4. The memory system according to claim 1, characterized in that, The peripheral circuit is configured as follows: Perform a single-level cell programming operation on the second storage cell of the memory to store the layer instruction data.

5. The memory system according to claim 1, characterized in that, The storage controller is also configured to: Send a second programming operation command to the memory, the second programming command including the first data and the first address; In response to a power failure, if the second programming operation has not been completed, a fourth programming operation command is sent to the memory, wherein the fourth programming operation command includes the first data and a third address, and the third address corresponds to a third storage unit; The peripheral circuit is configured as follows: Receive the second programming operation command from the storage controller, and perform the second programming operation on the first storage cell of the memory to store the first data; The system receives the fourth programming operation command from the storage controller and performs a single-level cell programming operation on the third storage cell of the memory to store the page data corresponding to the first data.

6. The memory system according to claim 1, characterized in that, The storage controller is configured as follows: In response to a power failure, a setting characteristic command is sent to the memory, the setting characteristic command including a first parameter, the first parameter indicating that the coarse data backup function of the memory is enabled; The peripheral circuit is configured as follows: The system receives the setting feature command from the storage controller and enables the coarse data backup function of the storage device.

7. The memory system according to claim 1, characterized in that, The first storage unit is a three-layer unit or a four-layer unit.

8. The memory system according to claim 1, characterized in that, The storage controller is configured as follows: Upon power-up, a setting characteristic command is sent to the memory, the setting characteristic command including a second parameter, the second parameter indicating that the coarse data recovery function of the memory is enabled; Send a first read operation command to the memory to obtain third data and fourth data, wherein the first read operation command includes the first address; Send a second read operation command to the memory to obtain the layer indication data, wherein the second read operation command includes the second address; The first data is obtained based on the layer indication data, the third data, and the fourth data; The peripheral circuit is configured as follows: Receive the first read operation command from the storage controller, perform a third read operation on the first storage cell based on the first layer read voltage to obtain the third data, and perform a fourth read operation on the first storage cell based on the second layer read voltage to obtain the fourth data; The system receives a second read operation command from the storage controller and performs a second read operation on the second storage cell to obtain the layer indication data.

9. The memory system according to claim 8, characterized in that, The storage controller is configured as follows: Send a fifth programming operation command to the memory, the fifth programming operation command including the first data and the first address; The peripheral circuit is configured as follows: The system receives the fifth programming operation command from the storage controller and performs the second programming operation on the first storage unit to store the first data.

10. The memory system according to claim 8, characterized in that, The storage controller is configured as follows: A sixth programming operation command is sent to the memory, the sixth programming operation command including the first data and the fourth address, the fourth address corresponding to the fourth memory cell; The peripheral circuit is configured as follows: The system receives the sixth programming operation command from the storage controller and performs a programming operation on the fourth storage unit to store the first data.

11. The memory system according to claim 8, characterized in that, The first layer read voltage is determined based on the voltage distribution of the odd-numbered states; the second layer read voltage is determined based on the voltage distribution of the even-numbered states.

12. The memory system according to claim 11, characterized in that, The storage controller is configured as follows: When the layer indicator data indicates an odd number of states, the third data is used as the first data; When the layer indicator data indicates an even state, the fourth data is used as the first data.

13. The memory system according to claim 1, characterized in that, The storage controller is configured as follows: After sending a first programming operation command to the memory, a status read command is sent to the memory to obtain the execution result of the first programming operation; Determine whether the first programming operation has been completed based on the execution result of the first programming operation.

14. The memory system according to claim 1, characterized in that, It also includes a backup power supply to provide power to the memory system in the event of a power outage.

15. The memory system according to claim 14, characterized in that, The backup power source is a capacitor.

16. A storage controller, comprising: The controller memory is configured to store control instructions; as well as A controller processor, coupled to the controller memory and configured to execute the control instructions to perform processing, the processing including: Send a first programming operation command to the memory. The first programming operation command includes first data and a first address, wherein the first data is data to be stored in the memory based on the first programming operation and the second programming operation, and the first address corresponds to a first memory cell. In response to a power failure, if the first programming operation has been completed, a third programming operation command is sent to the memory. The third programming operation command includes the first data and a second address, wherein the second address corresponds to a second storage unit, so that the memory generates layer indication data based on the first data and performs a third programming operation on the second storage unit to store the layer indication data.

17. The storage controller according to claim 16, characterized in that, The process includes: The layer indicator data is generated based on the parity information of the first data.

18. The storage controller according to claim 16, characterized in that, The third programming operation is a single-level unit programming operation.

19. The storage controller according to claim 16, characterized in that, The process includes: Send a second programming operation command to the memory, the second programming command including the first data and the first address; In response to a power failure, if the second programming operation has not been completed, a fourth programming operation command is sent to the memory. The fourth programming operation command includes the first data and a third address, wherein the third address corresponds to a third storage cell, so that the memory performs a single-level cell programming operation on the third storage cell to store the page data corresponding to the first data.

20. The storage controller according to claim 16, characterized in that, The process includes: In response to a power outage, a setting characteristic command is sent to the memory, the setting characteristic command including a first parameter, the first parameter indicating that the coarse data backup function of the memory is enabled.

21. The storage controller according to claim 16, characterized in that, The first storage unit includes a three-layer unit or a four-layer unit.

22. The storage controller according to claim 16, characterized in that, The process includes: Upon power-up, a setting characteristic command is sent to the memory, the setting characteristic command including a second parameter, the second parameter indicating that the coarse data recovery function of the memory is enabled; Send a first read operation command to the memory to obtain third data and fourth data, wherein the first read operation command includes the first address; Send a second read operation command to the memory to obtain the layer indication data, wherein the second read operation command includes the second address; The first data is obtained based on the layer indication data, the third data, and the fourth data.

23. The storage controller according to claim 22, characterized in that, The process includes: A fifth programming operation command is sent to the memory, the fifth programming operation command including the first data and the first address, so that the memory performs the second programming operation on the first storage cell to store the first data.

24. The storage controller according to claim 22, characterized in that, The process includes; A sixth programming operation command is sent to the memory, the sixth programming operation command including the first data and a fourth address, the fourth address corresponding to a fourth storage unit, so that the memory performs a programming operation on the fourth storage unit to store the first data.

25. The storage controller according to claim 24, characterized in that, The process includes: After sending the first programming operation command to the memory, a status read command (readstatus) is sent to the memory to obtain the execution status of the first programming operation; The execution status of the first programming operation is used to determine whether the first programming operation has been completed.

26. The storage controller according to claim 22, characterized in that, The process of obtaining the first data based on the layer indication data, the third data, and the fourth data includes: When the layer indicator data indicates an odd number of states, the third data is used as the first data; When the layer indicator data indicates an even state, the fourth data is used as the first data.

27. The storage controller according to claim 16, characterized in that, It also includes a backup power supply to provide power to the memory system in the event of a power outage.

28. The storage controller according to claim 27, characterized in that, The backup power source is a capacitor.

29. A memory comprising: Storage cell array, and Peripheral circuitry coupled to the memory cell array; The peripheral circuit is configured as follows: Receive a first programming operation command from the storage controller, the first programming operation command including first data and a first address, wherein the first data is data to be stored in the memory based on the first programming operation and the second programming operation, and the first address corresponds to a first storage cell; Perform the first programming operation on the first storage unit to store the first data; In response to a power failure, if the first programming operation has been completed, a third programming operation command is received from the storage controller, the third programming operation command including the first data and the second address, wherein the second address corresponds to the second storage cell; Based on the data generated by the first data generation layer; A third programming operation is performed on the second storage cell of the memory to store the layer instruction data.

30. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: The layer indicator data is generated based on the parity information of the first data.

31. The memory according to claim 30, characterized in that, The peripheral circuit is configured as follows: The parity check information of each page of the first data is XORed to generate the layer indicator data.

32. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: Perform a single-level cell programming operation on the second storage cell of the memory to store the layer instruction data.

33. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: Receive a second programming operation command from the storage controller, the second programming command including the first data and the first address; Perform the second programming operation on the first storage unit to store the first data; In response to a power failure, if the second programming operation has not been completed, a fourth programming operation command is received from the storage controller, the fourth programming operation command including the first data and a third address, wherein the third address corresponds to a third storage cell; Perform a single-level cell programming operation on the third storage cell of the memory to store the page data corresponding to the first data.

34. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: In response to a power outage, a setting characteristic command is received from the storage controller. The setting characteristic command includes a first parameter, which indicates that the coarse data backup function of the storage is enabled.

35. The memory according to claim 29, characterized in that, The first storage unit is a three-layer unit or a four-layer unit.

36. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: When powered on, a setting characteristic command is received from the storage controller. The setting characteristic command includes a second parameter, which indicates that the coarse data recovery function of the storage is enabled. Receive a first read operation command from the storage controller, the first read operation command including the first address; A third read operation is performed on the first memory cell based on the first layer read voltage to obtain third data, and a fourth read operation is performed on the first memory cell based on the second layer read voltage to obtain fourth data; Receive a second read operation command from the storage controller, the second read operation command including the second address; A second read operation is performed on the second storage unit to obtain the layer indication data, so as to obtain the first data based on the layer indication data, the third data, and the fourth data.

37. The memory according to claim 36, characterized in that, The peripheral circuit is configured as follows: Receive a fifth programming operation command from the storage controller, the fifth programming operation command including the first data and the first address; Perform the second programming operation on the first storage unit to store the first data.

38. The memory according to claim 36, characterized in that, The peripheral circuit is configured as follows: Receive a sixth programming operation command from the storage controller, wherein the sixth programming operation command includes the first data and a fourth address, and the fourth address corresponds to a fourth storage cell; Perform a programming operation on the fourth storage unit to store the first data.

39. The memory according to claim 36, characterized in that, The first layer read voltage is determined based on the voltage distribution of the odd-numbered states; the second layer read voltage is determined based on the voltage distribution of the even-numbered states.

40. The memory according to claim 39, characterized in that, The process of obtaining the first data based on the layer indication data, the third data, and the fourth data includes: When the layer indicator data indicates an odd number of states, the third data is used as the first data; When the layer indicator data indicates an even state, the fourth data is used as the first data.

41. The memory according to claim 29, characterized in that, The peripheral circuit is configured as follows: After executing the first programming operation, a status read command is received from the storage controller, enabling the storage controller to obtain the execution status of the first programming operation and determine whether the first programming operation has been completed based on the execution status of the first programming operation.

42. A method of operating a memory, comprising: Receive a first programming operation command from the storage controller, the first programming operation command including first data and a first address, wherein the first data is data to be stored in the memory based on the first programming operation and the second programming operation, and the first address corresponds to a first storage cell; Perform the first programming operation on the first storage unit to store the first data; In response to a power failure, if the first programming operation has been completed, a third programming operation command is received from the storage controller, the third programming operation command including the first data and the second address, wherein the second address corresponds to the second storage cell; Based on the data generated by the first data generation layer; A third programming operation is performed on the second storage cell of the memory to store the layer instruction data.

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