Quantum circuit mapping method and related devices for neutral atom quantum chips

Abstract

This application discloses a quantum circuit mapping method and related apparatus for neutral atom quantum chips. The method includes traversing the quantum logic gates in the quantum circuit to obtain front-layer gates and back-layer gates; using the quantum logic gates whose qubits acting in the front-layer gates are not connected as target quantum logic gates; determining a movement scheme for the qubits acting in the target quantum logic gates based on the qubit movement distance and the change in distance between the qubits acting in the back-layer gates after the qubit movement; moving the qubits acting in the target quantum logic gates according to the movement scheme so that the target quantum logic gates can be directly executed; using the back-layer gates as quantum logic gates in the quantum circuit, and performing the traversal of the quantum logic gates in the quantum circuit to obtain front-layer gates and back-layer gates, until all quantum logic gates can be directly executed. Using this application embodiment can reduce qubit movement operations and improve the compilation speed of quantum circuits.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum circuit mapping method and related apparatus for neutral atom quantum chips. Background Technology

[0002] Neutral atom-based quantum computing is a cutting-edge technology that utilizes lasers to trap and manipulate neutral atoms (such as rubidium and cesium) as qubits. Its core lies in cooling atoms to near absolute zero and using optical tweezers arrays to fix them in specific positions, forming programmable two-dimensional or three-dimensional qubit arrays. Qubits are typically encoded in the hyperfine levels of atoms or excited to high Rydberg states, where the strong dipole interactions between Rydberg atoms enable efficient two-qubit quantum gate operations (such as those based on the Rydberg blocking effect).

[0003] Unlike superconducting circuits or ion trap solutions, neutral atom quantum chips, when executing dual gates acting on non-adjacent qubits, do not use quantum logic gates to swap qubits to achieve the execution of the dual gates. Instead, they utilize qubit movement operations to achieve the execution of the dual gates. This difference also brings a technical problem compared to superconducting circuits or ion trap solutions: qubit movement operations are relatively time-consuming. Summary of the Invention

[0004] This application provides a quantum circuit mapping method and related apparatus for neutral atom quantum chips, which can reduce the movement of qubits and improve the compilation speed of quantum circuits.

[0005] The first aspect of this application provides a quantum circuit mapping method for neutral atom quantum chips, including:

[0006] By traversing the quantum logic gates in the quantum circuit, the front-layer gate and the back-layer gate are obtained. The back-layer gate is a quantum logic gate that can only be executed after the front-layer gate has been executed.

[0007] The quantum logic gate in which the qubits in the preceding gate are not connected is taken as the target quantum logic gate;

[0008] The movement scheme of the qubits acting on the target quantum logic gate is determined based on the movement distance of the qubits and the change in the distance of the qubits acting on the subsequent gates after the qubits are moved.

[0009] The qubits acting on the target quantum logic gate are moved according to the moving scheme so that the target quantum logic gate can be executed directly;

[0010] The back-layer gate is used as a quantum logic gate in the quantum circuit, and the quantum logic gate in the quantum circuit is traversed as described in the execution step to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

[0011] Optionally, determining the qubit movement scheme for the target quantum logic gate based on the qubit movement distance and the change in qubit distance affected by the subsequent gate after the qubit movement includes:

[0012] Determine multiple shift schemes for the qubits acting on the target quantum logic gate;

[0013] The score for each movement scheme is calculated based on the distance the qubit moves and the change in qubit distance affected by the back gate after the qubit moves.

[0014] The move with the lowest score is determined as the optimal move.

[0015] Optionally, the method further includes:

[0016] The quantum logic gates in the front-layer gates that are not connected are determined based on the current topology of the neutral atom quantum chip, and the topology is used to characterize the position of the qubits in the neutral atom quantum chip.

[0017] Optionally, before traversing the quantum logic gates in the quantum circuit to obtain the previous and next layer gates, the method further includes:

[0018] The quantum circuit can be transformed based on the basic gates supported by the neutral atom quantum chip.

[0019] Optionally, the basic single gate supported by the neutral atom quantum chip includes R. X Door, R Y Door and R Z The transformation of any single gate in the quantum circuit based on the basic single gate supported by the neutral atom quantum chip includes:

[0020] If the nearest preceding gate of any single gate in the quantum circuit is R X For a door, the conversion is performed according to method one, where method one is: U = R X (φ)·R Z (θ)·R X (λ);

[0021] If the nearest preceding gate of any single gate in the quantum circuit is R Y or R Z For a door, the arbitrary single door is converted according to method two, where method two is: U = R Z(φ)·R Y (θ)·R Z (λ);

[0022] Where φ, θ, and λ are rotation angles.

[0023] Optionally, the method further includes:

[0024] The front doors are layered according to the type of each individual door in the front layer.

[0025] Optionally, the step of dividing the front doors into layers according to the type of individual doors in the front layer includes:

[0026] Determine the type of each door in the front layer, and group doors of the same type into the same layer;

[0027] Determine the crosstalk between each double door in the front layer and each single door in each layer, and classify each double door in the front layer and the single door with the least crosstalk into the same layer.

[0028] A second aspect of this application provides a quantum circuit mapping device for neutral atom quantum chips, characterized in that it includes:

[0029] A logic gate partitioning unit is used to traverse the quantum logic gates in the quantum circuit to obtain the front-layer gates and the back-layer gates. The back-layer gates are quantum logic gates that can only be executed after the front-layer gates have been executed.

[0030] A logic gate determination unit is used to identify a quantum logic gate in which the qubits acting in the previous layer gate are not connected as the target quantum logic gate.

[0031] The movement scheme determination unit is used to determine the movement scheme of the qubits acting on the target quantum logic gate based on the movement distance of the qubits and the change in the distance between the qubits acting on the back-layer gate after the qubits are moved.

[0032] A logic gate mapping unit is used to move the qubits acting on the target quantum logic gate according to the moving scheme, so that the target quantum logic gate can be directly executed;

[0033] The cyclic mapping unit is used to treat the back-layer gate as a quantum logic gate in the quantum circuit, and to perform the step of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

[0034] A third aspect of this application provides an electronic device, including: a processor and a memory;

[0035] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0036] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application.

[0037] This application provides a quantum circuit mapping method and related apparatus for neutral atom quantum chips. The method involves traversing the quantum logic gates in the quantum circuit to obtain a front-layer gate and a back-layer gate, where the back-layer gate is a quantum logic gate that can only be executed after the front-layer gate has finished executing. The method uses a quantum logic gate whose qubits in the front-layer gate are not connected as the target quantum logic gate. Based on the qubit movement distance and the change in distance between the qubits in the back-layer gate after the qubit movement, a movement scheme for the qubits in the target quantum logic gate is determined. The qubits in the target quantum logic gate are moved according to this movement scheme so that the target quantum logic gate can be directly executed. The back-layer gate is then used as the quantum logic gate in the quantum circuit, and the process of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate is repeated until all quantum logic gates can be directly executed.

[0038] It can be seen that by determining the qubit movement scheme of the target quantum logic gate based on the qubit movement distance and the change in the distance between the qubits acting on the subsequent gates after the qubit movement, the number of qubit movement operations can be reduced, thereby improving the compilation speed of quantum circuits. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 An example system block diagram of a quantum circuit mapping method for neutral atom quantum chips provided in one embodiment of this application is shown;

[0041] Figure 2 A flowchart illustrating a quantum circuit mapping method for neutral atom quantum chips according to an embodiment of this application is shown.

[0042] Figure 3A schematic diagram of the topology of a neutral atom quantum chip provided in one embodiment of this application is shown;

[0043] Figure 4 A schematic diagram of the topology of a neutral atom quantum chip provided in another embodiment of this application is shown;

[0044] Figure 5 This illustration shows a schematic diagram of the structure of a quantum circuit mapping device for neutral atom quantum chips according to an embodiment of this application;

[0045] Figure 6 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0048] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data. n A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0049] Please refer to Figure 1 This illustrates an example system block diagram of a quantum circuit mapping method for neutral atom quantum chips according to an embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0050] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0051] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0052] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0053] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0054] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0055] Please refer to Figure 2 This document illustrates a flowchart of a quantum circuit mapping method for neutral atom quantum chips according to an embodiment of this application. This method can be applied to computer devices, which refer to electronic devices capable of data computation and processing. The method may include the following steps:

[0056] Step 201: Traverse the quantum logic gates in the quantum circuit to obtain the front-layer gates and the back-layer gates. The back-layer gates are quantum logic gates that can only be executed after the front-layer gates have finished executing.

[0057] In this case, the qubits with the effect of the back gate are at least partially the same as those with the effect of the front gate.

[0058] Before performing step 201, the method also includes operations such as multi-gate decomposition and basic logic gate optimization of the quantum circuit.

[0059] Among them, the multi-gate decomposition of quantum circuits aims to use decomposition operations to transform arbitrary quantum circuits submitted by users into quantum circuits that can be directly executed by neutral atom chips. For example, assuming that the quantum logic gates supported by the neutral atom chip are CZ, CNOT, and R... X R Y and R Z Then, it is necessary to convert quantum logic gates of the types mentioned above into the basic quantum logic gate.

[0060] The optimization of the fundamental logic gates in quantum circuits aims to reduce the number of basic logic gates using operations such as gate cancellation, gate merging, and gate transformation. After the above multi-control gate decomposition, only CZ and CNOT two-qubit gates (two-gate) and single-qubit gates (single-gate) remain in the quantum circuit, while the single-qubit gate supported by the neutral atom chip is only R. X R Y and R Z The purpose of basic logic gate optimization is to merge various single-gate transformations into these three single gates.

[0061] Gates that perform the same operation but in opposite directions (i.e., their angles are negative of each other) or whose operations are essentially inverses of each other, i.e., logic gate cancellation, can be directly eliminated from the quantum circuit. Basic logic gate merging, where consecutive single gates of the same type can be merged into one gate without changing the gate type, is another key aspect. For logic gate conversion, in superconducting circuits or ion trap quantum computing, all consecutive single gates are first converted into U3 gates, and then the U3 gates are converted into R(φ) gates. Quantum computing based on neutral atoms differs from superconducting circuits or ion trap schemes.

[0062] Furthermore, before traversing the quantum logic gates in the quantum circuit to obtain the previous and next layer gates, the method further includes:

[0063] The quantum circuit can be transformed based on the basic gates supported by the neutral atom quantum chip.

[0064] Specifically, the basic single gate supported by the neutral atom quantum chip includes R X Door, R Y Door and R Z The transformation of any single gate in the quantum circuit based on the basic single gate supported by the neutral atom quantum chip includes:

[0065] If the nearest preceding gate of any single gate in the quantum circuit is R X For a door, the conversion is performed according to method one, where method one is: U = R X (φ)·R Z (θ)·R X (λ);

[0066] If the nearest preceding gate of any single gate in the quantum circuit is R Y or R Z For a door, the arbitrary single door is converted according to method two, where method two is: U = R Z (φ)·R Y (θ)·R Z (λ);

[0067] Where φ, θ, and λ are rotation angles.

[0068] As can be seen, by using the above method to transform any single gate, adjacent single gates of the same type can be merged after the transformation, thereby reducing the number of quantum logic gates and thus reducing the depth of quantum circuits, which is beneficial to improving the execution accuracy of quantum circuits.

[0069] Step 202: Select the quantum logic gate in which the qubits in the previous layer gate are not connected as the target quantum logic gate.

[0070] Prior to step 202, the method may further include:

[0071] The quantum logic gates in the front-layer gates that are not connected are determined based on the current topology of the neutral atom quantum chip, and the topology is used to characterize the position of the qubits in the neutral atom quantum chip.

[0072] For example, such as Figure 3 The diagram illustrates a schematic topological structure of a neutral atom quantum chip according to an embodiment of this application. If the quantum logic gates include a dual gate CZ1 acting on qubits q0 and q1 and a gate acting on qubits q3 and q4... 11 The two-door CZ2, from Figure 3 As can be seen, qubits q0 and q1 are directly connected, and qubits q3 and q4 are directly connected. 11 Since they are not directly connected, the dual-gate CZ2 is the target quantum logic gate.

[0073] Step 203: Determine the qubit movement scheme for the target quantum logic gate based on the qubit movement distance and the change in qubit distance to the back gate after the qubit movement.

[0074] In step 203, namely, determining the qubit movement scheme for the target quantum logic gate based on the qubit movement distance and the change in qubit distance to the back-layer gate after the qubit movement, includes:

[0075] Determine multiple shift schemes for the qubits acting on the target quantum logic gate;

[0076] The score for each movement scheme is calculated based on the distance the qubit moves and the change in qubit distance affected by the back gate after the qubit moves.

[0077] The move with the lowest score is determined as the optimal move.

[0078] For example, suppose the quantum logic gates include a dual gate CZ1 acting on qubits q0 and q2, and a gate acting on qubits q3 and q4. 11 The dual-gate CZ2 and the action on qubits q8 and q 11 The dual-gate CZ3, the current topology of neutral atom quantum chips is still as... Figure 3 As shown. The qubit q, which has a combined effect with the dual-gate CZ3 and dual-gate CZ2. 11 Therefore, CZ1 and CZ2 are the front doors, and CZ3 is the back door.

[0079] A Cartesian coordinate system is established with the positions of qubits q0 and q1 as the origin. The distance the qubit moves is represented by SCore1, and the change in the distance of the qubit affected by the back gate after the qubit moves is represented by SCore2. There are currently two moving schemes:

[0080] 1. For the front gate CZ1, move qubit q1 to (0,1) and move qubit q2 to (0,0), SCore1 = 1 + 1 = 2; CZ3 is unaffected after the move, SCore1 = 0;

[0081] 2. For the front-layer gate CZ2, move qubit q2 to (1,1), and move qubit q... 11 Moving to (0,1), SCore1 = 1 + 3 = 4; CZ3 is affected after the move, and the qubits q8 and q... 11 The distance changes from 2 to 1, SCore2 = -1;

[0082] Therefore, if we take the minimum value of the sum of SCore1 and SCore2, then movement scheme one is the optimal movement scheme.

[0083] Step 204: Move the qubits that act on the target quantum logic gate according to the moving scheme so that the target quantum logic gate can be executed directly.

[0084] Step 205: Use the back-layer gate as a quantum logic gate in the quantum circuit, and execute the step described in the step of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

[0085] It should be noted that since the topology of the neutral atom quantum chip changes after the qubits are moved, the front and back gates need to be redefined based on the new topology of the neutral atom quantum chip.

[0086] This application provides a quantum circuit mapping method and related apparatus for neutral atom quantum chips. The method involves traversing the quantum logic gates in the quantum circuit to obtain a front-layer gate and a back-layer gate, where the back-layer gate is a quantum logic gate that can only be executed after the front-layer gate has finished executing. The method uses a quantum logic gate whose qubits in the front-layer gate are not connected as the target quantum logic gate. Based on the qubit movement distance and the change in distance between the qubits in the back-layer gate after the qubit movement, a movement scheme for the qubits in the target quantum logic gate is determined. The qubits in the target quantum logic gate are moved according to this movement scheme so that the target quantum logic gate can be directly executed. The back-layer gate is then used as the quantum logic gate in the quantum circuit, and the process of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate is repeated until all quantum logic gates can be directly executed.

[0087] It can be seen that by determining the qubit movement scheme of the target quantum logic gate based on the qubit movement distance and the change in the distance between the qubits acting on the subsequent gates after the qubit movement, the number of qubit movement operations can be reduced, thereby improving the compilation speed of quantum circuits.

[0088] In one embodiment provided in this application, the method further includes:

[0089] The front doors are layered according to the type of each individual door in the front layer.

[0090] Specifically, the step of dividing the front doors into layers according to the type of each individual door in the front layer includes:

[0091] Determine the type of each door in the front layer, and group doors of the same type into the same layer;

[0092] Determine the crosstalk between each double door in the front layer and each single door in each layer, and classify each double door in the front layer and the single door with the least crosstalk into the same layer.

[0093] Crosstalk can be determined by the position of the qubits acting on the quantum logic gates. The farther apart the qubits are, the weaker the crosstalk; the closer the qubits are, the stronger the crosstalk.

[0094] For example, such as Figure 4 The diagram illustrates a topological structure of a neutral atom quantum chip according to another embodiment of this application. The quantum logic gates include a single gate RX1 acting on qubit q0, a double gate CZ1 acting on qubits q1 and q2, a single gate RY1 acting on qubit q3, a double gate CZ2 acting on qubits q4 and q5, a single gate RZ1 acting on qubit q6, a double gate CZ3 acting on qubits q7 and q8, and gates acting on qubits q9 and q1. 10 The dual-gate CZ4, acting on the q-qubit 11 and q 12 The dual-gate CZ5, acting on the q-qubit 13 The single gate RX2. It can be seen that the above quantum logic gates do not have qubits with the same function, so they all belong to the previous layer gates.

[0095] If the basic single gate supported by the neutral atom quantum chip includes R X Door, R Y Door and R Z The gate can be divided into three layers. For the quantum logic gates mentioned above, the first layer includes R. X The doors include single doors RX1 and RX2; the second layer includes R Y Doors, including single door RY1; the first layer includes R Z The gate, including the single gate RZ1, is divided into single gates. Then, the remaining dual gates are divided according to crosstalk.

[0096] from Figure 4 It can be seen that the qubits q9 and q are activated by the double-gate CZ4. 10 The qubit q0 acting from a single gate RX1 and the qubit q acting from a single gate RX2 13 Since both are 2, they are furthest apart, thus minimizing crosstalk. Therefore, dual-gate CZ4, single-gate RX1, and single-gate RX2 are grouped into the same layer, and they are executed first. The qubits q4 and q5 act on dual-gate CZ2, and the qubits q5 act on dual-gate CZ5. 11 and q 12 The qubits q3 acting on single-gate RY1 are all 3, the furthest away, thus minimizing crosstalk. Therefore, dual-gate CZ2 and dual-gate CZ5 are grouped with single-gate RY1 in the same layer, and they are executed after the previous layer has finished. Finally, the remaining dual-gate CZ1 and dual-gate CZ3 are grouped with single-gate RZ1 in the same layer, and they are executed after the previous layer has finished.

[0097] It can be seen that by layering the front-end gates, the technical problem that different types of single gates cannot be executed on the same layer when a neutral atom chip executes a single gate on a quantum circuit can be solved, which leads to an increase in the number of circuit layers and an increase in circuit execution time.

[0098] Figure 5 A schematic diagram of a quantum circuit mapping device for a neutral atom quantum chip according to an embodiment of this application is shown. The device includes:

[0099] The logic gate partitioning unit 501 is used to traverse the quantum logic gates in the quantum circuit to obtain the front-layer gates and the back-layer gates. The back-layer gates are quantum logic gates that can only be executed after the front-layer gates have been executed.

[0100] The logic gate determination unit 502 is used to identify the quantum logic gate in which the qubits acting in the previous layer gate are not connected as the target quantum logic gate.

[0101] The movement scheme determination unit 503 is used to determine the movement scheme of the qubits acting on the target quantum logic gate based on the movement distance of the qubits and the change in the distance between the qubits acting on the back layer gate after the qubits are moved.

[0102] The logic gate mapping unit 504 is used to move the qubits acting on the target quantum logic gate according to the moving scheme, so that the target quantum logic gate can be directly executed.

[0103] The cyclic mapping unit 505 is used to treat the back-layer gate as a quantum logic gate in the quantum circuit, and to perform the step of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

[0104] Figure 6 The diagram illustrates the structure of a computer device according to an embodiment of this application, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system of the quantum circuit mapping method for neutral atom quantum chips in any of the above embodiments.

[0105] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system of the quantum circuit mapping method for neutral atom quantum chips in any of the above embodiments.

[0106] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system of the quantum circuit mapping method for neutral atom quantum chips in any of the above embodiments.

[0107] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0108] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0109] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0110] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0111] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0112] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0117] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum circuit mapping method for neutral atom quantum chips, characterized in that, include: By traversing the quantum logic gates in the quantum circuit, the front-layer gate and the back-layer gate are obtained. The back-layer gate is a quantum logic gate that can only be executed after the front-layer gate has been executed. Determine the type of each door in the front layer, and group doors of the same type into the same layer; Determine the crosstalk between each double door in the front layer and each single door in each layer, and classify each double door in the front layer and the single door with the least crosstalk into the same layer; The quantum logic gate in which the qubits in the preceding gate are not connected is taken as the target quantum logic gate; The movement scheme of the qubits acting on the target quantum logic gate is determined based on the movement distance of the qubits and the change in the distance of the qubits acting on the subsequent gates after the qubits are moved. The qubits acting on the target quantum logic gate are moved according to the moving scheme so that the target quantum logic gate can be executed directly; The back-layer gate is used as a quantum logic gate in the quantum circuit, and the quantum logic gate in the quantum circuit is traversed as described in the execution step to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

2. The method according to claim 1, characterized in that, The method for determining the qubit movement scheme of the target quantum logic gate based on the qubit movement distance and the change in qubit distance affected by the subsequent gates after the qubit movement includes: Determine multiple shift schemes for the qubits acting on the target quantum logic gate; The score for each movement scheme is calculated based on the distance the qubit moves and the change in qubit distance affected by the back gate after the qubit moves. The move with the lowest score is determined as the optimal move.

3. The method according to claim 1, characterized in that, The method further includes: The quantum logic gates in the front-layer gates that are not connected are determined based on the current topology of the neutral atom quantum chip, and the topology is used to characterize the position of the qubits in the neutral atom quantum chip.

4. The method according to claim 3, characterized in that, Before traversing the quantum logic gates in the quantum circuit to obtain the previous and next gates, the method further includes: The quantum circuit can be transformed based on the basic gates supported by the neutral atom quantum chip.

5. The method according to claim 4, characterized in that, The basic single gates supported by the neutral atom quantum chip include Door, Door and The transformation of any single gate in the quantum circuit based on the basic single gate supported by the neutral atom quantum chip includes: If the nearest preceding gate of any single gate in the quantum circuit is For a door, the conversion is performed according to method one, where method one is: ; If the nearest preceding gate of any single gate in the quantum circuit is or For doors, the conversion of any single door is performed according to method two, which is: ; in, 、 、 The angle is the rotation angle.

6. A quantum circuit mapping device for neutral atom quantum chips, characterized in that, include: A logic gate partitioning unit is used to traverse the quantum logic gates in the quantum circuit to obtain the front-layer gates and the back-layer gates. The back-layer gates are quantum logic gates that can only be executed after the front-layer gates have been executed. The logic gate partitioning unit is also used to determine the type of a single gate in the previous layer gate, and to partition single gates of the same type into the same layer; The logic gate partitioning unit is also used to determine the crosstalk between each double gate in the front layer and each single gate in each layer, and to partition each double gate in the front layer and the single gate with the least crosstalk into the same layer. A logic gate determination unit is used to identify a quantum logic gate in which the qubits acting in the previous layer gate are not connected as the target quantum logic gate. The movement scheme determination unit is used to determine the movement scheme of the qubits acting on the target quantum logic gate based on the movement distance of the qubits and the change in the distance between the qubits acting on the back-layer gate after the qubits are moved. A logic gate mapping unit is used to move the qubits acting on the target quantum logic gate according to the moving scheme, so that the target quantum logic gate can be directly executed; The cyclic mapping unit is used to treat the back-layer gate as a quantum logic gate in the quantum circuit, and to perform the step of traversing the quantum logic gates in the quantum circuit to obtain the front-layer gate and the back-layer gate, until all quantum logic gates can be directly executed.

7. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-5.

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