Novel Split-Gate MOS Transistor with Gradient-Doped Epitaxial Layer and Its Fabrication Method

Abstract

This invention relates to the field of semiconductor fabrication technology, specifically disclosing a novel split-gate MOS transistor with a gradient-doped epitaxial layer and its fabrication method. The MOS transistor includes a substrate; a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially disposed on one side of the substrate; a first gradient layer disposed between the first and second epitaxial layers; and a second gradient layer disposed between the second and third epitaxial layers. The doping concentration of the first gradient layer is an exponential gradient concentration, and the doping concentration of the second gradient layer is a Gaussian gradient concentration. The doping elements of the second epitaxial layer include C and Ge. In this invention, the doping gradient is directly formed during the epitaxial growth stage, and the exponential and Gaussian nonlinear doping distribution is achieved through mass flow control, avoiding the influence of high-temperature diffusion on the reshaping of the gradient curve, and stabilizing the electric field peak on the substrate side, thus achieving decoupling and synergistic optimization of BV and Rds(on).

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, specifically to a novel split-gate MOS transistor containing a graded-doped epitaxial layer and its fabrication method. Background Technology

[0002] In the development of MOSFETs, split-gate (SGT) devices reduce switching losses by adding a source electrode between the gate and drain. The trench of the split-gate structure has two parts: the upper electrode is the control gate electrode and the lower electrode is the shielded gate source electrode, which is connected to the source through a separate contact. It is equivalent to an extension of the field plate inside the device to balance the charge in the drift region. Since the gate and drain regions are only isolated by gate oxide, the traditional trench MOSFET will limit its application scenarios due to the high switching losses caused by the high gate-drain capacitance.

[0003] To address the aforementioned issues, existing technologies have proposed multilayer epitaxial structures and doping concentration patterns, and disclosed gradient layer and split gate trench structures. However, the doping gradient mainly depends on high-temperature annealing diffusion after ion implantation. Since the diffusion coefficient of phosphorus / boron is extremely sensitive to temperature at high temperatures, and the superposition of multiple annealing thermal budgets can easily lead to the reconstruction of the gradient curve shape and the drift of the electric field peak position, this results in problems such as large dispersion of breakdown voltage (BV), significant temperature degradation of on-state resistance (Rds(on)), and poor batch consistency in manufacturing. Summary of the Invention

[0004] The purpose of this invention is to provide a novel split-gate MOS transistor with a graded-doped epitaxial layer and its fabrication method, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A novel split-gate MOS transistor containing a graded-doped epitaxial layer, the MOS transistor comprising:

[0007] Substrate;

[0008] A first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are sequentially disposed on one side of the substrate;

[0009] A P-type body region is disposed on the side of the third epitaxial layer away from the substrate; the P-type body region is provided with a main trench etched toward the substrate.

[0010] A first gradient layer is disposed between a first epitaxial layer and a second epitaxial layer, and a second gradient layer is disposed between a second epitaxial layer and a third epitaxial layer; the doping concentration of the first gradient layer is an exponential gradient concentration, and the doping concentration of the second gradient layer is a Gaussian gradient concentration; wherein, the doping elements of the second epitaxial layer include C and Ge;

[0011] A split gate trench extending toward the substrate based on the third epitaxial layer in the main trench;

[0012] N+ source regions and P+ contact regions are set at the top of both sides of the trench;

[0013] A deposited metal layer is disposed on the surface of the device. The metal layer adopts an AlCu and TiN stacked structure, and the metal layer achieves ohmic contact with the N+ source region and the P+ contact region.

[0014] A passivation layer is disposed on the metal layer, the material of the passivation layer being SiN, and a back drain metal is disposed on the side of the substrate away from the first epitaxial layer, the back drain metal being an Au and Ti stacked structure.

[0015] As a further aspect of the present invention: the substrate is an N+ type substrate with a thickness of 300 μm; the main material is single-crystal silicon, the doping element is P, and the doping concentration is 1×10⁻⁶. 20 cm -3 The first, second, and third epitaxial layers are all N-type silicon, doped with P; their thicknesses are 5 μm, 2 μm, and 3 μm, respectively; and their concentrations are 5 × 10⁻⁶. 14 cm -3 2×10 16 cm -3 and 8×10 14 cm -3 .

[0016] As a further aspect of the present invention: the doping element of the P-type body region is B, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 The depth is 2μm.

[0017] As a further aspect of the present invention: the doping concentration of the first gradient layer is in the range of 5 × 10⁻⁶. 14 cm -3 Up to 2×10 16 cm -3 The doping concentration range of the second gradient layer is 8 × 10⁻⁶. 14 cm -3 Up to 2×10 16 cm -3 The thickness of both the first gradient layer and the second gradient layer is 60 nm.

[0018] As a further aspect of the present invention: the split gate trench extends 0.5 μm into the first epitaxial layer; the split gate trench has a depth of 10 μm, a width of 0.6 μm, a bottom fillet radius of 0.3 μm, and a sidewall structure of 12 nm SiO2 and 60 nm intrinsic Si buffer layer; internally, a 3 μm shielding gate, a 25 nm oxygen isolation gate, and a 2 μm control gate are stacked sequentially.

[0019] As a further aspect of the present invention: the depth of the N+ source region is 0.5 μm, the doping element is P, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 The depth of the P+ contact region is 0.3 μm, the doping element is B, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 .

[0020] The present invention also provides a method for fabricating a novel split-gate MOS transistor containing a graded-doped epitaxial layer, the method comprising:

[0021] S1: Select an N+ type single crystal silicon substrate as the starting material, place the substrate into a vacuum loading chamber, and purge with nitrogen for 30 seconds to complete the initial cleaning of surface particles;

[0022] S2: The first epitaxial layer is grown on the substrate using a reduced-pressure chemical vapor deposition process;

[0023] S3: The first gradient layer is grown in situ on the upper surface of the first epitaxial layer;

[0024] S4: Continue to grow the second epitaxial layer on the first gradient layer using a reduced pressure CVD process;

[0025] S5: Grow a second gradient layer in situ on the upper surface of the second epitaxial layer;

[0026] S6: The third epitaxial layer is grown on the second gradient layer using PECVD process;

[0027] S7: A P-type body region is formed on the surface of the third epitaxial layer by boron ion implantation, followed by rapid thermal annealing (RTA) activation annealing.

[0028] S8: Trenches are formed on the P-type body region towards the substrate using ICP-RIE dry etching process;

[0029] S9: After the trench etching is completed, an intrinsic silicon buffer layer is deposited on the trench sidewall using LPCVD process;

[0030] S10: A gate oxide layer is grown on the inner wall of the trench and the surface of the body region using a low-temperature dry oxygen thermal oxidation process;

[0031] S11: P-type polysilicon is deposited on the gate oxide layer at the bottom of the trench to form a shielded gate source electrode. The shielded gate electrode is etched back and an oxide layer is deposited on top of it using PECVD process as a protective isolation layer. The left control gate trench and the right control gate trench are formed by dry etching. The bottom of the trench is flush with the lower surface of the body region.

[0032] S12: Deposit N-type polysilicon in the left and right control gate trenches to form control gate electrodes; after the control gate electrodes are deposited, use a thermal oxidation process to grow a field oxide layer on the surface of the bulk region and the top of the trench, the field oxide layer is used for device surface isolation and electric field mitigation;

[0033] S13: An insulating dielectric layer is deposited on the field oxide layer using PECVD, and the deposition material is SiN;

[0034] S14: Dry etching is used to create contact holes in the region corresponding to the N+ source regions on both sides of the insulating dielectric layer and the trench, and a metal layer is deposited inside the contact holes and on the insulating dielectric layer.

[0035] S15: Deposit SiN as a passivation layer on the metal layer.

[0036] Compared with existing technologies, the advantages of this invention are as follows: The doping gradient is directly formed during the epitaxial growth stage, and exponential and Gaussian nonlinear doping distributions are achieved through mass flow control. This avoids the impact of high-temperature diffusion on the reshaping of the gradient curve, ensuring the electric field peak is stably locked on the substrate side, achieving decoupling and synergistic optimization of BV and Rds(on). Simultaneously, in-situ composite doping with carbon (C) and germanium (Ge) is used. C is used to stabilize the temperature fluctuation sensitivity of the phosphorus / boron diffusion coefficient, ensuring the gradient shape remains stable after annealing, significantly improving resistance temperature drift control and manufacturing consistency. Ge introduces compressive stress with a controllable atomic ratio, which improves electron mobility and reduces carrier scattering at high temperatures, thus significantly compressing the degradation rate of Rds(on) at high temperatures. In addition, the present invention introduces a 60nm intrinsic Si buffer layer on the sidewall of the main trench, and works in synergy with the vertical stacking of the gate oxide layer, shielding gate / isolation oxygen / control gate to achieve a continuous and seamless spatial electric field splicing between the trench depletion region and the drift depletion region, eliminating local electric field overshoot and dead zone, further improving the breakdown voltage without increasing the device resistance, and reducing the risk of forward voltage drop and reverse leakage current of the body diode. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention.

[0038] Figure 1 This is a schematic diagram of a novel split-gate MOS transistor structure containing a graded-doped epitaxial layer.

[0039] Figure 2 This is the first flowchart of a method for fabricating a novel split-gate MOS transistor containing a graded-doped epitaxial layer.

[0040] Figure 3This is the second flowchart of a method for fabricating a novel split-gate MOS transistor with a graded-doped epitaxial layer.

[0041] Figure 4 This is the third flowchart of the fabrication method for a novel split-gate MOS transistor containing a graded-doped epitaxial layer. Detailed Implementation

[0042] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0043] Unless otherwise specified, all methods used in this invention are conventional methods known to those skilled in the art, and all reagents and materials used are commercially available products.

[0044] Example 1:

[0045] like Figure 1 As shown in the embodiment of the present invention, a novel split-gate MOS transistor containing a graded-doped epitaxial layer is provided, the MOS transistor comprising:

[0046] Substrate;

[0047] A first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are sequentially disposed on one side of a substrate; the substrate is an N+ type substrate with a thickness of 300 μm; the main material is single-crystal silicon, and the doping element is P with a doping concentration of 1 × 10⁻⁶. 20 cm -3 The first, second, and third epitaxial layers are all N-type silicon, doped with P; their thicknesses are 5 μm, 2 μm, and 3 μm, respectively; and their concentrations are 5 × 10⁻⁶. 14 cm -3 2×10 16 cm -3 and 8×10 14 cm -3 ;

[0048] A P-type body region is disposed on the side of the third epitaxial layer away from the substrate; the P-type body region has a main trench etched towards the substrate; the doping element of the P-type body region is B, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 The depth is 2μm;

[0049] A first gradient layer is disposed between the first epitaxial layer and the second epitaxial layer, and a second gradient layer is disposed between the second epitaxial layer and the third epitaxial layer; the doping concentration of the first gradient layer is an exponential gradient concentration, and the doping concentration of the second gradient layer is a Gaussian gradient concentration; the doping concentration range of the first gradient layer is 5 × 10⁻⁶. 14 cm -3 Up to 2×10 16 cm -3 The doping concentration range of the second gradient layer is 8 × 10⁻⁶. 14 cm -3 Up to 2×10 16 cm -3 The thickness of both the first and second gradient layers is 60 nm; the doping elements of the second epitaxial layer include C and Ge; the doping concentration of C is 1 × 10⁻⁶. 15 cm -3 The atomic percentage of Ge is 4%.

[0050] A split gate trench extends towards the substrate based on the third epitaxial layer in the main trench; the split gate trench penetrates 0.5 μm into the first epitaxial layer; the split gate trench has a depth of 10 μm, a width of 0.6 μm, a bottom fillet radius of 0.3 μm, and a sidewall structure of 12 nm SiO2 and 60 nm intrinsic Si buffer layer; internally, a 3 μm shielding gate, a 25 nm oxygen isolation gate, and a 2 μm control gate are stacked sequentially.

[0051] The trench is flanked by N+ source regions and P+ contact regions at the top of both sides; the depth of the N+ source regions is 0.5 μm, the doping element is P, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 The depth of the P+ contact region is 0.3 μm, the doping element is B, and the doping concentration is 1 × 10⁻⁶. 19 cm -3；

[0052] A deposited metal layer is disposed on the surface of the device. The metal layer adopts an AlCu and TiN stacked structure, and the metal layer achieves ohmic contact with the N+ source region and the P+ contact region.

[0053] A passivation layer is disposed on the metal layer, the material of the passivation layer being SiN, and a back drain metal is disposed on the side of the substrate away from the first epitaxial layer, the back drain metal being an Au and Ti stacked structure.

[0054] Please see Figures 2 to 4 The method used in the fabrication of MOSFETs is as follows:

[0055] S1: A single-crystal silicon substrate with an N+ (100) crystal orientation was selected as the starting material. The substrate thickness was approximately 300 micrometers, and the phosphorus doping concentration was approximately 1 × 10⁻⁶.20 cm -3 The substrate is placed in the vacuum loading chamber and purged with nitrogen for 30 seconds to complete the initial cleaning of surface particles.

[0056] S2: The first epitaxial layer is grown on the substrate using a reduced pressure chemical vapor deposition process; the epitaxial growth temperature is set to 1000 degrees Celsius, the chamber pressure is 80 Torr, the silicon precursor gas is SiH4 with a flow rate of 50 sccm, and the phosphine flow rate is 4 sccm.

[0057] S3: The first gradient layer is grown in situ on the upper surface of the first epitaxial layer; the silicon precursor gas is SiH4 with a flow rate of 50 sccm; the mass flow meter is controlled to reduce the phosphine from 20 sccm to 4 sccm in 5 sccm / steps, with each step lasting 30 seconds.

[0058] S4: A second epitaxial layer is grown on the first graded layer using a reduced-pressure CVD process. The epitaxial growth temperature is set to 1000 degrees Celsius, the chamber pressure to 80 Torr, the silicon precursor gas to be SiH4 at a flow rate of 50 sccm, and the phosphine flow rate to 20 sccm. During growth, stress-modified doping gases are simultaneously introduced, including propane and germanium tetrachloride. The propane flow rate is 2 sccm, the germanium tetrachloride flow rate is 3 sccm, and the carbon doping concentration is controlled at 1 × 10⁻⁶. 15 cm -3 The following has a germanium atomic ratio of 4%;

[0059] S5: The second gradient layer is grown in situ on the upper surface of the second epitaxial layer; the silicon precursor gas is SiH4 with a flow rate of 50 sccm. The mass flow meter is controlled to reduce the phosphine from 20 sccm to 3 sccm in 5 sccm increments, with each step lasting 30 seconds.

[0060] S6: The third epitaxial layer is grown on the second gradient layer using PECVD process; the epitaxial growth temperature is set to 850 degrees Celsius, the chamber pressure is 60 Torr, the silicon precursor gas is SiH4 with a flow rate of 30 sccm, and the doping source gas is arsine with a flow rate of 1.5 sccm.

[0061] S7: A P-type bulk region was formed on the surface of the third epitaxial layer by boron ion implantation at an energy of 60 keV and a dose of 3 × 10⁻⁶ keV. 13 ions / cm 2 After injection, rapid thermal annealing (RTA) is used for activation annealing at a temperature of 850 degrees Celsius for 45 seconds, with a heating rate of 120 degrees Celsius / second and a cooling rate of 180 degrees Celsius / second. The total thermal budget does not exceed 60 seconds.

[0062] S8: A deep trench structure is formed on the P-type body region towards the substrate using an ICP-RIE dry etching process. The trench width is 0.6 micrometers, the depth is 10 micrometers, and the bottom extends 0.5 micrometers into the first epitaxial layer. The etching gas system is SF6 and O2, with flow rates of 40 sccm and 6 sccm, respectively. The chamber pressure is 5 mTorr, the ICP power is 600 W, the RF bias power is 80 W, and the etching rate is 0.8 micrometers / minute. At the end of the etching process, the bottom corner of the trench is naturally rounded by treating it with pure O2 gas at 30 W for 10 seconds.

[0063] S9: After the trench etching is completed, an intrinsic silicon buffer layer is deposited on the sidewall of the trench using LPCVD process. The deposition temperature is 550 degrees Celsius, the chamber pressure is 200 mTorr, the silicon source gas is SiH4 with a flow rate of 6 sccm, the deposition rate is controlled at 6 nanometers / minute, and the target thickness of the buffer layer is 60 nanometers.

[0064] S10: A gate oxide layer is grown on the inner wall of the trench and the surface of the body region using a low-temperature dry oxygen thermal oxidation process. The oxidation temperature is 500 degrees Celsius, the oxidation time is 10 seconds, and the target oxide layer thickness is 12 nanometers. After oxidation, forming gas (N2:H2=95:5) is introduced, and the interface dangling bond is repaired by annealing at 450 degrees Celsius for 1 hour.

[0065] S11: P-type polysilicon is deposited on the gate oxide layer at the bottom of the trench to form a shielded gate-source electrode. The deposition temperature is 620 degrees Celsius, the thickness is 3 micrometers, and the boron doping concentration is 5 × 10⁻⁶. 19 cm -3 Subsequently, the shielding gate was etched back so that its top was 25 nm below the surface of the body region, and a 25 nm oxide layer was deposited on top of it using PECVD as a protective isolation layer. The oxide layer above the body region was then etched, and the left and right control gate trenches were formed using dry etching, with the bottom of the trenches flush with the lower surface of the body region.

[0066] S12: N-type polysilicon is deposited in the left and right control gate trenches to form control gate electrodes. The deposition temperature is 620 degrees Celsius, the thickness is 2 micrometers, and the phosphorus doping concentration is 8 × 10⁻⁶. 19 cm -3 After deposition, a field oxide layer is grown on the body region and the top of the trench. The oxidation temperature is 400 degrees Celsius, the oxidation time is 25 minutes, and the oxide layer thickness is 120 nanometers. That is, after the control gate electrode is deposited, a field oxide layer is grown on the surface of the body region and the top of the trench using a thermal oxidation process. The field oxide layer is used for device surface isolation and electric field mitigation.

[0067] S13: An insulating dielectric layer is deposited on the field oxide layer using PECVD. The deposition material is SiN, the deposition temperature is 350 degrees Celsius, and the thickness is 500 nanometers.

[0068] S14: Dry etching is used to create contact holes in the region corresponding to the N+ source regions on both sides of the insulating dielectric layer and the trench. The contact hole diameter is 0.4 micrometers. Then, a front metal layer is deposited inside the contact hole and on the insulating dielectric layer. The metal system consists of 30 nanometers of Ti and 3 micrometers of AlCu. After the metal deposition is completed, ohmic contact alloying is completed by annealing with forming gas at 420 degrees Celsius for 30 minutes.

[0069] S15: Deposit SiN as a passivation layer on the metal layer; the passivation layer has a thickness of 600nm–800nm, and SiN is deposited at 300℃.

[0070] Regarding the working principle of the above scheme:

[0071] This invention achieves synergistic optimization of device breakdown voltage and on-state resistance by constructing a precise and controllable nonlinear doping gradient during the epitaxial growth stage. Traditional drift region doping gradients mostly rely on high-temperature diffusion after ion implantation. However, under multi-step annealing thermal budgets, the impurity diffusion coefficient is highly sensitive to temperature, and the shape of the doping curve is easily reconstructed, leading to drift of the electric field peak position, increased dispersion of breakdown voltage, and high-temperature temperature drift degradation of on-state resistance. In the growth process of the first and second gradient layers, this invention uses a mass flow meter to precisely control the flow rate of the doping source gas in segments, so that the doping concentration forms an exponential distribution and a Gaussian distribution, respectively. This establishes a stable nonlinear concentration gradient in the thickness direction, making the electric field continuous, smooth, and predictable in the longitudinal direction, and locking the maximum electric field peak at the substrate-side drift region interface far from the bottom of the trench, effectively avoiding local electric field concentration and premature breakdown induced by trench curvature.

[0072] During the second epitaxial layer growth stage, the present invention introduces carbon and germanium doping in situ. Carbon is embedded in the silicon lattice in a low-concentration solid solution manner, which reduces the fluctuation of the phosphorus / boron diffusion coefficient with temperature change. This ensures that the doping gradient maintains its original distribution shape after rapid thermal annealing activation, thus ensuring the consistency of the drift region resistance and electric field distribution. Germanium is replaced by silicon lattice at a fractional atomic percentage to form a controllable lattice constant mismatch compressive stress. Under high-temperature operating conditions, this significantly improves electron mobility and reduces carrier scattering probability, resulting in a significant decrease in on-state resistance at both room temperature and high temperature. Furthermore, at high temperature, the mobility gain and the longitudinal doping gradient synergistically offset the resistance increase trend caused by phonon scattering. This achieves multiple gains, including significant compression of drift region resistance temperature drift, a substantial reduction in on-state resistance temperature degradation rate, and a significant improvement in breakdown voltage consistency.

[0073] Furthermore, this invention deposits an intrinsic silicon buffer layer on the sidewall of the main trench and combines it with low-temperature dry oxygen thermal oxidation to form a high-quality gate dielectric, which reduces the trap density at the interface between the trench region and the body region, decreases the carrier capture probability, and further reduces the dispersion of leakage current and threshold voltage. The vertical stacking of the shielding gate, oxygen isolation, and control gate in the trench forms a spatial redistribution structure of dual depletion regions inside and outside the trench. With the participation of the intrinsic Si buffer layer, the trench depletion region and the epitaxial drift region depletion region achieve seamless electric field spatial splicing, eliminate the electric field blind zone, further homogenize the potential gradient of the trench sidewall, suppress the local electric field overshoot at the junction of the trench bottom and the sidewall, reduce the forward voltage drop of the body diode, significantly reduce the reverse leakage current, and improve the reliability of the device under high voltage and high temperature conditions.

[0074] Ultimately, the front metal layer is directly alloyed with the N+ source region and P+ contact region through contact holes to form an ohmic contact with a low contact barrier, and the overlying passivation layer achieves full surface encapsulation protection of the device, avoiding reliability degradation induced by external ions, water vapor and electric field edge defects.

[0075] Example 2:

[0076] Unlike Example 1, a temperature control process is introduced in steps S2, S4, S5, and S6. The temperature control process is as follows:

[0077] The surface temperature of five points on the wafer is collected simultaneously using an infrared thermometer, and the original temperature value of each point is output.

[0078] The temperature of the heating platform base is collected by thermocouples, and a reference temperature value is output.

[0079] The fusion temperature was calculated using a weighted fusion algorithm, with the weight of the original temperature value at each point being 0.7 and the weight of the reference temperature value being 0.3.

[0080] Calculate the deviation between the fusion temperature and the preset target temperature; the preset target temperature is the temperature set in the steps.

[0081] The power adjustment amount is calculated based on the deviation value; wherein the power adjustment amount includes a boundary condition, which is a range of ±5% of the current power.

[0082] The calculated power adjustment is output to the heating system via a PID controller.

[0083] The calculation of the power adjustment amount adopts an incremental PID algorithm, specifically as follows:

[0084] In the formula, For the first Power adjustment amount for the next cycle. For the first The deviation value of the next cycle, correspondingly and Corresponding to the first The deviation value of the next cycle and the first The deviation value for the next cycle; For proportionality coefficient, Here, is the integral coefficient, and is the differential coefficient; all three are preset values, and during the isothermal stage, , , .

[0085] Example 3:

[0086] Unlike Example 1, a chamber pressure control process is introduced in steps S2, S4, S5, and S6. The chamber pressure is acquired by a Baratron vacuum gauge, and the control target is a throttle valve. When the pressure is too high, the throttle valve opening is increased to accelerate exhaust; when the pressure is too low, the throttle valve opening is decreased. The control process uses an incremental PID algorithm, and the target pressure is the pressure set in each step.

[0087] Example 4:

[0088] Unlike Example 2, a chamber pressure control process is introduced in steps S2, S4, S5, and S6. The chamber pressure is acquired by a Baratron vacuum gauge, and the control target is a throttle valve. When the pressure is too high, the throttle valve opening is increased to accelerate exhaust; when the pressure is too low, the throttle valve opening is decreased. The control process uses an incremental PID algorithm, and the target pressure is the pressure set in each step.

[0089] Example 5:

[0090] Unlike Example 4, the atomic percentage of Ge in the second epitaxial layer is 3%.

[0091] Example 6:

[0092] Unlike Example 4, the atomic percentage of Ge in the second epitaxial layer is 5%.

[0093] Comparative Example 1:

[0094] The difference from Example 1 is that no doping elements including C and Ge are introduced into the second epitaxial layer, and correspondingly, stress-modified doping gas is not introduced in step S4 of the preparation method.

[0095] Comparative Example 2:

[0096] The difference from Example 1 is that both the first gradient layer and the second gradient layer have linearly gradient concentrations.

[0097] Comparative Example 3:

[0098] The difference from Comparative Example 1 is that both the first and second gradient layers have linearly gradient concentrations.

[0099] The specific details regarding Examples 1-6 and Comparative Examples 1-3 are as follows:

[0100] Example 1 provides a complete MOS transistor and its fabrication method. Example 2 introduces a temperature control process during epitaxial layer formation. Example 3 introduces a chamber pressure control process during epitaxial layer formation. Example 4 is equivalent to introducing both temperature control and chamber pressure control processes simultaneously. Examples 5 and 6 respectively provide two concentrations of stress-modified doping gases.

[0101] Comparative Example 1 did not introduce stress-modified doping gas in the second epitaxial layer, and the preparation method was updated simultaneously. Comparative Example 2 did not introduce exponential gradient concentration and Gaussian gradient concentration in the first and second gradient layers. Compared with Example 1, Comparative Example 3 did not introduce stress-modified doping gas, nor did it introduce exponential gradient concentration and Gaussian gradient concentration.

[0102] The testing process included measuring on-state resistance, breakdown voltage, threshold voltage, reverse leakage current, and forward voltage drop of the body diode. Conventional testing methods were employed, with each instance corresponding to a set of fifty samples. The final average value was taken as the result. The testing method is as follows:

[0103] 1. On-state resistance Rds(on) test method:

[0104] A power parameter analyzer (such as Keysight B1505A or equivalent) was used to place the device on a temperature-controlled probe station and test it at 25℃ and 150℃. During the test, the gate voltage Vgs was set to 15V to ensure saturation drive, and the drain-source voltage Vds was set to 0.1V. The drain current was gradually increased to the device's rated current (to achieve a current density of approximately 100A / cm²). Vds and Id were recorded under stable conduction conditions, and Rds(on) = Vds / Id was calculated. The result was normalized to the form of mΩ·cm².

[0105] 2. Breakdown voltage BVdss test method:

[0106] Using a high-voltage tester, with Vgs=0V and the source grounded, the drain voltage Vds is gradually increased in steps of 10V until the device enters the avalanche breakdown state (judgment condition: leakage current reaches 1mA). Vds at this time is recorded as BVdss.

[0107] 3. Threshold voltage Vth test method:

[0108] A semiconductor parameter analyzer was used, with Vds=0.1V and the source grounded. The gate voltage Vgs was scanned in steps of 0.05V. When the drain current reached 1μA (or 10A / cm² equivalent microcurrent judgment), Vgs was recorded as Vth, and the standard deviation of 10–20 devices was calculated as a consistency index.

[0109] 4. Reverse leakage current Idss test method:

[0110] At 25℃ and 150℃, a high-voltage tester was used, with Vgs=0V and Vds=0.8×BVdss set, and reverse biased for more than 30s. The stable leakage current was recorded as Idss.

[0111] 5. Test method for forward voltage drop Vf of body diode:

[0112] Using a semiconductor parameter analyzer, if is set to the device's rated current, the gate is grounded, and the source and drain are reverse-connected to make the body diode forward-biased. The stable voltage is recorded as Vf.

[0113] The test results are as follows:

[0114] Device group On-state resistance Rds(on) (mΩ·cm²) 25℃ / 150℃ Breakdown voltage BVdss (V) Threshold voltage Vth(V) Reverse leakage current Idss (μA) 25℃ / 150℃ The forward voltage drop Vf(V) of the body diode Example 1 1.65 / 2.25 790 3.95 0.12 / 0.75 0.78 Example 2 1.58 / 2.18 795 3.90 0.10 / 0.68 0.77 Example 3 1.60 / 2.20 788 3.92 0.11 / 0.70 0.76 Example 4 1.45 / 2.05 805 3.85 0.07 / 0.52 0.74 Example 5 1.50 / 2.12 798 3.88 0.09 / 0.60 0.75 Example 6 1.42 / 2.00 812 3.80 0.06 / 0.48 0.73 Comparative Example 1 2.35 / 3.65 620 4.05 0.40 / 3.2 0.92 Comparative Example 2 2.70 / 4.10 610 4.20 0.65 / 7.8 1.05 Comparative Example 3 2.85 / 4.35 598 4.35 1.10 / 14.0 1.10

[0115] Results analysis:

[0116] Example 1 provides a complete MOS transistor and its fabrication method. Compared to Example 1, Comparative Example 1 does not introduce stress-modified doping gas in the second epitaxial layer, and the fabrication method is updated accordingly. Comparative Example 2 does not introduce exponential gradient concentration and Gaussian gradient concentration in the first and second gradient layers. Compared to Example 1, Comparative Example 3 does not introduce either stress-modified doping gas, exponential gradient concentration, or Gaussian gradient concentration. Therefore, comparing Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 together, it can be seen that Example 1 has significant improvements in all parameters compared to Comparative Example 3 (the prior art). Comparative Examples 1 and 2 are examples that only adopt some improvements of Example 1. Compared to Comparative Example 3, they have slight improvements in various aspects, but the improvement effect is not obvious when only some improvements are adopted. The improvement of Example 1 is extremely obvious, which shows that the improvements in both aspects are actually synergistic.

[0117] For Examples 2 and 3, both involve intelligent control of a single parameter, which makes the conditions of the preparation process more stringent. Consequently, the performance of the resulting product is better, but the improvement is not very significant. This is because the purpose of the two control processes is actually to achieve the predetermined goal more strictly and to establish production conditions that meet the standards. It plays a role in icing on the cake. However, in practical applications, when each parameter is already excellent enough, even a small improvement is a very big step forward. For example, improving from 50% to 80% versus improving from 80% to 85% are both quite significant improvements.

[0118] Furthermore, Example 4 combines two control processes, resulting in a more significant performance improvement. Examples 5 and 6 are based on Example 4, but with changes to the Ge content. Example 5 is almost identical to Example 4, while Example 6 shows a significant improvement over Example 4. Considering cost issues and unknown risks (excessive concentration in a certain group may bring unknown risks in practical applications), Example 4 is considered the optimal example.

[0119] In fact, the doping elements of the second epitaxial layer include C and Ge. The above embodiments compare the Ge element based on the determination of the C doping concentration. In reality, there are still many variables that affect the final effect, including the parameters and conditions during preparation. However, based on the above facts, embodiment 4 is considered to be the optimal embodiment.

[0120] Regarding the above scheme, unlike the existing technology which uses ion implantation diffusion to form a doping gradient, this invention achieves an exponential doping distribution in the first graded layer and a Gaussian doping distribution in the second graded layer through mass flow rate control during the epitaxial growth process. This enables the doping concentration in the drift region to form a precise and controllable nonlinear gradient in the thickness direction, overcoming the problems of BV dispersion and Rds(on) temperature drift degradation caused by uncontrolled impurity diffusion under high-temperature processes.

[0121] Furthermore, this invention introduces carbon (C) and germanium (Ge) composite doping in situ during the second epitaxial layer growth stage. C doping is used to suppress the temperature sensitivity changes of the phosphorus / boron diffusion coefficient to stabilize the gradient, while Ge forms compressive stress at an atomic ratio of 3%–5% to improve electron mobility at high temperatures. The two work together to achieve a drift region resistance temperature drift of <3%, a BV uniformity improvement of >20%, and a Rds(on) degradation rate reduction of >70%. This triple gain has not been reported in the prior art and is unpredictable.

[0122] In addition, the present invention introduces an intrinsic Si buffer layer between the main trench sidewall and the shielding gate, forming a redistribution depletion region in the split gate structure, so that the trench gate depletion region and the epitaxial drift region depletion region achieve a spatially seamless electric field splicing, eliminating the electric field blind zone and the local electric field concentration induced by the trench curvature, thereby improving the BV to a higher level while maintaining a low Rds(on).

[0123] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A novel split-gate MOS transistor containing a graded-doped epitaxial layer, characterized in that, The MOSFET includes: Substrate; A first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are sequentially disposed on one side of the substrate; A P-type body region is disposed on the side of the third epitaxial layer away from the substrate; the P-type body region is provided with a main trench etched toward the substrate. A first gradient layer is disposed between a first epitaxial layer and a second epitaxial layer, and a second gradient layer is disposed between a second epitaxial layer and a third epitaxial layer; the doping concentration of the first gradient layer is an exponential gradient concentration, and the doping concentration of the second gradient layer is a Gaussian gradient concentration; wherein, the doping elements of the second epitaxial layer include C and Ge; A split gate trench extending toward the substrate based on the third epitaxial layer in the main trench; N+ source regions and P+ contact regions are set at the top of both sides of the trench; A deposited metal layer is disposed on the surface of the device. The metal layer adopts an AlCu and TiN stacked structure, and the metal layer achieves ohmic contact with the N+ source region and the P+ contact region. A passivation layer is disposed on the metal layer, the material of the passivation layer being SiN, and a back drain metal is disposed on the side of the substrate away from the first epitaxial layer, the back drain metal being an Au and Ti stacked structure.

2. The novel split-gate MOS transistor with a graded-doped epitaxial layer according to claim 1, characterized in that, The substrate is an N+ type substrate with a thickness of 300 μm; the main material is monocrystalline silicon, and the doping element is P with a doping concentration of 1 × 10⁻⁶. 20 cm -3 The first, second, and third epitaxial layers are all N-type silicon, doped with P; their thicknesses are 5 μm, 2 μm, and 3 μm, respectively; and their concentrations are 5 × 10⁻⁶. 14 cm -3 2×10 16 cm -3 and 8×10 14 cm -3 .

3. The novel split-gate MOS transistor with a graded-doped epitaxial layer according to claim 1, characterized in that, The doping element in the P-type body region is B, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 The depth is 2μm.

4. The novel split-gate MOS transistor with a graded-doped epitaxial layer according to claim 1, characterized in that, The split gate trench extends 0.5 μm into the first epitaxial layer; the split gate trench has a depth of 10 μm, a width of 0.6 μm, a bottom fillet radius of 0.3 μm, and a sidewall structure of 12 nm SiO2 and 60 nm intrinsic Si buffer layer; internally, a 3 μm shielding gate, a 25 nm oxygen isolation gate, and a 2 μm control gate are stacked sequentially.

5. The novel split-gate MOS transistor with a graded-doped epitaxial layer according to claim 1, characterized in that, The depth of the N+ source region is 0.5 μm, the dopant element is P, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 The depth of the P+ contact region is 0.3 μm, the doping element is B, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 .

6. A method for fabricating a novel split-gate MOS transistor containing a graded-doped epitaxial layer as described in any one of claims 1 to 5, characterized in that, The preparation method includes: S1: Select an N+ type single crystal silicon substrate as the starting material, place the substrate into a vacuum loading chamber, and purge with nitrogen for 30 seconds to complete the initial cleaning of surface particles; S2: The first epitaxial layer is grown on the substrate using a reduced-pressure chemical vapor deposition process; S3: The first gradient layer is grown in situ on the upper surface of the first epitaxial layer; S4: Continue to grow the second epitaxial layer on the first gradient layer using a reduced pressure CVD process; S5: Grow a second gradient layer in situ on the upper surface of the second epitaxial layer; S6: The third epitaxial layer is grown on the second gradient layer using PECVD process; S7: A P-type body region is formed on the surface of the third epitaxial layer by boron ion implantation, followed by rapid thermal annealing (RTA) activation annealing. S8: Trenches are formed on the P-type body region towards the substrate using ICP-RIE dry etching process; S9: After the trench etching is completed, an intrinsic silicon buffer layer is deposited on the trench sidewall using LPCVD process; S10: A gate oxide layer is grown on the inner wall of the trench and the surface of the body region using a low-temperature dry oxygen thermal oxidation process; S11: P-type polysilicon is deposited on the gate oxide layer at the bottom of the trench to form a shielded gate source electrode. The shielded gate electrode is etched back and an oxide layer is deposited on top of it using PECVD process as a protective isolation layer. The left control gate trench and the right control gate trench are formed by dry etching. The bottom of the trench is flush with the lower surface of the body region. S12: Deposit N-type polysilicon in the left and right control gate trenches to form control gate electrodes; after the control gate electrodes are deposited, use a thermal oxidation process to grow a field oxide layer on the surface of the bulk region and the top of the trench, the field oxide layer is used for device surface isolation and electric field mitigation; S13: An insulating dielectric layer is deposited on the field oxide layer using PECVD, and the deposition material is SiN; S14: Dry etching is used to create contact holes in the region corresponding to the N+ source regions on both sides of the insulating dielectric layer and the trench, and a metal layer is deposited inside the contact holes and on the insulating dielectric layer. S15: Deposit SiN as a passivation layer on the metal layer.

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