Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, a first high-voltage well region, a first doped region, a second doped region, a third doped region, a first conductive layer and a floating conductive layer, the substrate has a first conductivity type. The epitaxial layer is disposed on the substrate and has a second conductive type. The first high-voltage well region is disposed in the epitaxial layer and has a second conductivity type. The first doped region and the second doped region are arranged in the first high-voltage well region and have the first conduction type. The third doped region is arranged in the first high-voltage well region and has the second conductive type. The first conductive layer is electrically connected with the first high-voltage well region and the first doped region. The floating conductive layer is electrically connected with the second doped region and the third doped region, and is electrically isolated from the first conductive layer. According to the semiconductor device provided by the invention, the electrical property and the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices including floating conductive layers. Background Technology

[0002] Current high-voltage integrated circuits (HVICs) may include a high-side circuit in the high-side region, a low-side circuit in the low-side region, and an isolation structure disposed between them. Bootstrap diodes in bootstrap circuits are often integrated with HVICs to provide power to transistors in the high-voltage region.

[0003] However, integrating bootstrap diodes and HVICs can lead to problems due to complex fabrication processes and structures, such as insufficient switching speed, excessively long recovery time, excessive forward voltage, insufficient forward current, and excess carrier accumulation, resulting in insufficient reliability of the semiconductor device. Therefore, although existing semiconductor devices have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Thus, some issues regarding semiconductor devices still need to be overcome. Summary of the Invention

[0004] This application avoids the accumulation of excess charge carriers, whether electrons or holes, in the semiconductor device by setting a floating conductive layer electrically connected to floating doped regions of different conductivity types (e.g., a second doped region and a third doped region). Furthermore, this application achieves the characteristics of both a Schottky diode (SBD) and a PIN diode by setting a current path analogous to a merged PIN Schottky (MPS) structure. This improves the electrical properties and reliability of the semiconductor device.

[0005] In some embodiments, this application provides a semiconductor device. The semiconductor device includes a substrate, an epitaxial layer, a first high-voltage well region, a first doped region, a second doped region, a third doped region, a first conductive layer, and a floating conductive layer. The substrate has a first conductivity type. The epitaxial layer is disposed on the substrate and has a second conductivity type different from the first conductivity type. The first high-voltage well region is disposed in the epitaxial layer and has the second conductivity type. The first doped region is disposed in the first high-voltage well region and has the first conductivity type. The second doped region is disposed in the first high-voltage well region and has the first conductivity type. The third doped region is disposed in the first high-voltage well region and has the second conductivity type. The first conductive layer is electrically connected to the first high-voltage well region and the first doped region. The floating conductive layer is electrically connected to the second doped region and the third doped region, and is electrically isolated from the first conductive layer.

[0006] The semiconductor device of this application can be applied to various types of electronic devices and methods of forming thereof. To make the components and advantages of this application more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0007] This application can be more fully understood from the following detailed description when read in conjunction with the drawings. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0008] Figures 1 to 3 This is a cross-sectional schematic diagram of each stage of a method for forming a semiconductor device according to an embodiment of this application.

[0009] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of this application.

[0010] Figure 5 and Figure 6 This is a top view schematic diagram of a semiconductor device according to an embodiment of this application.

[0011] Figures 7 to 9 These are top views of a semiconductor device according to an embodiment of this application.

[0012] Explanation of reference numerals in the attached figures:

[0013] 1,2,3,4: Semiconductor devices

[0014] 100:Substrate

[0015] 102: First Embedded Layer

[0016] 104: Second Embedded Layer

[0017] 106: Epitaxial layer

[0018] 112: First High-Pressure Well Area

[0019] 114: Second High-Pressure Well Area

[0020] 200: Isolation layer

[0021] 210: Gate dielectric layer

[0022] 220: Gate electrode

[0023] 310: First doped region

[0024] 312: Opening

[0025] 320: Second doped region

[0026] 330: Third doped region

[0027] 340: Fourth doped region

[0028] 350: Fifth doped region

[0029] 400: Interlayer dielectric layer

[0030] 410: First contact object

[0031] 412: Floating conductive layer contact material

[0032] 420: Second contact object

[0033] 430: Third contact object

[0034] 500: Floating conductive layer

[0035] 510: First conductive layer

[0036] 520: Second conductive layer

[0037] 530: Third conductive layer

[0038] AA: Active Zone

[0039] D1: First Direction

[0040] D2: Second Direction

[0041] D3: Third direction

[0042] I-I',II-II': line segment

[0043] P1: First current path

[0044] P2: Second current path Detailed Implementation

[0045] The semiconductor devices of various embodiments in this application are described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this application. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this application. Of course, these are only examples and not limitations on this application. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this application. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this application and does not represent any relationship between the different embodiments and / or structures discussed.

[0046] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped so that it is upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments of this application should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0047] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, this may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0048] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that element (or those elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.

[0049] In some embodiments of this application, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with another structure disposed between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0050] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "the range is between the first value and the second value" or "the first value to the second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first and second values ​​within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0051] Throughout this application, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Thus, when the terms "comprise" and / or "having" are used in the description of this application, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more corresponding components, areas, steps, operations, and / or elements.

[0052] It should be understood that, without departing from the spirit of this application, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this application, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this application.

[0054] In this application, the directions are not limited to the three axes of a Cartesian coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (height direction). In some embodiments, the top view described herein is a schematic diagram of viewing the XY plane, and the cross-sectional view described herein is a schematic diagram of viewing the XZ plane. The normal direction of the substrate described herein is the third direction D3.

[0055] Reference Figure 1 This is a cross-sectional schematic diagram of the various stages of a method for forming a semiconductor device 1 according to an embodiment of this application. In some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. Generally, a semiconductor-on-insulator substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate.

[0056] In some embodiments, substrate 100 may include elemental semiconductors, including silicon, germanium, the like, or combinations thereof; substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or combinations thereof; substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof, but this application is not limited thereto.

[0057] In some embodiments, the first conductivity type and the second conductivity type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, doping depth, and size of the doped region can also be adjusted according to electrical requirements. In some embodiments, the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For ease of explanation, in the following text, the first conductivity type can be P-type and the second conductivity type can be N-type, but this application is not limited thereto.

[0058] like Figure 1 As shown, in some embodiments, a first buried layer 102 and a second buried layer 104 may be formed in the substrate 100. The first buried layer 102 may have a second conductivity type different from the first conductivity type, i.e., N-type. The second buried layer 104 may have the first conductivity type, i.e., P-type. In some embodiments, the first buried layer 102 and the second buried layer 104 may be formed by processes such as ion implantation, diffusion, drive-in, similar processes, or combinations thereof, but this application is not limited thereto. Furthermore, the implanted dopant may be further activated by a rapid thermal annealing (RTA) process. In some embodiments, depending on the required conductivity type, the dopant may be an N-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb), or a P-type dopant such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0059] like Figure 1As shown, in some embodiments, an epitaxial layer 106 may be formed on the substrate 100, and the epitaxial layer 106 may have a second conductivity type different from the first conductivity type, i.e., N-type. In some embodiments, the epitaxial layer 106 may be formed on the first buried layer 102 and the second buried layer 104. In some embodiments, after the epitaxial layer 106 is formed, the doping profile on the first buried layer 102 and the second buried layer 104 may be changed by performing the aforementioned diffusion process, thermal ingress process and / or rapid thermal annealing process.

[0060] like Figure 1 As shown, in some embodiments, a first high voltage well 112 may be formed in the epitaxial layer 106, and the first high voltage well 112 may have a second conductivity type, i.e., N-type. In some embodiments, a first buried layer 102 may be disposed between the substrate 100 and the first high voltage well 112. In some embodiments, in the first direction D1, the width of the first high voltage well 112 may be smaller than the width of the first buried layer 102. In some embodiments, the projection of the first high voltage well 112 onto the substrate 100 lies within the projection of the first buried layer 102 onto the substrate 100. In some embodiments, the first high voltage well 112 may penetrate the epitaxial layer 106. In some embodiments, the first high voltage well 112 may be formed by performing the aforementioned ion implantation, diffusion process, thermal induction process, and / or rapid thermal annealing process. In some embodiments, the doping concentration of the first high voltage well 112 may be smaller than the doping concentration of the first buried layer 102. In some embodiments, the doping concentration of the first high voltage well 112 may be greater than the doping concentration of the epitaxial layer 106.

[0061] like Figure 1 As shown, in some embodiments, a second high-voltage well region 114 may be formed in the epitaxial layer 106, and the second high-voltage well region 114 may have a first conductivity type, i.e., P-type. In some embodiments, the second buried layer 104 may be disposed between the substrate 100 and the second high-voltage well region 114. In some embodiments, in the first direction D1, the width of the second high-voltage well region 114 may be substantially the same as the width of the second buried layer 104. In some embodiments, the projection of the second high-voltage well region 114 onto the substrate 100 is aligned with the projection of the second buried layer 104 onto the substrate 100. In some embodiments, the second high-voltage well region 114 may penetrate the epitaxial layer 106. In some embodiments, the second high-voltage well region 114 may be formed by performing the aforementioned ion implantation, diffusion process, thermal ingress process, and / or rapid thermal annealing process. In some embodiments, the doping concentration of the second high-voltage well region 114 may be less than the doping concentration of the second buried layer 104.

[0062] like Figure 1As shown, in some embodiments, an active region AA of a semiconductor device is defined on the substrate 100, and an isolation layer 200 is formed according to the location of the active region AA. In some embodiments, the isolation layer 200 may be formed on the epitaxial layer 106. In some embodiments, the isolation layer 200 may be disposed between the epitaxial layer 106 and a subsequently formed interlayer dielectric layer. In some embodiments, the isolation layer 200 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxides oxynitride such as silicon oxynitride, the like, or combinations thereof, but this application is not limited thereto. For example, the isolation layer 200 may include field oxides. In some embodiments, the isolation layer 200 may be formed by local oxidation of silicon (LOCOS) formed by thermal oxidation.

[0063] like Figure 1 As shown, in some embodiments, a gate dielectric layer 210 is formed on the isolation layer 200, the epitaxial layer 106, and the first high-voltage well region 112, and a gate electrode 220 is formed on the gate dielectric layer 210. In some embodiments, the gate dielectric layer 210 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxide oxynitrides such as silicon oxynitride, the like, or combinations thereof, but this application is not limited thereto. In some embodiments, the gate dielectric layer 210 may include a high dielectric constant dielectric material. For example, the gate dielectric layer 210 may include silicon oxide. In some embodiments, the gate electrode 220 may include amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, the like, or combinations thereof, but this application is not limited thereto. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or combinations thereof, but this application is not limited thereto. For example, the gate electrode 220 may include polysilicon. In some embodiments, the gate electrode 220 may be formed by sputtering, chemical vapor deposition (CVD), resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof, but this application is not limited thereto.

[0064] Reference Figure 2This is a cross-sectional schematic diagram of the various stages of a method for forming a semiconductor device 1 according to an embodiment of this application. In some embodiments, a first doped region 310, a second doped region 320, and a third doped region 330 are formed in a first high-voltage well region 112. The first doped region 310 and the second doped region 320 may have a first conductivity type, i.e., P-type, and the third doped region 330 may have a second conductivity type, i.e., N-type. In some embodiments, a fourth doped region 340 is formed in an epitaxial layer 106, and the fourth doped region 340 may have a second conductivity type, i.e., N-type. In some embodiments, a fifth doped region 350 is formed in a second high-voltage well region 114, and the fifth doped region 350 may have a first conductivity type, i.e., P-type. In some embodiments, the first doped region 310 to the fifth doped region 350 can be formed by performing the aforementioned ion implantation, diffusion process, thermal ingress process, and / or rapid thermal annealing process. In some embodiments, the first doped region 310, the second doped region 320, and the fifth doped region 350 can be formed in the same or different process layers. In some embodiments, the third doped region 330 and the fourth doped region 340 may be formed in the same or different processes. Accordingly, this application can adjust the shape and size of the first doped region 310 by adjusting the mask pattern, thereby easily adjusting the ratio of the Schottky diode to the PIN diode. Furthermore, this application can adjust the shape and size of the second doped region 320 and the third doped region 330 by adjusting the mask pattern, thereby easily forming floating doped regions for capturing excess carriers.

[0065] like Figure 2 As shown, in some embodiments, in the cross-sectional view, a pair of first doped regions 310 may be provided. However, the pair of first doped regions 310 are substantially continuous. In some embodiments, a portion of the first high-voltage well region 112 may be interposed in the pair of first doped regions 310. In some embodiments, a portion of the first high-voltage well region 112 may be interposed between the first doped region 310 and the second doped region 320. In some embodiments, a portion of the first high-voltage well region 112 may be interposed between the third doped region 330 and the epitaxial layer 106.

[0066] like Figure 2As shown, in some embodiments, the first doped region 310 and the second doped region 320 are spaced apart by a distance. In some embodiments, the second doped region 320 and the third doped region 330 are in direct contact. In some embodiments, the second doped region 320 and the third doped region 330 may be disposed between the first doped region 310 and the fourth doped region 340. In other words, doped regions with different conductivity types that are in direct contact with each other may be disposed between the first doped region 310 and the fourth doped region 340 so that excess carriers of different conductivity types can be discharged. In detail, since the subsequently formed floating electrode (e.g., floating electrode 500) is electrically connected to two floating doped regions with different conductivity types simultaneously, excess carriers of different conductivity types can be discharged by the corresponding floating doped region. For example, excess electrons can be discharged by the second doped region 320, and excess holes can be discharged by the third doped region 330. In some embodiments, the area of ​​the second doped region 320 may be A1, the area of ​​the third doped region 330 may be A2, and the ratio of the area of ​​the second doped region 320 to the area of ​​the third doped region 330 may be A1 / A2. In some embodiments, A1 / A2 may be 0.1 to 10, but this application is not limited thereto. For example, A1 / A2 may be 0.1, 0.125, 0.2, 0.25, 0.5, 0.75, 1, 1.33, 2, 4, 5, 8, 10, or any value or a range of values ​​between the foregoing values, but this application is not limited thereto. Figure 2 As shown, in some embodiments, A1 / A2 may be approximately 1.

[0067] like Figure 2 As shown, in some embodiments, the second doped region 320 may be disposed between the first doped region 310 and the third doped region 330. In other embodiments, the positions or conductivity types of the second doped region 320 and the third doped region 330 may be interchanged. For example (not shown), when the second doped region 320 is disposed between the first doped region 310 and the third doped region 330, the second doped region 320 may be N-type and the third doped region 330 may be P-type. Accordingly, the subsequently formed floating electrode can also be electrically connected to doped regions with different conductivity types, so that excess carriers of different conductivity types can be discharged.

[0068] like Figure 2As shown, in some embodiments, the third doped region 330 may be disposed between the second doped region 320 and the fourth doped region 340. In some embodiments, the fourth doped region 340 is spaced apart from the first high-voltage well region 112 by a distance. In some embodiments, the fourth doped region 340 and the fifth doped region 350 are respectively disposed on both sides of the gate electrode 220. In some embodiments, the first doped region 310 may be disposed between the second doped region 320 and the fifth doped region 350. In some embodiments, in the normal direction (third direction D3) of the substrate 100, the third doped region 330 may or may not overlap with the gate electrode 220.

[0069] like Figure 2 As shown, in some embodiments, in the first direction D1, both the second doped region 320 and the third doped region 330 are closer to the first doped region 310 than the fourth doped region 340. Specifically, the first doped region 310 can be analogous to the source doped region, and the fourth doped region 340 can be analogous to the drain doped region. When the second doped region 320 and the third doped region 330, used to capture excess carriers, are closer to the first doped region 310 which is closer to the voltage source, it is more effective at capturing excess carriers. In some embodiments, the second doped region 320 and the third doped region 330 may be disposed between the first doped region 310 and the gate electrode 220. In other embodiments (not shown), the second doped region 320 and the third doped region 330 may be disposed between the first doped region 310 and the fifth doped region 350. Compared to the first doping region 310 and the fifth doping region 350, the second doping region 320 and the third doping region 330 are positioned between the first doping region 310 and the fourth doping region 340, which is more conducive to capturing excess carriers.

[0070] Reference Figure 3 This is a cross-sectional schematic diagram of each stage of a method for forming a semiconductor device 1 according to an embodiment of this application. Figure 3 Showing along the subsequent Figure 5 The diagram shows a cross-sectional view captured by line segment I-I'. In some embodiments, an interlayer dielectric layer 400 may be formed on the gate electrode 220 in a blanket manner. In some embodiments, the interlayer dielectric layer 400 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, or combinations thereof, but this application is not limited thereto.

[0071] like Figure 3As shown, in some embodiments, vias (not shown) may be formed in the interlayer dielectric layer 400 to expose the top surfaces of the first doped regions 310 to the fifth doped regions 350. In some embodiments, a first contact 410 may be formed in the via to be disposed on the first high-voltage well region 112 and the first doped region 310. In some embodiments, the first contact 410 may be in direct contact with the first high-voltage well region 112 and the first doped region 310. In some embodiments, the first contact 410 may cover a portion of the top surface of the first doped region 310 and expose a portion of the top surface of the first doped region 310. In some embodiments, on the third direction D3, the projection of the first contact 410 onto the substrate 100 may overlap with the projection of the first doped region 310 onto the substrate 100.

[0072] like Figure 3 As shown, in some embodiments, a floating conductive layer contact 412 may be formed in the via, such that the floating conductive layer contact 412 is disposed on both the second doped region 320 and the third doped region 330. In some embodiments, the floating conductive layer contact 412 may be in direct contact with both the second doped region 320 and the third doped region 330. In some embodiments, a second contact 420 may be formed in the via, such that the second contact 420 is disposed on the fourth doped region 340. In some embodiments, the second contact 420 may be in direct contact with the fourth doped region 340. In some embodiments, a third contact 430 may be formed in the via, such that the third contact 430 is disposed on the fifth doped region 350. In some embodiments, the third contact 430 may be in direct contact with the fifth doped region 350. In some embodiments, the first contact 410, the floating conductive layer contact 412, the second contact 420 and the third contact 430 may penetrate the interlayer dielectric layer 400 respectively, and may include metal, metal nitride, conductive metal oxide, the like or a combination thereof, but this application is not limited thereto.

[0073] like Figure 3 As shown, in some embodiments, a first conductive layer 510 may be formed on the interlayer dielectric layer 400, and the first conductive layer 510 is electrically connected to the first high-voltage well region 112 and the first doped region 310 through a first contact 410. In some embodiments, since the opening 312 may be disposed in the first doped region 310, the first contact 410 may directly contact the first high-voltage well region 112 and the first doped region 310 through the opening 312 of the first doped region 310. In some embodiments, on the third direction D3, the projection of the opening 312 surrounded by the first doped region 310 onto the substrate 100 may be located within the projection of the first contact 410 onto the substrate 100.

[0074] like Figure 3As shown, in some embodiments, a floating conductive layer 500 may be formed on the interlayer dielectric layer 400, and the floating conductive layer 500 is electrically connected to the second doped region 320 and the third doped region 330 through a floating conductive layer contact 412. In some embodiments, a second conductive layer 520 may be formed on the interlayer dielectric layer 400, and the second conductive layer 520 is electrically connected to the fourth doped region 340 through a second contact 420. In some embodiments, a third conductive layer 530 may be formed on the interlayer dielectric layer 400, and the third conductive layer 530 is electrically connected to the fifth doped region 350 through a third contact 430. Therefore, a semiconductor device 1 can be obtained. Figure 3 As shown, in some embodiments, the floating conductive layer 500 may be electrically isolated from the first conductive layer 510, the second conductive layer 520, and the third conductive layer 530, respectively. In some embodiments, the floating conductive layer 500 may be disposed between the first conductive layer 510 and the second conductive layer 520. In some embodiments, the floating conductive layer 500 may be closer to the first conductive layer 510 than the second conductive layer 520.

[0075] like Figure 3 As shown, in some embodiments, the active region AA, in which the first doped region 310 and the first conductive layer 510 are disposed, can be the anode region of the semiconductor device, and therefore the first conductive layer 510 can serve as the anode electrode of the semiconductor device 1. In some embodiments, the active region AA, in which the fourth doped region 340 and the second conductive layer 520 are disposed, can be the cathode region of the semiconductor device, and therefore the second conductive layer 520 can serve as the cathode electrode of the semiconductor device 1. In some embodiments, within the anode region, the area corresponding to the second doped region 320, the third doped region 330, and the floating conductive layer 500 can be a floating region, and therefore the floating conductive layer 500 can serve as a floating field plate of the semiconductor device 1.

[0076] like Figure 3 As shown, in some embodiments, in the first current path P1, when a voltage is applied to the first conductive layer 510, the current flows sequentially along the first contact 410, the first doped region 310, the first high-voltage well region 112, the epitaxial layer 106, the fourth doped region 340, and the second contact 420 to the second conductive layer 520. Since the first doped region 310 is analogous to a P-type semiconductor in a PIN diode, the first high-voltage well region 112 and the epitaxial layer 106 are analogous to an intrinsic (I-type) semiconductor in a PIN diode, and the fourth doped region 340 is analogous to an N-type semiconductor in a PIN diode, the first current path P1 is analogous to the current path of a PIN diode structure to reduce the on-state leakage current of the semiconductor device 1. In some embodiments, the first doped region 310 near the second doped region 320 and the first doped region 310 near the fifth doped region 350 can both form the first current path P1.

[0077] In some embodiments, in the second current path P2, when a voltage is applied to the first conductive layer 510, current flows sequentially along the first contact 410, the first high-voltage well region 112, the epitaxial layer 106, the fourth doped region 340, and the second contact 420 to the second conductive layer 520. Since the first contact 410, which is in direct contact with the first high-voltage well region 112, can serve as the metal portion of a Schottky diode, and the first high-voltage well region 112 can serve as the semiconductor portion of a Schottky diode, a Schottky barrier is generated at the interface between the first high-voltage well region 112 and the first contact 410. Therefore, the second current path P2 can be analogous to the current path of a Schottky diode structure to improve the switching speed of the semiconductor device 1, reduce the recovery time, and / or reduce the on-state voltage. In some embodiments, the first current path P1 can be connected in parallel with the second current path P2. Accordingly, the semiconductor device 1 of this application may include a merged PIN Schottky (MPS) diode in which a Schottky diode and a PIN diode are connected in parallel.

[0078] Reference Figure 4 This is a cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of this application. Figure 4 Showing along the subsequent Figure 5 The diagram shows a cross-sectional view taken from line segment II-II'. In some embodiments, the first doped region 310 physically separates the first contact 410 from the first high-pressure well region 112, thereby preventing the formation of a Schottky barrier at the interface between the first high-pressure well region 112 and the first contact 410. Therefore, in Figure 4 In the semiconductor device 1, there may be a first current path P1, but no second current path P2.

[0079] Reference Figure 5 This is a top view schematic diagram of a semiconductor device 1 according to an embodiment of this application. In some embodiments, in the top view, the first doped region 310 may surround the first contact 410. In some embodiments, in the top view, the extending direction of the gate electrode 220 is a second direction D2, and the openings 312 of the first doped region 310 may be spaced apart along the extending direction of the gate electrode 220, i.e., the second direction D2. In some embodiments, the openings 312 may have triangular, rectangular, circular, elliptical, polygonal, polygonal with arc-shaped edges, or other suitable shapes, but this application is not limited thereto. In some embodiments, the number of openings 312 may be a positive integer from 1 to 100, but this application is not limited thereto.

[0080] Reference Figure 6 This is a top view schematic diagram of a semiconductor device 1 according to an embodiment of this application. For ease of explanation, in Figure 6The diagram only shows the substrate 100, the first high-voltage well region 112, the first doped regions 310 to the fifth doped regions 350, and the opening 312. In some embodiments, in the top view, the first doped region 310 covers the top surface of the first high-voltage well region 112, forming a current path (first current path P1) analogous to a PIN diode structure. In some embodiments, in the top view, the opening 312 of the first doped region 310 may expose the top surface of the first high-voltage well region 112, forming a current path (second current path P2) analogous to a Schottky diode structure. Therefore, the area of ​​the first doped region 310 may correspond to the area of ​​the PIN diode, and the area of ​​the opening 312 surrounded by the first doped region 310 may correspond to the area of ​​the Schottky diode. In some embodiments, when the area of ​​the first doped region 310 may be A3, and the area of ​​the opening 312 surrounded by the first doped region 310 may be A4, the ratio of the PIN diode to the Schottky diode (PIN diode / Schottky diode) may be A3 / A4. In some embodiments, A3 / A4 can be 0.1 to 10, but this application is not limited thereto. For example, A3 / A4 can be 0.1, 0.125, 0.2, 0.25, 0.5, 0.75, 1, 1.33, 2, 4, 5, 8, 10, or any value or range of values ​​between the foregoing, but this application is not limited thereto. Figure 6 As shown, in some embodiments, A3 / A4 may be approximately 2.

[0081] In the following text, identical or similar component symbols and descriptions are omitted.

[0082] Reference Figure 7 This is a top view schematic diagram of a semiconductor device 2 according to an embodiment of this application. In some embodiments, in the top view, the opening 312 of the first doped region 310 may have different sizes to adjust the ratio of an analog Schottky diode structure to an analog PIN diode structure. Figure 7 As shown, in some embodiments, A3 / A4 may be approximately 1.

[0083] Reference Figure 8 This is a top view schematic diagram of a semiconductor device 3 according to an embodiment of the present application. In some embodiments, in the top view, the extending direction of the gate electrode 220 is a second direction D2, and the openings 312 of the first doped region 310 can extend along the extending direction of the gate electrode 220 (second direction D2) and are spaced apart along a first direction D1 perpendicular to the extending direction of the gate electrode 220 (second direction D2).

[0084] Reference Figure 9This is a top view schematic diagram of a semiconductor device 4 according to an embodiment of the present application. In some embodiments, the opening 312 may be disposed on the upper part of the first doped region 310, but not on the lower part of the first doped region 310. In some embodiments, in the top view, the upper edge of the opening 312 may be flush with the upper edge of the first doped region 310. In other embodiments (not shown), in the top view, the upper edge of the opening 312 may be spaced apart from the upper edge of the first doped region 310 by a distance to reduce leakage current.

[0085] In some embodiments, one or more of the semiconductor devices 1 to 4 described in this application may be applied to high voltage integrated circuits (HVICs), particularly to bootstrap circuits.

[0086] Accordingly, this application avoids the accumulation of excess carriers generated in the current path from the first doped region to the fourth doped region in the semiconductor device by setting a second doped region and a third doped region with different conductivity types between the first doped region (i.e., the source doped region) and the fourth doped region (i.e., the drain doped region). Since the first current path P1 of this application is analogous to the current path of a PIN diode structure, the conduction leakage current of the semiconductor device can be reduced. Since the second current path P2 of this application is analogous to the current path of a Schottky diode structure, the switching speed of the semiconductor device can be improved, the recovery time can be reduced, and / or the on-state voltage can be reduced. Since both the first current path P1 and the second current path P2 of this application are analogous to the current path of a combined PIN Schottky diode structure, they can combine the characteristics of both Schottky diodes and PIN diodes. Furthermore, this application can adjust the electrical properties of the semiconductor device by adjusting the ratio (e.g., area ratio) of the structure analogous to a Schottky diode to the structure analogous to a PIN diode. Accordingly, this application can avoid the accumulation of excess carriers, reduce on-state leakage current, improve switching speed, reduce recovery time and / or reduce on-state voltage, thereby improving the electrical properties and reliability of semiconductor devices.

[0087] The scope of protection of this application is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments herein. Any process, machine, manufacturing method, material composition, apparatus, method, and step that is currently available or will be developed in the future can be understood from the disclosure of this application and can be used according to this application as long as it can perform substantially the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of this application includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. No embodiment or claim of this application is required to achieve all the purposes, advantages, and / or features described in this application.

[0088] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this application to achieve the same purpose and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this application, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; An epitaxial layer is disposed on the substrate and has a second conductivity type different from the first conductivity type; A first high-pressure well zone is disposed in the epitaxial layer and has the second conductivity type; A first doped region is disposed in the first high-pressure well region and has the first conductivity type; A second doped region is disposed in the first high-pressure well region and has the first conductivity type; A third doped region is disposed in the first high-pressure well region and has the second conductivity type; A first conductive layer, electrically connected to the first high-pressure well region and the first doped region; and A floating conductive layer is electrically connected to the second doped region and the third doped region, and electrically isolated from the first conductive layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A fourth doped region is disposed in the epitaxial layer and has the second conductivity type, wherein the second doped region and the third doped region are disposed between the first doped region and the fourth doped region; and A second conductive layer is electrically connected to the fourth doped region.

3. The semiconductor device as claimed in claim 2, characterized in that, Compared to the fourth doped region, the second and third doped regions are closer to the first doped region.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A first contact material is disposed on the first high-voltage well region and the first doped region, contacting the first high-voltage well region and the first doped region, and is electrically connected to the first conductive layer. An opening is provided in the first doped region, and the first contact material contacts the first high-pressure well region and the first doped region through the opening.

5. The semiconductor device as claimed in claim 4, characterized in that, In a top view, the first doped region surrounds the first contact.

6. The semiconductor device as claimed in claim 4, characterized in that, Also includes: A gate dielectric layer is disposed on the epitaxial layer; and A gate electrode is disposed on the gate dielectric layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The openings are arranged along the extension direction of the gate electrode, or along a direction perpendicular to the extension direction of the gate electrode.

8. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A first embedded layer is disposed between the substrate and the first high-pressure well area, and has the second conductivity type.

9. The semiconductor device as claimed in claim 8, characterized in that, Also includes: A second high-pressure well zone is disposed in the epitaxial layer and has the first conductivity type; and A fifth doped region is disposed in the second high-pressure well region and has the first conductivity type. The first doped region is disposed between the second doped region and the fifth doped region.

10. The semiconductor device as claimed in claim 9, characterized in that, Also includes: A second embedded layer is disposed between the substrate and the second high-pressure well area, and has the first conductivity type.

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