A method for manufacturing a wire-bonded fan-out package structure

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to a preparation method of a fan-out packaging structure of wire bonding. A temporary bonding glue layer is prepared on the surface of a temporary carrier, a rewiring layer is prepared on the temporary bonding glue layer, the whole is cut into a strip structure, a memory chip is attached and stacked on the surface of the rewiring layer of each strip structure to form a chip group, the chip group is wired, the chip group is plastic encapsulated by plastic encapsulating material, the temporary carrier is removed to expose the temporary bonding glue layer; the temporary bonding glue layer is removed to expose the rewiring layer; a hole is opened at the lowermost pad of the rewiring layer to expose a metal pad, and the hole is a ball mounting hole; a tin ball is mounted in the ball mounting hole by using a ball mounting process; and the fan-out packaging structure is obtained by grinding and cutting. The application changes the packaging structure, can reduce the thickness of a substrate, improve the signal transmission capacity, and reduce the dependence on a traditional substrate, which is beneficial to the application of the future memory chip market.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a method for preparing a wire-bonded fan-out packaging structure. Background Technology

[0002] There are currently two main packaging methods for DRAM chips: traditional wire bonding on a BT substrate (BT resin substrate material) and 3D stacking using TSV technology. Both methods have their own advantages and disadvantages. Wire bonding is a mature technology with relatively low equipment costs, making it the most cost-effective packaging solution, and it can adapt to different chip sizes and substrate types. However, wire bonding involves long interconnect lengths, and the gold wires themselves have resistance and inductance, which can cause significant signal delay, power consumption, and noise (inductive effect) under high-speed signals. Furthermore, because the pads are usually located at the chip edge, the number of I / Os (interconnect density) is limited, making it unable to meet the demands of extremely high bandwidth.

[0003] TSV 3D packaging enables true, vertical, "face-to-face" interconnects between chips, a key path to extending Moore's Law. TSV provides the shortest vertical interconnect path between chips, significantly reducing signal latency and power consumption. Because TSVs can be distributed across the entire chip surface (not just the edges), the interconnect density is extremely high, providing massive parallel data channels—a core technology for high-bandwidth memory (HBM). Furthermore, this technology allows for the integration of chips with different process nodes and functions (such as logic and memory chips) to achieve optimal performance. However, TSV manufacturing, wafer thinning, and bonding processes are complex and require expensive equipment. After chip stacking, heat accumulates vertically, making heat dissipation a major challenge. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a wire-bonded fan-out package structure. The structure fabricated using this method can reduce substrate thickness, improve signal transmission capabilities, and reduce reliance on traditional substrates, which is beneficial for future applications in the memory chip market.

[0005] To achieve the above and other related objectives, the present invention provides the following technical solutions: A method for fabricating a wire-bonded fan-out package structure includes the following steps: A temporary bonding adhesive layer is prepared on the surface of a temporary carrier, and a redistribution layer is prepared on the temporary bonding adhesive layer. The whole structure is cut into strip structures. Memory chips are mounted and stacked on the redistribution layer surface of each strip structure to form a chip group. Wire bonding is performed on the chip group, and the chip group is encapsulated with molding compound. The temporary carrier is removed to expose the temporary bonding adhesive layer. The temporary bonding adhesive layer is removed to expose the redistribution layer. Holes are made at the bottom pad of the redistribution layer to expose the metal pads. The holes are called ball holes. Solder balls are placed in the ball holes using a ball-planting process. The fan-out package structure is obtained by grinding and cutting.

[0006] In one embodiment of the present invention, the method for preparing a redistribution layer on a temporary bonding adhesive layer includes the following steps: A PI layer is coated on a temporary bonding adhesive layer to form an insulating layer as the first layer of the redistribution layer. Photoresist is coated on the insulating layer to form a PI layer. The desired circuit pattern is formed through exposure and development steps. Metal is electroplated in the circuit pattern formed by the photoresist to form a metal layer, thus forming the RDL circuit.

[0007] Furthermore, the number of metal layers in the redistribution layer is 1-8, and the number of PI layers is 1-8.

[0008] In one embodiment of the present invention, wire bonding is performed on the chipset to bond the memory chip to the metal layer of the redistribution layer.

[0009] In one embodiment of the present invention, the temporary carrier is a slide, and the material of the slide includes one of glass, metal and ceramic; the size of the strip structure is 50mm×50mm~300mm×300mm.

[0010] In one embodiment of the present invention, the number of layers in the chipset is 1-32, and the number of stacks is 1-32.

[0011] In one embodiment of the present invention, the wire material for wire bonding includes one or more of gold, silver, copper, and aluminum; the hole-opening method includes one or more of mechanical hole opening, laser hole opening, and chemical etching hole opening.

[0012] In one embodiment of the present invention, the method for preparing a temporary bonding adhesive layer on the surface of a temporary carrier includes the following steps: An accelerator is coated on the surface of a temporary carrier and baked. Then, a temporary bonding adhesive is coated on the accelerator and baked. The adhesive layers of the accelerator and the temporary bonding adhesive together constitute the temporary bonding adhesive layer.

[0013] In one embodiment of the present invention, the method for preparing a temporary bonding adhesive layer on the surface of a temporary carrier includes the following steps: A temporary bonding adhesive is coated on the surface of a temporary carrier and pre-cured. A PEG-PAA aqueous solution is then coated on the temporary bonding adhesive and dried to form an induction layer. The adhesive layer and the induction layer together constitute the temporary bonding adhesive layer.

[0014] It should be noted that an induction layer composed of PEG-PAA aqueous solution is further coated on the temporary bonding adhesive. This induction layer itself does not participate in cross-linking and curing, and has a good synergistic relationship with the underlying colloid: 1) The PEG segments and the colloid have similar coefficients of thermal expansion, and can deform synchronously when heated, avoiding the accumulation of uneven stress at the interface. 2) The PEG-PAA induction layer and the colloid surface form a stable contact through hydrogen bonds and polar interactions; in pure water, the induction layer absorbs water and swells, and its diffused water molecules break down the hydrogen bonds and polar segment aggregation at the colloid interface; without destroying the overall structure of the colloid layer, it guides the colloid to decompose and dissolve layer by layer from the surface, achieving the dual effects of directional exfoliation and directional dissolution.

[0015] Furthermore, the preparation method of the temporary bonding adhesive includes the following steps: Take 2-EHA and acrylamide and stir. Add the matrix resin and continue stirring. Add PETA and PNB and mix well. Add photoinitiator and BPO and dissolve evenly. Filter and let stand to obtain temporary bonding adhesive.

[0016] Furthermore, the matrix resin includes urea-modified acrylate, and the viscosity of the temporary bonded adhesive is 2500-3300 cP.

[0017] It should be noted that: 1. 2-EHA is a branched acrylate monomer. After polymerization, it forms a linear backbone with flexible segments and a low glass transition temperature (Tg), providing a structural basis for subsequent segment slip behavior. It then forms a controllable network structure with the crosslinking agent PETA, transforming into a "rubber state" under heating conditions, exhibiting good thermal softening and slip properties. 2. Acrylamide molecules contain amide groups, which can increase the polarity of the colloid, enhance its adhesion to surfaces such as glass and PI, and participate in the polymerization reaction, increasing the system rigidity and regulating Tg. At room temperature, it enhances the initial bonding force, but at elevated temperatures, its amide hydrogen bonds can be weakened by thermal disturbance, providing a transformation space for subsequent slip release of interfacial binding forces. 3. The matrix resin is a partially prepolymerized medium-to-low molecular weight resin. The introduction of urea groups enhances network strength through hydrogen bonding, while still retaining flexible segments, achieving structural rigidity-flexibility adjustment. It can form a point-connected network between the soft segments of 2-EHA, ensuring structural stability without hindering segment slip at high temperatures. 4. PETA provides multiple double bond sites, which can participate in free radical polymerization with 2-EHA and acrylamide to form a three-dimensional cross-linked network, providing a stable structural framework for the adhesive layer. 5. PNB is a moderately polar diethyl ether solvent, which can effectively disperse various monomers and prepolymers in the formulation and impart wettability, improving the initial wetting between the adhesive layer and glass or metal substrates. After heating, PNB easily migrates to the adhesive layer surface, assisting in the formation of a lubricating layer and promoting thermal slippage.

[0018] The beneficial effects of this invention are: Traditional wire bonding technology operates on a BT substrate. Signals from the chip need to travel through solder balls and circuitry within the BT substrate before reaching the PCB. This long path introduces significant parasitic inductance and resistance, impacting signal integrity and transmission speed. Furthermore, the substrate itself has thickness, and with the chip added, the overall package thickness is difficult to achieve.

[0019] This invention replaces the substrate with a multilayer RDL structure, achieving high-density signal transmission while significantly reducing package thickness, meeting the extreme pursuit of thinness and lightness in mobile devices. Traditional BT substrates are 90-120µm thick, while in this invention, a single RDL layer can be 5-8µm thick. Depending on the number of layers, the thickness of a 1-8 layer RDL substrate ranges from 5-60µm.

[0020] Specifically, this invention can achieve the following: (1) Shorten interconnect paths and reduce parasitic effects: By directly replacing the traditional BT substrate with multilayer RDL, the long path of signals from the chip through solder balls, through the thick BT substrate, and then to the PCB is eliminated. The RDL lines can be designed to be shorter and more optimized, thereby reducing the parasitic inductance and resistance introduced by the interconnect. This results in lower signal transmission delay, less signal attenuation and distortion, and reduced dynamic power consumption.

[0021] (2) High-density interconnect capability: Although edge pad wire bonding is still used, the fan-out design of multi-layer RDL can redistribute and extend the limited I / O pads at the edge of the chip to the entire bottom area of ​​the package, providing connection points for more solder balls. This improves the I / O density and interconnect capability at the package level to a certain extent, falling between traditional wire bonding packaging and TSV, and can support higher bandwidth requirements than traditional wire bonding packaging.

[0022] (3) Reduced costs: 1) Avoided expensive TSV process: Completely bypassed the extremely complex and expensive process steps such as TSV deep hole etching, filling, wafer thinning to tens of micrometers, precision microbump fabrication and ultra-high precision chip-to-chip bonding. 2) Low equipment and material costs.

[0023] (4) Thinning and miniaturization: 1) Removing the BT substrate and replacing it with a multilayer RDL reduces the total thickness of the package by orders of magnitude. 2) It can meet the extreme requirements of mobile devices and provides key hardware support for achieving a thinner and lighter product design.

[0024] Furthermore, the present invention also provides two methods for preparing a temporary bonding adhesive layer on the surface of a carrier: (1) The first method is to first apply an accelerator layer to the surface of the carrier, then coat it with a temporary bonding adhesive material, and then heat and bake it to cure, forming a composite bonding structure. The accelerator contains polar functional groups, which can enhance the adhesion of the temporary adhesive layer to the surface of the glass carrier. (2) The second method is to first coat a PEG-PAA water-soluble inducing layer on the surface of the carrier, and then coat a UV / thermal dual-curing temporary bonding adhesive on top of the inducing layer to form a composite structure. (3) Both the first and second methods achieve the slip separation of the temporary carrier under heating conditions, but the thermal slip mechanism of the two methods is different. 1) In the first method, by heating the encapsulation structure to 180°C, the temporary bonding adhesive layer is significantly softened or even partially broken, the integrity of the adhesive layer structure decreases, and the interface separation is achieved under the action of external force. This process belongs to the passive slip process caused by thermal damage. 2) The second method involves controlling the heating temperature at 130°C. This temperature allows the temporary bonded adhesive layer to enter a rubber state without structural damage. The main chain segments of the adhesive possess slippage capability, and the interfacial shear strength decreases. In this state, only a very small parallel guiding force is needed to cause the temporary carrier and the encapsulation structure to slip off as a whole. This is a controlled thermal slippage mechanism driven by a material state transition. (4) Compared with the first and second methods, the second method is gentler, more thorough, and more environmentally friendly. It provides a cleaner and more stable surface for subsequent processes. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a structural schematic diagram of step one of the present invention; Figure 2 This is a schematic diagram of the structure of the substrate with a temporary bonding adhesive layer on its surface according to the present invention; Figure 3 This is a schematic diagram of the structure of step two of the present invention; Figure 4 This is a schematic diagram of the structure of step three of the present invention; Figure 5 This is a schematic diagram of the structure of step four of the present invention; Figure 6 This is a structural schematic diagram of step five of the present invention; Figure 7 This is a schematic diagram of the structure of step six of the present invention; Figure 8 This is a schematic diagram of the structure of step seven of the present invention; Figure 9 This is a structural schematic diagram of step eight of the present invention; The markings in the diagram are: 1. Temporary carrier; 2. Temporary bonding adhesive layer; 3. Reconnection layer; 4. Chipset; 5. Molding compound; 6. Ball hole; 7. Solder ball. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Unless otherwise specified, the materials used in the embodiments are readily available from commercial companies.

[0029] Example 1 A method for fabricating a wire-bonded fan-out package structure, the specific fabrication steps of which are as follows: Step 1: Refer to Figure 1 Prepare a clean slide as temporary carrier 1. The slide can be glass, metal, or ceramic; refer to... Figure 2 A temporary bonding adhesive layer 2 was prepared on the surface of the substrate.

[0030] Step Two: Refer to Figure 3 A redistribution layer 3 is prepared on the temporary bonding adhesive layer 2. The first layer of the redistribution layer 3 is PI (polyimide). Specifically, a PI layer is coated on the temporary bonding adhesive layer 2 to form an insulating layer as the first layer of the redistribution layer 3. Photoresist is coated on the insulating layer to form a PI layer. The desired circuit pattern is formed through exposure and development steps. Metal is electroplated in the circuit pattern formed by the photoresist to form a metal layer, thus forming the RDL circuit.

[0031] In addition to the first insulating layer, the subsequent electroplated metals and photoresist are used in combination as described above. The number of layers can be stacked, and the number of metal layers in redistribution layer 3 can be 1-8, as can the number of PI layers. Electrical connections are made between the RDL lines in each layer.

[0032] The insulation layer and the RDL lines together constitute the redistribution layer 3.

[0033] The temporary carrier 1 with the prepared redistribution layer 3 is cut into strip structures with a size of 50mm×50mm~300mm×300mm.

[0034] Step 3: Refer to Figure 4Memory chips are mounted and stacked on the surface of the redistribution layer 3 of each strip structure to form a chipset 4. The structure of the chipset 4 can be a 4-layer dual stack, an 8-layer dual stack, or a 16-layer single stack or dual stack. There are various combinations of different numbers of layers and stacks, with 1-32 layers and 1-32 stacks. Among them, dual stack consists of two chipsets 4, and single stack consists of one chipset 4.

[0035] Step Four: Refer to Figure 5 Wire bonding is performed on chipset 4 to bond the memory chips to the metal layer of redistribution layer 3. The wire material can be selected from gold, silver, copper, or aluminum.

[0036] Step 5: Refer to Figure 6 The chipset 4 is encapsulated using molding compound 5, which completely wraps the stacked chipset 4.

[0037] Step Six: Refer to Figure 7 The temporary carrier 1 is removed, exposing the temporary bonding adhesive layer 2; the temporary bonding adhesive layer 2 is removed, exposing the redistribution layer 3.

[0038] Step Seven: Refer to Figure 8 A hole is made at the bottom pad of the redistribution layer 3 to expose the metal pad. The hole can be made mechanically, by laser, or by chemical etching. The hole is named the ball-planting hole 6.

[0039] Step 8: Refer to Figure 9 Using a ball-planting process, solder balls 7 are planted in the ball-planting hole 6.

[0040] Step 9: The final package is obtained through grinding and cutting.

[0041] The following describes a more detailed implementation process, referring to the method in Example 1: Example 2 raw material: Isooctyl acrylate: 2-EHA, industrial grade; Acrylamide: analytical grade; Matrix resin: Urea-modified acrylate, Laromer® UA 19T is an option; Pentaerythritol triacrylate: PETA; Benzoyl peroxide: BPO; Photoinitiator: Irgacure 2959; Propylene glycol ethyl ether: PNB; The following preparation was carried out using the aforementioned raw materials: by weight, 35 parts of 2-EHA and 15 parts of acrylamide were taken, stirred at 300 rpm for 5 min, 10 parts of matrix resin were added, and stirring was continued for 10 min, 10 parts of PETA and 5 parts of PNB were added, and the mixture was mixed. Photoinitiator and 2 parts of BPO were added, and the mixture was dissolved evenly. The mixture was filtered and allowed to stand for 30 min to obtain a temporary bonding adhesive with a viscosity of 2500-3300 cP.

[0042] Example 3 raw material: Temporary bonding adhesive: Brewer Science® WaferBOND® HT-10.10; Accelerator: Accelerator AP-3000.

[0043] A wire-bonded fan-out package structure was prepared using the aforementioned raw materials. The specific preparation steps are as follows: Step 1: Refer to Figure 1 Prepare a clean glass slide as temporary support 1; refer to... Figure 2 An accelerator is coated on the surface of the substrate and baked on a hot plate at 150°C for 1 minute. Then, the aforementioned temporary bonding adhesive is coated on the accelerator and baked on a hot plate at 130°C for 4 minutes. The adhesive layer thickness is 20 μm. The adhesive layers of the accelerator and the temporary bonding adhesive together constitute the temporary bonding adhesive layer 2.

[0044] Step Two: Refer to Figure 3 A redistribution layer 3 is prepared on the temporary bonding adhesive layer 2. The first layer of the redistribution layer 3 is PI (polyimide). Specifically, a PI layer is coated on the temporary bonding adhesive layer 2 to form an insulating layer as the first layer of the redistribution layer 3. Photoresist is coated on the insulating layer to form a PI layer. The desired circuit pattern is formed through exposure and development steps. Metal is electroplated in the circuit pattern formed by the photoresist to form a metal layer, thus forming the RDL circuit.

[0045] In addition to the first insulating layer, the subsequent electroplated metals and photoresist are used in combination as described above. The number of layers can be stacked, and the number of metal layers in redistribution layer 3 can be 1-8, as can the number of PI layers. Electrical connections are made between the RDL lines in each layer.

[0046] The insulation layer and the RDL lines together constitute the redistribution layer 3.

[0047] The temporary carrier 1 with the prepared redistribution layer 3 is cut into strips of size, which can be 50mm×50mm~300mm×300mm.

[0048] Step 3: Refer to Figure 4Memory chips are mounted and stacked on the surface of redistribution layer 3 to form chipset 4. The structure of chipset 4 can be 4-layer dual stack, 8-layer dual stack, or 16-layer single stack or dual stack. There are various combinations of different numbers of layers and stacks, with 1-32 layers and 1-32 stacks. Among them, dual stack consists of two chipsets 4, and single stack consists of one chipset 4.

[0049] Step Four: Refer to Figure 5 Wire bonding is performed on chipset 4 to bond the chips to the metal layer of redistribution layer 3. The wire material can be selected from gold, silver, copper, or aluminum.

[0050] Step 5: Refer to Figure 6 The chipset 4 is encapsulated using molding compound 5, which completely wraps the stacked chipset 4.

[0051] Step Six: Refer to Figure 7 The temporary carrier 1 is removed, exposing the temporary bonding adhesive layer 2; the temporary bonding adhesive layer 2 is removed, exposing the redistribution layer 3.

[0052] Step Seven: Refer to Figure 8 A hole is made at the bottom pad of the redistribution layer 3 to expose the metal pad. The hole can be made mechanically, by laser, or by chemical etching. The hole is named the ball-planting hole 6.

[0053] Step 8: Refer to Figure 9 Using a ball-planting process, solder balls 7 are planted in the ball-planting hole 6.

[0054] Step 9: The final package is obtained through grinding and cutting.

[0055] Example 4 raw material: PEG-PAA aqueous solution: Polyacrylic acid polyethylene glycol block copolymer (PAA-b-PEG), with PAA molecular weight selected as 5000 Da and PEG molecular weight selected as 2000 Da.

[0056] A wire-bonded fan-out package structure was prepared using the aforementioned raw materials. The specific preparation steps are as follows: Step 1: Refer to Figure 1 Prepare a clean glass slide as temporary support 1; refer to... Figure 2 The temporary bonding adhesive prepared in Example 2 was coated on the surface of the substrate and pre-cured by UV light for 20 seconds, with a thickness of 20µm. A PEG-PAA aqueous solution was coated on the temporary bonding adhesive and dried to form a 1.5µm induction layer. The adhesive layer and the induction layer together constitute the temporary bonding adhesive layer 2.

[0057] Step Two: Refer toFigure 3 A redistribution layer 3 is prepared on the temporary bonding adhesive layer 2. The first layer of the redistribution layer 3 is PI (polyimide). Specifically, a PI layer is coated on the temporary bonding adhesive layer 2 to form an insulating layer as the first layer of the redistribution layer 3. Photoresist is coated on the insulating layer to form a PI layer. The desired circuit pattern is formed through exposure and development steps. Metal is electroplated in the circuit pattern formed by the photoresist to form a metal layer, thus forming the RDL circuit.

[0058] In addition to the first insulating layer, the subsequent electroplated metals and photoresist are used in combination as described above. The number of layers can be stacked, and the number of metal layers in redistribution layer 3 can be 1-8, as can the number of PI layers. Electrical connections are made between the RDL lines in each layer.

[0059] The insulation layer and the RDL lines together constitute the redistribution layer 3.

[0060] The temporary carrier 1 with the prepared redistribution layer 3 is cut into strips of size, which can be 50mm×50mm~300mm×300mm.

[0061] Step 3: Refer to Figure 4 Memory chips are mounted and stacked on the surface of redistribution layer 3 to form chipset 4. The structure of chipset 4 can be 4-layer dual stack, 8-layer dual stack, or 16-layer single stack or dual stack. There are various combinations of different numbers of layers and stacks, with 1-32 layers and 1-32 stacks. Among them, dual stack consists of two chipsets 4, and single stack consists of one chipset 4.

[0062] Step Four: Refer to Figure 5 Wire bonding is performed on chipset 4 to bond the chips to the metal layer of redistribution layer 3. The wire material can be selected from gold, silver, copper, or aluminum.

[0063] Step 5: Refer to Figure 6 The chipset 4 is encapsulated using molding compound 5, which completely wraps the stacked chipset 4.

[0064] Step Six: Refer to Figure 7 The temporary carrier 1 is removed, exposing the temporary bonding adhesive layer 2; the temporary bonding adhesive layer 2 is removed, exposing the redistribution layer 3.

[0065] Step Seven: Refer to Figure 8 A hole is made at the bottom pad of the redistribution layer 3 to expose the metal pad. The hole can be made mechanically, by laser, or by chemical etching. The hole is named the ball-planting hole 6.

[0066] Step 8: Refer to Figure 9 Using a ball-planting process, solder balls 7 are planted in the ball-planting hole 6.

[0067] Step 9: The final package is obtained through grinding and cutting.

[0068] The following evaluation and analysis will be conducted on step six, “removing the temporary carrier 1”, of Examples 3 and 4. Samples were prepared according to the methods of Examples 3 and 4. The specific parameters of steps two to five do not affect the removal of the temporary bonding adhesive layer 2, so specific point values ​​are not given here. In order to control experimental variables, the same parameters can be selected when preparing samples.

[0069] The methods for removing temporary carrier 1 are as follows: In Example 3: The prepared encapsulation structure was placed on a hot stage at 180°C and heated for 5 minutes to soften or partially break the bonds of the temporary bonding adhesive layer 2. Then, the temporary carrier 1 was slowly removed from above along the parallel direction using a vacuum adsorption platform.

[0070] In Example 4: The prepared encapsulation structure was placed in an oven at 130°C and heated for 4 minutes, causing the flexible polyacrylate backbone in the temporary bonding adhesive layer 2 to enter a rubber state, where the chain segments possess sliding ability, thereby reducing the interfacial shear strength between it and the temporary carrier 1. Subsequently, a minimal displacement was applied along the parallel direction using a vacuum adsorption platform to guide the temporary carrier 1 to slip and separate from the encapsulation structure as a whole.

[0071] Analysis: Both Examples 3 and 4 achieve the slip-off separation of the temporary carrier 1 under heating conditions, but their thermal slip-off mechanisms differ. In Example 3, heating the encapsulation structure to 180°C causes significant softening and even local chain breakage of the temporary bonded adhesive layer, reducing the structural integrity of the adhesive layer. Under external force, interfacial separation occurs; this process is a passive slip-off process triggered by thermal damage. In Example 4, the heating temperature is controlled at 130°C. This temperature only causes the temporary bonded adhesive layer to enter a rubbery state without structural damage. The main chain segments of the adhesive possess slippage capability, and the interfacial shear strength decreases. In this state, only a very small parallel guiding force is needed to induce the temporary carrier and encapsulation structure to slip-off as a whole, representing a controlled thermal slip-off mechanism driven by a material state transition.

[0072] The following evaluation and analysis will be conducted on step six, “removing the temporary bonding adhesive layer 2”, of Examples 3 and 4. Samples were prepared according to the methods of Examples 3 and 4 respectively. The specific parameters of steps two to five do not affect the removal of the temporary bonding adhesive layer 2, so specific point values ​​are not given here. In order to control experimental variables, the same parameters can be selected when preparing samples.

[0073] The methods for removing the temporary bonding adhesive layer 2 are as follows: In Example 3: The structure after removing the temporary carrier 1 is placed on a hot plate and heated to 180°C for 3 minutes to further soften and peel off the temporary bonding adhesive layer 2. The surface can then be further soaked or wiped with IPA solution (isopropanol) to remove the softened adhesive layer residue.

[0074] In Example 4: The entire structure was immersed in pure water at 30-40°C for 2 minutes, at which point the temporary bonding adhesive layer 2 began to dissolve. It was then rinsed once with IPA solution and dried on a hot plate at 80°C for 1 minute.

[0075] Analysis: In Example 3, the adhesive layer was softened again by high temperature before removal. To ensure complete removal, the dissolving and swelling effects of IPA were utilized. In Example 4, the PEG-PAA-based induction layer and the underlying colloidal portion affected by it are soluble in warm water. Water molecules can directly disrupt the hydrogen bonds between polymer chains, causing them to dissociate and dissolve in water, detaching from the surface. Example 4 eliminates the need for a secondary high-temperature treatment, avoiding thermal stress accumulation. Furthermore, the use of water to replace most organic solvents improves compatibility and safety with the encapsulated internal materials, making the cleaning process gentler, more thorough, and more environmentally friendly. This provides a cleaner and more stable surface for subsequent processes.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a wire-bonded fan-out package structure, characterized in that, Includes the following steps: A temporary bonding adhesive layer is prepared on the surface of a temporary carrier, and a redistribution layer is prepared on the temporary bonding adhesive layer. The whole is cut into strip structures, and memory chips are mounted and stacked on the redistribution layer surface of each strip structure to form a chip group. The chip group is wire bonded, and the chip group is encapsulated with molding compound. The temporary carrier is removed to expose the temporary bonding adhesive layer. Remove the temporary bonding adhesive layer to expose the redistribution layer; make holes at the bottom pads of the redistribution layer to expose the metal pads; the holes are ball-mounting holes. Solder balls are implanted into the ball-planting holes using a ball-planting process; Grinding and cutting are used to obtain a fan-out package structure; Methods for preparing a temporary bonding adhesive layer on the surface of a temporary carrier include: A temporary bonding adhesive is coated on the surface of a temporary carrier and pre-cured. A PEG-PAA aqueous solution is then coated on the temporary bonding adhesive and dried to form an induction layer. The adhesive layer and the induction layer together constitute the temporary bonding adhesive layer. The preparation method of the temporary bonding adhesive includes the following steps: Take 2-EHA and acrylamide and stir. Add the matrix resin and continue stirring. Add PETA and PNB and mix well. Add photoinitiator and BPO and dissolve evenly. Filter and let stand to obtain temporary bonding adhesive.

2. The method for fabricating a wire-bonded fan-out package structure according to claim 1, characterized in that, The method for preparing a redistribution layer on a temporary bonding adhesive layer includes the following steps: A PI layer is coated on a temporary bonding adhesive layer to form an insulating layer as the first layer of the redistribution layer. Photoresist is coated on the insulating layer to form a PI layer. The desired circuit pattern is formed through exposure and development steps. Metal is electroplated in the circuit pattern formed by the photoresist to form a metal layer, thus forming the RDL circuit.

3. The method for fabricating a wire-bonded fan-out package structure according to claim 2, characterized in that, The number of metal layers in the redistribution layer is 1-8, and the number of PI layers is 1-8; wire bonding is performed on the chipset to bond the memory chip to the metal layers of the redistribution layer.

4. The method for fabricating a wire-bonded fan-out package structure according to claim 1, characterized in that, The temporary carrier is a slide, which can be made of glass, metal or ceramic; the size of the strip structure is 50mm×50mm~300mm×300mm.

5. The method for fabricating a wire-bonded fan-out package structure according to claim 1, characterized in that, The chipset has 1-32 layers and 1-32 stacks.

6. The method for fabricating a wire-bonded fan-out package structure according to claim 1, characterized in that, The wire material for wire bonding includes one or more of gold, silver, copper, and aluminum; the hole-making method includes one or more of mechanical hole-making, laser hole-making, and chemical etching hole-making.

7. The method for fabricating a wire-bonded fan-out package structure according to claim 1, characterized in that, The matrix resin includes urea-modified acrylate, and the viscosity of the temporary bonded adhesive is 2500-3300 cP.

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