Post-simulation method and apparatus, electronic device, storage medium and program product

Abstract

Embodiments of the present disclosure provide a post-simulation method and device, electronic equipment, storage medium and program product. The post-simulation method comprises: obtaining a simulation delay when a test platform and a target system interact with signals by using a target timing model; wherein the target timing model is determined based on a current interaction scenario between the test platform and the target system; marking a first connection file according to the simulation delay to obtain a second connection file; wherein the first connection file comprises a signal mapping table and / or a connection description file between the test platform and the target system; the second connection file adds the simulation delay on the basis of the first connection file; and performing post-simulation of the target system based on the second connection file.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of simulation technology, and in particular to a post-simulation method and apparatus, electronic devices, storage media, and program products. Background Technology

[0002] In related technologies, SoC (System on Chip) verification can include, but is not limited to, pre-simulation and post-simulation. Post-simulation is performed after the SoC layout design is completed, by back-annotating parasitic parameters and interconnect delays to the extracted circuit netlist for simulation, analyzing the circuit, and ensuring that the circuit meets design requirements. Currently, test platforms are typically used to send stimulus signals and sample the output of the target system to improve simulation speed. However, since the test platform itself does not contain delay information, sampling errors are prone to occur in post-simulation. Therefore, existing solutions mainly determine the interaction delay between these two methods through manual debugging and rough estimation, which suffers from low accuracy, high cost, and low simulation efficiency. Summary of the Invention

[0003] This disclosure provides a post-simulation method and apparatus, electronic device, storage medium, and program product.

[0004] The technical solution of this disclosure embodiment is implemented as follows: This disclosure provides a post-simulation method, including: The target timing model is used to obtain the simulated delay when the test platform and the target system interact with signals; the target timing model is determined based on the current interaction scenario between the test platform and the target system. The first connection file is marked according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file; Post-simulation of the target system is performed based on the second linker file.

[0005] This disclosure provides a post-simulation device, including: The determination module is used to obtain the simulated delay when the test platform and the target system interact with signals using the target timing model; wherein, the target timing model is determined based on the current interaction scenario between the test platform and the target system; A tagging module is used to tag the first connection file according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file; The post-simulation module is used to perform post-simulation of the target system based on the second linker file.

[0006] This disclosure provides an electronic device, including a processor and a memory, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the above-described method.

[0007] This disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0008] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, the above-described method is implemented.

[0009] In this embodiment, on the one hand, the simulated delay between the target system and the test platform is obtained through the target timing module. First, since this simulated delay can realistically reflect the timing behavior in the actual signal interaction process, it ensures that various sampling problems caused by timing constraints, omissions, etc., will not occur in the post-simulation process, thereby improving the quality of the post-simulation. Second, compared with manual debugging and rough estimation, it improves the accuracy of delay information and reduces costs while improving simulation efficiency. Finally, by comprehensively considering the impact of the interaction scenario between the target system and the test platform on signal sampling, the accuracy and reliability of the delay information are further improved. On the other hand, the original connection file is automatically marked according to the simulated delay to simplify the delay processing of signals sent by the test platform in the post-simulation process, accelerating simulation verification and further improving the efficiency of the post-simulation. Furthermore, the target timing model is determined according to the interaction scenario between the test platform and the target system, realizing the adaptability between the timing model and the interaction scenario, improving the accuracy of the target timing model, thereby improving the stability and efficiency of the post-simulation. Meanwhile, since this post-simulation method does not need to consider the differences between different subsystems and different process angles, it is applicable to different subsystems and different process angles of the same subsystem, thus improving its compatibility, reusability and universality.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0012] Figure 1 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the present disclosure. Figure 1 ; Figure 2 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the disclosure. Figure 2 ; Figure 3 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the disclosure. Figure 3 ; Figure 4A A schematic diagram illustrating the determination of delay information in a related art according to an embodiment of this disclosure; Figure 4B A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the present disclosure is shown in Figure 4. Figure 4C A schematic diagram of a first interactive scenario provided in an embodiment of this disclosure; Figure 4D A schematic diagram of a second interactive scenario provided in an embodiment of this disclosure; Figure 4E This is a timing diagram of a first interactive scenario provided by an embodiment of the present disclosure; Figure 4F This is a timing diagram of a second interactive scenario provided by an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the composition structure of a post-simulation device provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0017] The method provided in this disclosure can be executed by an electronic device, which can be a laptop, tablet, desktop computer, set-top box, mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0018] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the disclosure. Figure 1 ,like Figure 1 As shown, the post-simulation method includes steps S11 and S13, wherein: Step S11: Use the target timing model to obtain the simulated delay when the test platform and the target system interact with signals; wherein, the target timing model is determined based on the current interaction scenario between the test platform and the target system.

[0020] Here, the target system can be any suitable hardware subsystem module that needs to be simulated and verified, such as a logic module or a subsystem of a SoC. The target system includes at least circuit modules consisting of sequential logic and combinational logic, which may include logic blocks such as AND gates, OR gates, flip-flops, and inverters. The target system operates after receiving a stimulus signal through a port. The port of the target system may include, but is not limited to, the first signal input port. First signal output port First clock port wait.

[0021] The test platform (or stimulus system) can be any suitable platform capable of transmitting stimulus signals. For example, the test platform can be a subsystem within a System-on-a-Chip (SoC). This test platform can be a tool used to replace a real master / slave module, capable of sending stimulus signals to the target system and sampling and evaluating the response signals output by the target system. The ports of this test platform can include, but are not limited to, a second signal input port. Second signal output port Second clock port wait.

[0022] The signal input ports (including a first signal input port and a second signal input port) are used to receive data signals, and there can be at least one such signal input port. The data signal can be a single-bit data signal or a multi-bit signal.

[0023] The signal output ports (including the first signal output port and the second signal output port) are used to output data signals, and the number of signal output ports can be at least one.

[0024] Clock ports (including a first clock port and a second clock port) are used to receive clock signals. These clock signals can be generated by a target clock source located outside the target system and test platform. In some implementations, the target clock source can be a PLL (Phase-Locked Loop) within the SoC. In practice, both the first clock port of the target system and the second clock port of the test platform are connected to the target clock source to receive its clock signal. In some implementations, the number of clock ports can be at least one. The number of clock ports is adapted to the number of signal input ports. For example, if there are five signal input ports, the number of clock ports can be one or more.

[0025] The target system and the test platform are connected via ports. In some embodiments, the signal input port of the target system is connected to the signal output port of the test platform.

[0026] Interaction scenarios characterize the communication mode or connection structure between the test platform and the target system. In some implementations, the connection method between the target system and the test platform may differ for different interaction scenarios; that is, the interaction paths between the test platform and the target system are at least partially different.

[0027] The interaction scenario can include, but is not limited to, the first interaction scenario and the second interaction scenario. The first interaction scenario refers to the test platform being mounted on a port of the target system, meaning the test platform is located outside the target system. The second interaction scenario refers to a subsystem of the target system being taken over by the test platform; that is, the test platform takes over and replaces the target system in performing its functions, meaning the test platform is located inside the target system. In implementation, in the first interaction scenario, the target system's signal input port is connected to the test platform's signal output port, and vice versa. In this case, the test platform can act as a transmitter, sending excitation signals to the target system's input port. In the second interaction scenario, the target system's signal input port is connected to the test platform's signal input port, and vice versa. In this case, the test platform can act as a receiver, receiving signals sent from the target system's input port. Therefore, the direction and path of signal flow differ in these two scenarios.

[0028] A timing model is a mathematical abstract description of the delay behavior of interface signals on a test platform, used to predict and calculate the propagation time of signals during simulation. This timing model can be any suitable neural network model or mathematical model capable of determining the simulation delay. The timing model may include, but is not limited to, a first timing model (or model A), a second timing model (or model B), etc. In some implementations, different interaction scenarios can correspond to different timing models. For example, in the case of a first interaction scenario, the target timing model can be model A, which is a timing model established under the first interaction scenario; in the case of a second interaction scenario, the target timing model can be model B, which is a timing model established under the second interaction scenario.

[0029] In some implementations, different timing models can use different timing parameters from a timing parameter set to determine the simulation delay, ensuring that the signal interaction between the test platform and the target system can be sampled under different interaction scenarios. This timing parameter set may include at least one timing parameter. For example, the timing parameter set may include the clock cycle of the second clock port of the test platform, which is used to drive and sample the signals at the port of the test platform. Alternatively, the timing parameter set may include multiple delays, such as clock port delays, transmission delay sets, etc., where the clock port delay characterizes the delay from the target clock source to the first clock port of the target system, and the transmission delay set includes the transmission delay of the first register driving the first signal output port.

[0030] Analog delay refers to the required delay value on each signal line calculated based on the target timing model. These delay values ​​may be the shift of the clock signal or the delay value of the data signal. In some implementations, the analog delay may include, but is not limited to, the following: Corresponding clock delay, at least one The corresponding signal delay, etc., can be simulated to truly reflect the actual timing of the target system.

[0031] The simulation delay can be determined in any suitable way.

[0032] In some implementations, the target timing parameter values ​​at a target process corner can be input into the target timing model from the timing parameter set to obtain the simulated delay. The target timing parameter is determined based on the target timing model or the current interaction scenario. This timing parameter may differ at different process corners, which may include, but are not limited to, Fast Corner, Slow Corner, and Typical Corner. In practice, the simulated delay is obtained by inputting the target timing parameter values ​​into the target timing model.

[0033] In some implementations, the entire set of timing parameters can be input into the target timing model to obtain the simulated delay.

[0034] Step S12: Mark the first connection file according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file.

[0035] Here, the first connection file can be a standard netlist connection file, which describes the signal mapping relationships and physical connection structures between the test platform and the target system. The first connection file can contain signal names, directions (input / output), port numbers, connection relationships, etc. For example, the first connection file can record... How the signal is connected to the target system Signals. Understandably, the first linker file usually does not contain delay information; therefore, it cannot be directly used for post-timing simulation.

[0036] In some implementations, the analog delay can be labeled using positive or negative annotations to generate a second connection file; that is, this delay information is added to the definition of the corresponding signal. For example, for a certain output signal... If it is determined that a signal requires a delay of 0.5 ns (nanoseconds) to be correctly sampled, then the corresponding delay attribute, such as "delay=0.5ns", will be added to the signal in the second connection file. This process can be called tagging, which makes the second connection file not only describe the signal connection relationship, but also contain precise delay information for subsequent simulation.

[0037] The implementation of the simulated delay marking can be any suitable method. For example, using a script to automatically mark the simulated delay can avoid errors caused by manually modifying the first linker file and improve the efficiency and consistency of delay marking. Another example is using any suitable simulation software to automatically mark the simulated delay. Yet another example is that since buffers can be set between the ports of the target system and the test platform, the delay values ​​of each buffer can be configured using a hardware description language based on the simulated delay to achieve simulated delay marking.

[0038] Step S13: Perform post-simulation of the target system based on the second linker file.

[0039] Here, post-simulation refers to the simulation process after adding timing information to the gate-level netlist. Post-simulation is a crucial step in verifying whether the chip design meets expected performance. In implementation, the initial netlist of the target system can be updated using the second linker file to obtain the target netlist. Then, appropriate excitation signals are applied to perform post-simulation on the target system, accurately simulating the signal propagation path and delay between the test platform and the target system during the simulation. The initial netlist is the circuit netlist of the target system.

[0040] In some implementations, the delay information corresponding to the target system can be obtained first, the target netlist can be back-annotated based on the delay information, and then the target system can be post-simulated using the back-annotated target netlist. The delay information corresponding to the target system may include, but is not limited to, the delay of each component of the target system, the delay of internal interconnects, etc.

[0041] In this embodiment, on the one hand, the simulated delay between the target system and the test platform is obtained through the target timing module. First, since this simulated delay can realistically reflect the timing behavior in the actual signal interaction process, it ensures that various sampling problems caused by timing constraints, omissions, etc., will not occur in the post-simulation process, thereby improving the quality of the post-simulation. Second, compared with manual debugging and rough estimation, it improves the accuracy of delay information and reduces costs while improving simulation efficiency. Finally, by comprehensively considering the impact of the interaction scenario between the target system and the test platform on signal sampling, the accuracy and reliability of the delay information are further improved. On the other hand, the first connection file is automatically marked according to the simulated delay to simplify the delay processing of signals sent by the test platform in the post-simulation process, accelerating simulation verification and further improving the efficiency of the post-simulation. Furthermore, the target timing model is determined according to the interaction scenario between the test platform and the target system, realizing the adaptability between the timing model and the interaction scenario, improving the accuracy of the target timing model, thereby improving the stability and efficiency of the post-simulation. Meanwhile, since this post-simulation method does not need to consider the differences between different subsystems and different process angles, it is applicable to different subsystems and different process angles of the same subsystem, thus improving its compatibility, reusability and universality.

[0042] Figure 2 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the disclosure. Figure 2 ,like Figure 2 As shown, the post-simulation method includes steps S21 and S24, wherein: Step S21: Determine the target timing model based on the current interaction scenario between the test platform and the target system; wherein, under different interaction scenarios, the interaction path between the test platform and the target system is at least partially different.

[0043] In integrated circuit design, GLS (Gate Level Simulation) is a crucial step in verifying the functionality and timing correctness of a chip. During this process, the test platform and the target system (such as hardware subsystem modules) interact via signals, and these signals exhibit a certain delay during transmission in the actual physical circuit. Therefore, to ensure accurate simulation results, it is essential to perform appropriate delay modeling on the interface signals of the test platform.

[0044] The current interaction scenario may include, but is not limited to, the first interaction scenario or the second interaction scenario.

[0045] The first interactive scenario represents a test platform located outside the target system. The test platform simulates excitation signals in a real environment and acquires the response signals of the target system. In this first interactive scenario, there is a clear physical boundary between the test platform and the target system. Therefore, it is necessary to model the test platform and consider factors such as signal delay, transmission path, and sampling accuracy to ensure that the test platform can correctly sample the output signals of the target system.

[0046] The second interactive scenario represents a test platform located within the target system. In this case, the test platform is no longer an external, independent device but is embedded in the target system, replacing the functions originally performed by actual modules (such as Master / Slave). For example, in a System-on-a-Chip (SoC), the test platform can replace a subsystem module and directly control the input and output signals of the subsystem module replaced by the test platform. In this scenario, the interaction between the test platform and the target system is closer, and the signal path is shorter. Therefore, modeling requires considering details such as the internal register clock path, setup time, and hold time to ensure that the test platform can accurately mimic the behavior of the original module and avoid sampling errors caused by delay mismatches.

[0047] In this way, by distinguishing the position of the test platform within the target system, it is helpful to establish a more realistic timing model, which can significantly improve the accuracy of the model, thereby improving the reliability of post-timing simulation, reducing the probability of simulation failure, and shortening the debugging cycle.

[0048] In some implementations, when the test platform is located outside the target system, the signal transmission path between it and the target system may be long, requiring consideration of more timing parameters; while when the test platform is embedded inside the target system, it may be necessary to focus on the register timing relationships of the interfaces between modules. Therefore, different interaction scenarios can correspond to different timing models.

[0049] The target timing model can be determined in any suitable way. In some implementations, a correspondence between each interaction scenario and each timing model can be established in advance. Based on this correspondence, a target timing model that fits the current interaction scenario can be obtained.

[0050] Step S22: Use the target timing model to obtain the simulated delay when the test platform and the target system interact with signals; wherein, the target timing model is determined based on the current interaction scenario between the test platform and the target system.

[0051] Step S23: Back-annotate the first connection file according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file.

[0052] Step S24: Perform post-simulation of the target system based on the second linker file.

[0053] Here, steps S22 to S24 correspond to steps S11 to S13, respectively. In practice, refer to the specific implementation of steps S11 to S13.

[0054] In this embodiment of the disclosure, by identifying the specific interaction scenarios between the test platform and the target system and selecting the corresponding timing model accordingly, it is possible not only to more accurately model the signal interaction behavior between the two, providing a reliable basis for subsequent timing analysis and simulation, but also to better adapt to the timing characteristics under different interaction scenarios, thereby improving the credibility and practicality of the post-simulation results.

[0055] Figure 3 A schematic diagram of the implementation process of a post-simulation method provided in this embodiment of the present disclosure. Figure 3 ,like Figure 3 As shown, the post-simulation method includes steps S31 and S34, wherein: Step S31: Obtain the parameter values ​​of multiple timing parameters in the timing parameter set at the target process angle; wherein, the timing parameters have different parameter values ​​at different process angles.

[0056] Here, the timing parameter set is a set of parameters describing the behavior of a circuit, used to characterize the delay characteristics of a gate-level circuit at different process corners. The target process corner refers to a specific combination of process conditions considered during chip manufacturing. In practice, because the physical implementation of integrated circuits is affected by the manufacturing process, each timing parameter will exhibit different values ​​at different process corners. For example, register setup time may be shorter at fast process corners, while it may be longer at slow process corners.

[0057] The timing parameter values ​​can be obtained in any suitable way. In some implementations, the timing parameter values ​​at different process corners can be extracted when performing STA (Static Timing Analysis) on the target system's PR (Place & Route) netlist file. In some implementations, the timing parameter values ​​at the target process corner can be read from a database containing the timing parameter values ​​for each process corner.

[0058] Step S32: Using the target timing model, determine the target timing parameters from multiple timing parameters in the timing parameter set. Different timing models use at least some different timing parameters. Based on the parameter values ​​of the target timing parameters, determine the simulation delay. The simulation delay includes at least one of the following: the clock delay corresponding to the second clock port of the test platform, and the signal delay corresponding to at least one second signal output port of the test platform.

[0059] Here, the target timing model can be any suitable neural network model or mathematical model capable of determining the simulation delay based on the parameter values ​​of the target timing parameters. In implementation, different interaction scenarios correspond to different timing models.

[0060] Different timing models select appropriate target timing parameters to determine the simulation delay. Simulation delay can include at least two types: clock delay, which is the delay of the test platform's clock port relative to the real clock; and signal delay, which is the delay of the test platform's output port relative to the target system.

[0061] In some implementations, different delay calculations may select different target timing parameters. For example, when determining clock delay, the target timing parameter may include a first target timing parameter; when determining signal delay, the target timing parameter may include a second target timing parameter.

[0062] In some implementations, different timing parameters are selected for different timing models for the same delay. For example, for clock delay, if the target timing model is model A, then the first target timing parameters may include the clock period of the second clock port, the clock port delay, the first clock delay set, the first data delay set, the transmission delay set, etc.; if the timing model is model B, then the first target timing parameters may include the clock port delay, the second clock delay set, the setup time set, the margin set, etc.

[0063] In practice, the process of determining the simulation delay using the target timing model can be found in the specific implementation of step S11 above.

[0064] Step S33: Mark the first connection file according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file.

[0065] Step S34: Perform post-simulation of the target system based on the second linker file.

[0066] Here, steps S33 and S34 correspond to steps S12 and S13 as described above, respectively. In practice, please refer to the specific implementation of steps S12 and S13.

[0067] In this embodiment, the simulated delay is determined by using the parameter values ​​of the timing parameters of the target timing model at the target process corner. On the one hand, since the timing model fully considers the impact of timing parameters such as register propagation delay, register setup time, and register hold time on signal sampling, it can more comprehensively reflect the timing changes in actual chip manufacturing, improving the accuracy and reliability of delay information, thereby ensuring stable sampling of signals at the clock edge and reducing the risk of timing violations caused by contention or jitter. On the other hand, since the timing model can be adapted to different process corners, it supports timing verification in multiple scenarios, improving robustness and compatibility. Furthermore, different timing parameters are selected for different models, making the models more flexible and adaptable to different design environments and verification requirements.

[0068] In some embodiments, the target system includes a first clock port, at least one first signal output port, a first register driving each first signal output port, at least one first signal input port, and a second register driven by each first signal input port; the test platform includes a second clock port; the timing parameter set includes at least one of the following: clock port delay, characterizing the delay from the target clock source to the first clock port; a first clock delay set, including the clock delay corresponding to each first signal output port, wherein the clock delay corresponding to the first signal output port is the clock delay from the target clock source to the corresponding first register driving the first signal output port; a first data delay set, including the data delay corresponding to each first signal output port, wherein the data delay corresponding to the first signal output port is the data delay from the first register driving the first signal output port to the first signal output port; transmission delay. The set includes: a delay set, comprising the transmission delay of the first register driving the first signal output port; a second clock delay set, comprising the clock delay corresponding to each first signal input port, wherein the clock delay corresponding to the first signal input port is the clock delay from the target clock source to the second register driven by the first signal input port; a setup duration set, comprising the setup duration of the second register driven by each first signal input port; a hold duration set, comprising the hold duration of the second register driven by each first signal input port; a second data delay set, comprising the data delay corresponding to each first signal input port, wherein the data delay corresponding to the first signal input port is the data delay from the first signal input port to the second register driven by the first signal input port; a margin set, comprising the setup duration margin of the second register driven by each first signal input port based on the actual timing; and the clock cycle of the second clock port of the test platform.

[0069] Here, the clock port delay... This refers to the target clock source to The propagation delay is significant. Clock port delay can be affected by factors such as wiring path length, parasitic capacitance, and wiring impedance. During simulation, if the clock port delay value is not set correctly, the simulation may result in discrepancies between the sampling time and the actual signal changes, thus affecting the accuracy of the verification results.

[0070] The target system includes at least one at least one Each Each corresponds to a first register Each Each corresponds to a second register , Used to drive the corresponding , Corresponding drive.

[0071] The first clock delay set includes various Corresponding clock delay , Is the target clock source to The clock delay is the delay between the target clock source and the clock input of the first register. The first clock delay set is crucial to ensuring that the output signal is triggered at the correct clock edge.

[0072] The second clock delay set includes various Corresponding clock delay , Is the target clock source to The second clock delay is the delay between the target clock source and the clock input of the second register. This second clock delay set is crucial to ensuring that the input signal is sampled at the appropriate clock edge.

[0073] The first data delay set includes various Corresponding data latency , yes arrive The data delay. The delay described by the first data delay set is determined by the wiring path from the first register output to the first signal output port, and may include wiring delay, gate-level logic delay, etc. Accurately calculating the delay described by the first data delay set helps ensure that the output signal arrives at the receiver at the expected time.

[0074] The second data delay set includes various Corresponding data latency , yes arrive The second data delay set covers the wiring and logic delays between the input port and the second register input. This second data delay set is crucial for ensuring that data is sampled while meeting setup and hold time requirements.

[0075] The transmission delay set includes each transmission delay ,Should yes The rising edge of the clock The internal propagation delay of the output is the time required from the arrival of the clock edge to the stable output of the first register. The propagation delay set is one of the key timing parameters of the first register, directly affecting the stability and reliability of the output signal.

[0076] The establishment of duration sets includes various Establishment time The setup duration set refers to the minimum time that data must remain stable in each second register before the clock edge arrives. This definition is a key timing constraint to ensure that data can be sampled correctly.

[0077] The margin set includes each Establishment time margin This margin refers to the amount of space that ensures the second register can still operate reliably under actual timing conditions. The larger the margin, the higher the robustness.

[0078] The duration set includes various Duration of retention The hold duration set defines the minimum time that the data in each second register must remain unchanged after the clock edge to prevent sampling errors caused by data changes near the clock edge.

[0079] clock cycle Used to drive and sample signals at the ports of the test platform. This determines the overall operating frequency of the test platform and serves as the basic parameter for timing modeling.

[0080] In this embodiment, the timing parameter set fully considers the delay from the target clock source to the clock port of the target system, the transmission delay from the rising edge of the register sampling clock to the output terminal, the data delay from the rising edge of the register clock to the signal output port, the setup time of register sampling, the hold time of the register, etc., covering more details. While enriching the timing parameters, it also improves the comprehensiveness and accuracy of the timing parameters, thereby improving the accuracy of the simulation delay determined according to the timing parameter set, and thus ensuring that the test platform can accurately and stably sample the output signal of the target system with which it interacts.

[0081] In some implementations, when the simulated delay includes the clock delay corresponding to the second clock port, the target timing parameter includes a first target timing parameter; the test platform also includes at least one second signal input port; the step S32, which determines the simulated delay based on the parameter value of the target timing parameter, includes steps S321 and S322, wherein: Step S321: For each second signal input port, determine the delay corresponding to the second signal input port based on the parameter value of the first target timing parameter.

[0082] Here, the second signal input port refers to the interface in the test platform used to receive signals from external modules or the system. The function of the second signal input port is to introduce signals from the actual circuit into the test platform for simulation purposes. By setting multiple second signal input ports, independent control and measurement of multiple signals can be achieved, improving test accuracy.

[0083] The first target timing parameters are a set of key timing metrics specifically defined for the second clock port in the simulation delay. These parameters directly affect whether the test platform can correctly sample the output signal of the target system, thus ensuring the accuracy of the simulation.

[0084] Should The corresponding delay can be determined in any suitable way.

[0085] In some implementations, for each The parameter values ​​of each first target timing parameter and each... can be pre-established. The corresponding relationships between delays can be established, and based on these relationships, parameter values ​​that match the timing parameters of the first target can be obtained. The corresponding delay.

[0086] In some implementations, since different timing models or different interaction scenarios use different first target timing parameters, therefore: When the target time series model is model A, the first target time series parameters include: , ,each ,each and each At this point, it can be based on , ,each ,each and each Determine each The corresponding delay.

[0087] In some implementations, when the first interaction scenario or target temporal model is model A, the Corresponding delay The determination method may include, but is not limited to, the difference between the first difference and the second difference, or the weighted sum of these differences. The first difference refers to... and The difference between them, the second difference refers to , and The difference between them. In implementation, those skilled in the art can determine this independently based on actual needs. The method of determining the method is not limited in the embodiments disclosed herein.

[0088] In some implementations, the number of... can be determined by the following formula (3-1). indivual Corresponding delay ,Right now: (3-1); in, Indicates the first indivual The second difference, Indicates the first indivual The first difference.

[0089] When the target time series model is model B, the first target time series parameters include: ,each ,each and each At this point, it can be based on ,each ,each and each Determine each The corresponding delay.

[0090] In some implementations, when the second interaction scenario or target temporal model is model B, the Corresponding delay The determination method may include, but is not limited to, the difference between the second sum and the third difference, or the weighted sum of these differences. The second sum refers to... and The sum between them, the third difference refers to and The difference between them. In implementation, those skilled in the art can determine this independently based on actual needs. The method of determining the method is not limited in the embodiments disclosed herein.

[0091] In some implementations, the number of... can be determined by the following formula (3-2). indivual Corresponding delay ,Right now: (3-2); in, Indicates the first indivual The second sum, Indicates the first indivual The third difference.

[0092] Step S322: If the delay corresponding to at least one second signal input port does not meet the first preset condition, determine the clock delay corresponding to the second clock port based on the delay corresponding to each second signal input port.

[0093] Here, the first preset condition can be any suitable condition, such as being greater than a first preset value. The first preset value can be any suitable value, such as 0, 0.01, etc.

[0094] In implementation, if at least one If the corresponding delay does not meet the first preset condition, it indicates that the signal output by the target system may not be accurately sampled by the test platform. In this case, the test platform's... The output clock signal needs to be delayed.

[0095] The methods for determining the clock delay corresponding to the second clock port may include, but are not limited to, the first target delay, a weighted average of the first target delay, the first sum, and a weighted average of the first sum. The first target delay is determined based on each... The corresponding delay is determined. The first sum refers to the sum between the first target delay and the first target value. The first target value can be any suitable small value, such as 0.1, 0.15, etc. In implementation, those skilled in the art can independently determine the method for determining the clock delay corresponding to the second clock port according to actual needs, and the embodiments disclosed herein are not limited thereto.

[0096] Understandably, in each The corresponding delays all meet the first preset condition, indicating that the signal output by the target system can be accurately sampled by the test platform. At this time, The output clock signal does not need to be delayed.

[0097] In this embodiment, by introducing a first target timing parameter into the simulated delay and determining whether the delay of each signal input port of the test platform meets specific conditions, and then deciding whether to adjust the master clock delay, a dynamic optimization timing processing mechanism is realized. This mechanism can automatically adjust the clock delay in complex timing environments to ensure the stability of signal interaction between the test platform and the target system, and to ensure that the signal output of the last stage register of the target system is correctly and stably sampled by the test platform, thereby improving the reliability and simulation efficiency of the test platform.

[0098] In some implementations, when the target timing model is a first timing model, the first target timing parameters include the clock period of the second clock port, the clock port delay, a first clock delay set, a first data delay set, and a transmission delay set; the step S321, which determines the delay corresponding to the second signal input port based on the parameter values ​​of the first target timing parameters, includes steps S3211 to S3213, wherein: Step S3211: Determine the first difference between the clock port delay and the clock delay corresponding to the first target port in the first clock delay set; the first target port is the first signal output port connected to the second signal input port.

[0099] Here, the first timing model is applicable to the first interaction scenario. The first timing model considers multiple key delay parameters, which improves the accuracy of delay information calculation and avoids the errors caused by relying solely on the maximum delay or rough estimation in traditional methods.

[0100] The first target port is typically a first signal output port, whose output signal is received by the second signal input port. Since the signal transmission is affected by various factors, such as path length and register response time, a detailed analysis of the delay at the first target port is necessary to ensure that the test platform can correctly sample the output signal from the first target port.

[0101] The first difference refers to and The difference between them. The first difference reflects the additional clock delay from the register to the module port, which helps determine whether the clock sampling position of the test platform needs to be adjusted.

[0102] In some implementations, the number of... can be determined by the following formula (3-3). indivual First difference ,Right now: (3-3); in, Indicates the first indivual The corresponding clock delay, the first indivual and the indivual Connected, This indicates clock port delay.

[0103] Step S3212: Determine the second difference between the clock period of the second clock port, the data delay corresponding to the first target port in the first data delay set, and the transmission delay of the first register driving the first target port in the transmission delay set.

[0104] Here, the second difference refers to , and The difference between the two values. The second difference is used to evaluate the total delay time required for the data signal to travel from the register to the module port, including the delay of the data path and the transmission path.

[0105] In some implementations, the number of... can be determined by the following formula (3-4). indivual The second difference ,Right now: (3-4); in, express clock cycle, Indicates the first indivual The corresponding data latency, Indicates the driver number indivual of The transmission delay, the first indivual and the indivual Connected.

[0106] Step S3213: Determine the delay corresponding to the second signal input port based on the first difference and the second difference.

[0107] here, The corresponding delay can be determined in ways including, but not limited to, the difference between the first and second differences, or a weighted average of these differences. For example, the difference can be used as the... The corresponding delay. In implementation, the delay can be determined using the formula (3-1) above. indivual Corresponding delay .

[0108] During implementation, by comparing the first difference with the second difference, it is possible to more accurately determine whether the test platform needs to add additional delay to ensure the correctness of sampling.

[0109] In the embodiments of this disclosure, the first timing model combines multiple factors such as clock cycle, clock delay, data delay and transmission delay for comprehensive calculation, which can more accurately predict the delay performance of the signal input port. It fully considers each link in the signal path and realizes refined modeling of the interface signal delay of the test platform. This can effectively reduce sampling errors caused by inaccurate delay settings, thereby improving the accuracy of post-simulation and the efficiency of chip verification.

[0110] In some implementations, when the target timing model is a second timing model, the first target timing parameters include clock port delay, a second clock delay set, a setup duration set, and a margin set; the step S321, which determines the delay corresponding to the second signal input port based on the parameter values ​​of the first target timing parameters, includes steps S3214 to S3216, wherein: Step S3214: Determine the second sum between the setup duration of the second register driven by the third target port in the setup duration set and the setup duration margin of the second register driven by the third target port in the margin set; wherein, the third target port is the first signal input port connected to the second signal input port.

[0111] Here, the second timing model corresponds to the scenario where the test platform takes over the subsystem, in which case the test platform replaces the functions that should originally be performed by the hardware subsystem. The second timing model is more suitable for verifying whether the test platform can accurately simulate hardware behavior and maintain timing consistency.

[0112] The third target port refers to the upstream port that has a direct connection to the second signal input port. Typically, the third target port is responsible for providing the input signal to the second register. Therefore, during the modeling process, the timing characteristics of the third target port will directly affect the sampling behavior of the second register.

[0113] The second sum refers to and The sum of the values ​​between them. In some implementations, the value of the first can be determined by the following formulas (3-5). indivual The second sum ,Right now: (3-5); in, Indicates the first indivual Driven The establishment time Indicates the first indivual Driven The establishment time margin, the first indivual and the indivual Connected.

[0114] Step S3215: Determine the third difference between the clock port delay and the clock delay corresponding to the third target port in the second clock delay set.

[0115] Here, the third difference refers to and The third difference reflects the time deviation between the master clock used by the test platform and the actual clock signal entering the register, which helps to determine whether there is a clock offset problem.

[0116] In some implementations, the number of... can be determined by the following formulas (3-6). indivual The third difference ,Right now: (3-6); in, Indicates the first indivual The corresponding clock delay, the first indivual and the indivual Connected, This indicates clock port delay.

[0117] Step S3216: Determine the delay corresponding to the second signal input port based on the second sum and the third difference.

[0118] here, The corresponding delay can be determined in ways including, but not limited to, the difference between the second sum and the third difference, or a weighted average of those differences. For example, this difference can be used as the... The corresponding delay. In implementation, the delay can be determined using the formula (3-2) above. indivual Corresponding delay .

[0119] In implementation, the second sum and the third difference are combined to obtain the delay corresponding to the second signal input port. This not only takes into account the setup time and margin of the register, but also integrates the delay difference of the clock path, thereby achieving high-precision modeling of the delay information of the second signal input port.

[0120] In this embodiment, factors such as setup time, margin, and clock delay are introduced into the second timing model to construct a more refined timing model. This model can more comprehensively capture the timing relationship between the test platform and the target system, and can more precisely evaluate the delay effect of the signal input port, thereby significantly improving the stability and efficiency of post-simulation.

[0121] In some implementations, determining the clock delay corresponding to the second clock port based on the delay corresponding to each second signal input port in step S322 includes steps S3221 and S3222, wherein: Step S3221: Determine the first target delay based on the delay corresponding to each second signal input port.

[0122] Here, the first target delay is an abstract expression of the delay corresponding to multiple second signal input ports, which is used for subsequent more accurate clock delay calculations.

[0123] The method for determining the first target delay may include, but is not limited to, the inverse of the delay corresponding to a certain second signal input port, a weighted sum of the inverses of the delay corresponding to a certain second signal input port, the mean of the inverses of the delays corresponding to all second signal input ports, or the root mean square deviation of the inverses of the delays corresponding to all second signal input ports. For example, the inverse of the delay corresponding to the largest second signal input port may be used as the first target delay.

[0124] In some implementations, the first target delay can be determined using the following formulas (3-7). ,Right now: (3-7); in, Indicates the first indivual The corresponding delay. In implementation, for the first interaction scenario, it can be determined using the above formula (3-1). For the second interaction scenario, it can be determined using the above formula (3-2). .

[0125] In some implementations, in the case of multi-bit signals, the largest delay among all bits may be selected as the first target delay to ensure that all bits can be sampled correctly. This is more reasonable than the prior art method of using the maximum delay to compensate for all bits, because the first target delay avoids the performance loss caused by overcompensation.

[0126] Step S3222: Determine the clock delay corresponding to the second clock port based on the first sum value between the first target delay and the first target value.

[0127] Here, the first target value can be a preset safety value (such as 0.1 times the clock cycle). The first target value can be any suitable small safety value, such as 0.1, 0.15, etc. It can also be a value that is dynamically adjusted according to specific process corners or design constraints. For example, in some scenarios, the first target value can be automatically adjusted according to the margin parameters under different corners, thereby ensuring that timing requirements are still met in the worst case.

[0128] The method for determining the clock delay corresponding to the second clock port may include, but is not limited to, the first sum value, a weighted sum of the first sum value, etc. For example, the first sum value can be used as the clock delay corresponding to the second clock port.

[0129] In some implementations, the clock delay corresponding to the second clock port can be determined using the following formulas (3-8). ,Right now: (3-8); in, This indicates that the first objective is delayed. This represents the first target value.

[0130] There is a logical relationship between the first target delay and the first target value. Together, they determine the clock delay setting of the test platform interface. This approach is more scientific and accurate than simply using a fixed safety value for rough estimation in existing technologies. The first target delay not only considers the actual delay on the signal path but also incorporates system-level timing margins, thereby improving the accuracy of the clock delay.

[0131] In this embodiment of the disclosure, by comprehensively processing the delays corresponding to each second signal input port to generate a first target delay, and further combining the first target value to derive a suitable clock delay value, the accuracy of the clock delay can be improved, ensuring that timing requirements can still be met in the worst case, thereby improving the stability of the interaction between the test platform and the target system.

[0132] In some implementations, when the analog delay includes the signal delay corresponding to at least one second signal output port, the target timing parameter includes a second target timing parameter; the step S32, which determines the analog delay based on the parameter value of the target timing parameter, includes step S323, wherein: Step S323: For each second signal output port, determine the delay corresponding to the second signal output port based on the second target timing parameters, and determine the signal delay corresponding to the second signal output port based on the delay corresponding to the second signal output port.

[0133] Here, since each second signal output port may have different timing characteristics, it is necessary to calculate the signal delay corresponding to each second signal output port separately.

[0134] The second target timing parameters typically include key metrics such as data delay and transmission delay from the register to the second signal output port. The second target timing parameters differ somewhat from the first target timing parameters. By employing the second target timing parameters, which provide a more refined model specifically for each second signal output port, the differences between various second signal output ports can be more accurately reflected, thereby improving the accuracy and robustness of the overall timing model. Simultaneously, by calculating the delay value for each second signal output port individually, it ensures that the signal from each second signal output port is correctly sampled during simulation, thus avoiding the problem of partial signal sampling failure caused by a uniform delay setting on the test platform.

[0135] Should The corresponding delay can be determined in any suitable way. The second target timing parameters include those used to determine each... The corresponding timing parameters for the delay.

[0136] In some implementations, for each The parameter values ​​of each second target timing parameter and each... can be pre-established. The correspondence between the corresponding delays can be established, and based on this correspondence, the parameter values ​​that are adapted to the timing parameters of the second target can be obtained. The corresponding delay.

[0137] In some implementations, since different timing models or different interaction scenarios use different timing parameters for the second target, therefore: When the target time series model is model A, the second target time series parameters may include: ,each ,each ,each At least one of them.

[0138] Corresponding delay The determination method may include, but is not limited to, the sum of the fourth and fifth differences, or a weighted sum of these differences. The fourth difference refers to... and The difference between them, the fifth difference refers to and The difference between them. In implementation, those skilled in the art can determine this independently based on actual needs. The method of determining the method is not limited in the embodiments disclosed herein.

[0139] In some implementations, the number of... can be determined by the following formulas (3-9). indivual Corresponding delay ,Right now: (3-9); in, Indicates the first indivual The fourth difference, Indicates the first indivual The fifth difference.

[0140] When the target time series model is model B, the second target time series parameter set may include ,each ,each ,each At least one of them.

[0141] Corresponding delay The determination method may include, but is not limited to, the sum between the sixth difference and the third sum, or the weighted sum of that sum. The sixth difference refers to... and The difference between them, the third sum refers to and The sum of the values. In implementation, those skilled in the art can determine this independently based on actual needs. The method of determining the method is not limited in the embodiments disclosed herein.

[0142] In some implementations, the number of... can be determined by the following formula (3-10). indivual Corresponding delay ,Right now: (3-10); in, Indicates the first indivual The sixth difference, Indicates the first indivual The third sum.

[0143] Should Corresponding signal delay The method for determining this can be any suitable method. In some implementations, it can be directly... As In some implementations, it can be based on Determine the second preset condition For example, if If the second preset condition is met, then As Conversely, if If the second preset condition is not met, then the second target value representing the absence of delay will be used as... .

[0144] In this embodiment, by introducing a second target timing parameter and calculating the signal delay of each second signal output port separately, the timing modeling accuracy in multi-port scenarios can be effectively improved to achieve fine compensation. Furthermore, the error caused by setting a uniform delay can be avoided, ensuring that the signal of each second signal output port can be correctly sampled in the simulation. This further optimizes the signal interaction behavior between the test platform and the target system and helps to discover potential timing problems.

[0145] In some implementations, when the target timing model is a first timing model, the second target timing parameters include clock port delay, a second clock delay set, a hold duration set, and a second data delay set; the step S323, which determines the delay corresponding to the second signal output port based on the second target timing parameters, includes steps S3231 to S3233, wherein: Step S3231: Determine the fourth difference between the clock delay of the clock port and the clock delay of the second target port in the second clock delay set; wherein, the second target port is the first signal input port connected to the second signal output port.

[0146] Here, the first timing model is a specific timing modeling method for the interaction scenario between the test platform and hardware subsystem modules. The first timing model considers the delay characteristics of the test platform interface signals on different paths and performs accurate calculations by introducing several key timing parameters.

[0147] Since test platform interfaces typically consist of multiple signals, each potentially connected to different registers or logic units, precise modeling and compensation of the delay for each signal path are necessary to ensure the test platform can correctly sample signals from the hardware subsystem.

[0148] The second target port is a certain first signal input port, and the output signal of the first signal input port is received by the second signal output port.

[0149] The fourth difference refers to and The fourth difference reflects the relative position of the test platform and the register on the time axis. This fourth difference determines whether the clock phase needs to be adjusted to meet sampling requirements. If the fourth difference is less than zero, it indicates that the test platform's clock arrives earlier than the register's clock, which may lead to sampling errors; in this case, a delay needs to be added.

[0150] In some implementations, the number of... can be determined by the following formula (3-11). indivual The fourth difference ,Right now: (3-11); in, Indicates the first indivual The corresponding clock delay, the first indivual and the indivual Connected, This indicates clock port delay.

[0151] Step S3232: Determine the fifth difference between the data delay corresponding to the second target port in the second data delay set and the hold duration of the second register driven by the second target port in the hold duration set.

[0152] Here, the fifth difference refers to and The fifth difference is used to determine whether the data can be stably transmitted to the input of the drive register before the clock edge arrives, thus meeting the setup time requirements. If the fifth difference is less than zero, it means that the data arrives at the register input later than the register's hold time requirement, and the data path delay also needs to be adjusted.

[0153] In some implementations, the number of... can be determined by the following formula (3-12). indivual The fifth difference ,Right now: (3-12); in, Indicates the first indivual Driven Duration of retention Indicates the first indivual The corresponding data delay.

[0154] Step S3233: Based on the fourth and fifth differences, determine the delay corresponding to the second signal output port.

[0155] here, The corresponding delay can be determined in ways including, but not limited to, the sum of the fourth and fifth differences, or a weighted sum of those differences. For example, the sum can be used as the... The corresponding delay. In implementation, the delay can be determined using the formula (3-9) above. indivual Corresponding delay .

[0156] During implementation, by taking both differences into account, it can be automatically determined whether additional delay compensation needs to be added to the signal of the test platform to ensure the correctness of the sampling.

[0157] In the embodiments of this disclosure, by combining key parameters such as clock delay, data delay, and hold time in the first timing model, the delay performance of the signal output port can be evaluated more comprehensively, which helps to discover potential timing conflicts and thus improve the stability and accuracy of post-simulation.

[0158] In some implementations, when the target timing model is a second timing model, the second target timing parameters include clock port delay, a first clock delay set, a first data delay set, and a transmission delay set; the step S323, which determines the delay corresponding to the second signal output port based on the second target timing parameters, includes steps S3234 to S3236, wherein: Step S3234: Determine the sixth difference between the clock port delay and the clock delay corresponding to the fourth target port in the first clock delay set; wherein, the fourth target port is the first signal output port connected to the second signal output port.

[0159] Here, the second timing model is adapted to the second interaction scenario. The second timing model considers multiple key delay parameters, which improves the accuracy of delay information calculation.

[0160] The fourth target port is the first signal output port connected to the second signal output port. The timing characteristics of the fourth target port will directly affect the behavior of the second signal output port.

[0161] The sixth difference refers to and The sixth difference reflects the time offset between the fourth target port and the master clock source. The sixth difference is a key indicator for evaluating whether the signal can be correctly sampled in the next cycle.

[0162] In some implementations, the number of... can be determined by the following formula (3-13). indivual The sixth difference ,Right now: (3-13); in, Indicates the first indivual The corresponding clock delay, the first indivual and the indivual Connected, This indicates clock port delay.

[0163] Step S3235: Determine the third sum between the data delay corresponding to the fourth target port in the first data delay set and the transmission delay of the first register driving the fourth target port in the transmission delay set.

[0164] Here, the third sum refers to and The sum of the values ​​between them, in some implementations, can be determined by the following formula (3-14). indivual The third sum ,Right now: (3-14); in, Indicates the first indivual Driven Transmission delay, Indicates the first indivual The corresponding data delay.

[0165] Step S3236: Determine the delay corresponding to the second signal output port based on the sixth difference and the third sum.

[0166] here, The corresponding delay can be determined in ways including, but not limited to, the sum between the sixth difference and the third sum, or a weighted sum of that sum. For example, this sum can be used as the... The corresponding delay. In implementation, the delay can be determined using the formula (3-11) above. indivual Corresponding delay .

[0167] During implementation, the path delay and signal propagation characteristics between the fourth target port and the second signal output port were fully considered by combining the sixth difference and the third sum to ensure the accuracy of the simulation.

[0168] In this embodiment of the disclosure, by combining parameters such as clock delay, data delay, and transmission delay in the second timing model, the delay performance of the signal output port can be evaluated more accurately, improving the accuracy of post-simulation and reducing debugging time and resource consumption.

[0169] In some implementations, determining the signal delay corresponding to the second signal output port based on the delay corresponding to the second signal output port in step S323 includes step S3237, wherein: Step S3237: When the target timing model is the first timing model and the delay corresponding to the second signal output port meets the second preset condition, or when the target timing model is the second timing model, the delay corresponding to the second signal output port is taken as the signal delay corresponding to the second signal output port.

[0170] Here, the second preset condition can be any suitable condition, such as being greater than a second preset value. This second preset value can be any suitable value, such as 0, 0.01, etc. The second preset condition typically refers to the fact that, in model A, the delay margin of the test platform's input signal relative to the clock edge is greater than zero. When the second preset condition is met, the test platform does not need to add any additional delay because the input signal already meets the sampling condition. If the second preset condition is not met, then the test platform needs to adjust the delay to ensure the correctness of the sampling.

[0171] When that Corresponding delay When the value exceeds the second preset value, the signal representing the output of the target system may not be accurately sampled by the test platform. In this case, the If a delay is needed for the test platform to accurately sample the data, then... As the Corresponding signal delay .

[0172] If the target timing model is the first timing model and the delay corresponding to the second signal output port does not meet the second preset condition, the second target value is used as the signal delay corresponding to the second signal output port. The second target value can be any suitable value that represents the absence of delay. For example, the second target value can be 0, a negative number, etc.

[0173] In this embodiment, by setting reasonable judgment conditions, the delay value of the signal output port can be quickly determined, thereby simplifying the model calculation process, reducing unnecessary delay compensation operations, improving the running efficiency of the model while ensuring accuracy, and thus reducing the number of iterations and debugging time in the simulation process, and accelerating the overall progress of post-simulation.

[0174] The following example uses the target system as the hardware subsystem of a SoC and the test platform as the stimulus generator to illustrate the post-simulation method provided in this disclosure.

[0175] In the verification process of integrated circuits, GLS is a very important step. By back-annotating the delay information of gate-level circuits into the netlist composed of basic gate cells in the form of SDF (Standard Delay File), it is possible to discover potential constraints and timing problems in the design.

[0176] As the scale of SOC chips increases, the simulation scale and simulation machine resources also increase dramatically, resulting in longer simulation times. To accelerate post-simulation, GLS timing post-simulation typically uses an excitation generator instead of a real excitation generator to send excitation signals and samples the output of the hardware subsystem. Since the excitation generator does not carry delay information, there are generally no problems when performing pure netlist simulation as the gate-level circuits within the netlist do not back-annotate timing information. However, various sampling problems are often encountered when performing GLS timing post-simulation, such as failure to sample signals or signal sampling errors.

[0177] Currently, the sampling problem is mainly solved in the following two ways: Method 1: Manually adjusting the delay parameters generally requires analysis and debugging in conjunction with GLS simulation waveforms. By observing and manually adjusting the clock delay of the excitation generator's interface, the correctness of sampling during the interaction between the excitation generator and the hardware subsystem can be ensured. This method is suitable for low clock frequencies, but it consumes a lot of debugging time, requires multiple iterations, and involves finding multiple sets of parameters for debugging. Not only does it fail to ensure normal sampling under different corners (process corners), but it also reduces simulation speed and efficiency, resulting in high simulation costs.

[0178] Method 2: Rough delay estimation. Roughly estimate the delay information of the excitation generator's interface and back-annotate it to the corresponding connection file. Figure 4A This is a schematic diagram illustrating the determination of delay information in a related art according to an embodiment of this disclosure, such as... Figure 4A As shown, the hardware subsystem 401 and the excitation generator 402 are connected via a port. In implementation, this is achieved by delaying the clock source to the internal flip-flop DFF. and clock cycle A comparison is used to determine whether the stimulus generator can sample the output signal of the hardware subsystem it interacts with; that is: through... Using this method to determine whether a delay needs to be added, and adding a delay of 0.1 times the clock cycle as a safety value, presents the following problems: 1) The delay information is not accurate enough and does not fully account for the delay from the rising edge of the register clock to the register output. Data delay between register output and the output port of the hardware subsystem Register setup time Register hold duration Even so, the aforementioned sampling problems will still exist; 2) A security value needs to be added; 3) The delay calculation and compensation for the multi-bit signals output by the hardware subsystem were not performed accurately; 4) The impact of the interaction between the stimulus generator and the hardware subsystem on the delay information was not considered.

[0179] To address the problems of the two methods mentioned above, this disclosure provides a post-simulation method. First, a corresponding timing model is established based on the interaction scenario between the excitation generator and the hardware subsystem. Then, the delay information of the excitation generator's interface is automatically generated based on the timing model and a unified delay description file containing a set of timing parameters. This information is then automatically back-annotated to the connection file between the excitation generator and the hardware subsystem. Finally, the connection file is ported to the GLS timing post-simulation environment for post-simulation. First, because the timing parameter set includes various timing parameters, the impact of these timing parameters and interaction scenarios on sampling is fully considered, resulting in a more accurate timing model. Second, by defining a unified and richer delay description file, which includes all the timing parameters needed to build the timing model for various interaction scenarios, a more accurate timing model can be built. Furthermore, extracting the timing parameter set corresponding to each process corner according to the delay description file not only ensures the speed and accuracy of the timing parameter set but also facilitates subsequent reuse. Third, because the delay information performs fine-grained compensation for each bit of signal, the robustness of the model is greatly improved. Finally, the entire process—from extracting the timing parameter set from the delay file to parsing the delay file to generate delay information and then back-annotating the delay information—is fully automated, further accelerating simulation time, improving simulation efficiency, and reducing iteration cycles. This facilitates the maintenance, modification, and subsequent reuse of the GLS timing simulation environment.

[0180] Figure 4B Schematic diagram four illustrates the implementation flow of a post-simulation method provided in this embodiment of the disclosure, as shown below. Figure 4B As shown, the post-simulation method includes steps S401 to S405, wherein: Step S401: Determine the interaction scenario between the hardware subsystem and the stimulus generator based on the location where the stimulus generator is attached; Here, the interaction scenario can include either the first interaction scenario or the second interaction scenario.

[0181] Figure 4C This is a schematic diagram of a first interactive scenario provided in an embodiment of the present disclosure, such as... Figure 4C As shown, the hardware subsystem 411 and the excitation generator 412 are connected via an interface. The excitation generator 412 interacts with the hardware subsystem 411 and is connected to the port of the hardware subsystem 411, wherein: The first clock port of hardware subsystem 411 With the second clock port of the excitation generator 412 Connected to the first clock port Upon receiving the clock signal from the target clock source 413, the excitation generator 412 uses the clock as the first clock port of the hardware subsystem 411. The clock; The first signal input port of hardware subsystem 411 With the second signal output port of the excitation generator 412 Connected; The first signal output port of hardware subsystem 411 The second signal input port of the excitation generator 412 Connected.

[0182] Figure 4D This is a schematic diagram of a second interactive scenario provided in an embodiment of the present disclosure, such as... Figure 4D As shown, the hardware subsystem 421 and the excitation generator 422 are connected via an interface. The excitation generator 422 will take over and replace the hardware subsystem 421 in its operation, wherein: The first clock port of hardware subsystem 421 With the second clock port of the excitation generator 422 Connected to the first clock port Receive the clock signal from the target clock source 423; The first signal input port of hardware subsystem 421 The second signal input port of the excitation generator 422 Connected; The first signal output port of hardware subsystem 421 With the second signal output port of the excitation generator 422 Connected.

[0183] Step S402: Obtain the timing parameter set corresponding to the target process corner based on the delay description file; Step S403: Input the timing parameter set corresponding to the target process angle into the timing model corresponding to the interaction scenario between the hardware subsystem and the excitation generator to obtain the delay information of the excitation generator port under the target process angle (corresponding to the aforementioned simulation delay). Here, the delay information of the excitation generator's port includes Corresponding clock delay and at least one Corresponding signal delay .

[0184] exist Figure 4C In the first interactive scenario shown: For the direction from hardware subsystem 411 to excitation generator 412, to ensure that the signal output by the last stage register in hardware subsystem 411 can be sampled by excitation generator 412, the following judgment needs to be performed: (1) If all Corresponding delay If the value is greater than 0 (corresponding to the aforementioned first preset condition), then the clock signal of the excitation generator does not need to be delayed; (2) If at least one Corresponding delay If the value is less than 0, the clock signal of the excitation generator needs to be delayed. In implementation, this can be determined according to the above formula (3-8). .

[0185] For the direction from excitation generator 412 to hardware subsystem 411, it must be ensured that the signal output by excitation generator 412 is sampled by hardware subsystem 411. For any one The following judgment needs to be performed: (1) If The corresponding delay is less than 0 (corresponding to the aforementioned failure to meet the second preset condition), then the The output signal can be sampled by the hardware subsystem 411. The output signal does not require delay; (2) If If the corresponding delay is greater than 0, then the The output signal cannot be sampled by hardware subsystem 411. At this time, The output signal needs to be delayed; during implementation, it can be... The corresponding delay is used as the .

[0186] Figure 4E This is a timing diagram of a first interactive scenario provided by an embodiment of the present disclosure, such as... Figure 4E As shown, by delaying the signal at the port of the excitation generator according to this simulated delay, it can be ensured that the signal can be sampled correctly and stably.

[0187] exist Figure 4D In the second interactive scenario shown: Regarding the output direction of hardware subsystem 411, the timing within hardware subsystem 411 must ensure that the delay of the output signal from the excitation generator 412 interface is sampled by the subsequent register interacting with hardware subsystem 411. This requires that the output signal of excitation generator 412 perfectly match the timing delay of the output signal from hardware subsystem 411. Therefore, the signal output by excitation generator 412 needs to be delayed before being sampled. In implementation, this can be determined using the formula (3-10) above. As the first indivual Corresponding signal delay .

[0188] To ensure that the excitation generator 412 can sample correctly, the following judgment needs to be performed regarding the input direction of the hardware subsystem 411: (1) If all Corresponding delay If the value is greater than 0 (corresponding to the aforementioned first preset condition), then the clock signal of the excitation generator does not need to be delayed; (2) If at least one Corresponding delay If the value is less than 0, the clock signal of the excitation generator needs to be delayed. In implementation, this can be determined according to the above formula (3-8). .

[0189] Figure 4F This is a timing diagram illustrating a second interactive scenario provided in an embodiment of the present disclosure, such as... Figure 4F As shown, the signal at the port of the excitation generator is delayed according to this model to ensure that the excitation generator 412's signal is delayed before the next clock edge arrives. The corresponding delay is greater than 0; otherwise, point m will arrive after the next sampling clock of the excitation generator 412, thus ensuring that the signal can be sampled correctly and stably.

[0190] Step S404: Based on the delay information of the excitation generator port under the target process angle, back-annotate the first connection file representing the connection relationship between the hardware subsystem and the excitation generator to obtain the second connection file; To further enhance automation, the timing parameter set, the first connection file, and the interaction scenario can be input into the delay back-annotation model to obtain the second connection file. This delay back-annotation model can be any suitable model capable of performing this function. In implementation, the delay back-annotation model first determines the model delay based on the timing parameter set and the interaction scenario, then back-annotates the model delay to the first connection file to obtain the second connection file.

[0191] Step S405: Perform post-simulation of the hardware subsystem according to the second connection file.

[0192] Based on the above embodiments, this disclosure provides a post-simulation device. Figure 5 This is a schematic diagram of the composition structure of a post-simulation device provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the device 50 includes a determination module 51, a marking module 52, and a post-simulation module 53, wherein: The determining module 51 is used to obtain the simulated delay when the test platform and the target system interact with signals using the target timing model; wherein, the target timing model is determined based on the current interaction scenario between the test platform and the target system; The marking module 52 is used to mark the first connection file according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file adds the simulated delay to the first connection file; The post-simulation module 53 is used to perform post-simulation of the target system based on the second linker file.

[0193] In some implementations, the determining module 51 is further configured to determine the target timing model based on the current interaction scenario between the test platform and the target system; wherein, under different interaction scenarios, the interaction path between the test platform and the target system is at least partially different.

[0194] In some implementations, the current interaction scenario includes: a first interaction scenario, wherein the first interaction scenario characterization test platform is located outside the target system; or, a second interaction scenario, wherein the second interaction scenario characterization test platform is located inside the target system.

[0195] In some embodiments, the apparatus further includes an acquisition module for acquiring parameter values ​​of multiple timing parameters in a timing parameter set at a target process angle; wherein the timing parameters have different parameter values ​​at different process angles; the determination module 51 is further configured to determine a target timing parameter from the multiple timing parameters in the timing parameter set, wherein different timing models use at least some different timing parameters; and determine a simulation delay based on the parameter value of the target timing parameter, wherein the simulation delay includes at least one of the following: clock delay corresponding to a second clock port of the test platform, and signal delay corresponding to at least one second signal output port of the test platform.

[0196] In some implementations, the target system includes a first clock port, at least one first signal output port, a first register driving each first signal output port, at least one first signal input port, and a second register driven by each first signal input port; the test platform includes a second clock port; the timing parameter set includes at least one of the following: clock port delay, characterizing the delay from the target clock source to the first clock port; a first clock delay set, including the clock delay corresponding to each first signal output port, wherein the clock delay corresponding to the first signal output port is the clock delay from the target clock source to the corresponding first register driving the first signal output port; a first data delay set, including the data delay corresponding to each first signal output port, wherein the data delay corresponding to the first signal output port is the data delay from the first register driving the first signal output port to the first signal output port; and transmission delay. The set includes: a first clock delay set, comprising the transmission delay of the first register driving the first signal output port; a second clock delay set, comprising the clock delay corresponding to each first signal input port, wherein the clock delay corresponding to the first signal input port is the clock delay from the target clock source to the second register driven by the first signal input port; a setup duration set, comprising the setup duration of the second register driven by each first signal input port; a hold duration set, comprising the hold duration of the second register driven by each first signal input port; a second data delay set, comprising the data delay corresponding to each first signal input port, wherein the data delay corresponding to the first signal input port is the data delay from the first signal input port to the second register driven by the first signal input port; a margin set, comprising the setup duration margin of the second register driven by each first signal input port based on the actual timing; and the clock cycle of the second clock port of the test platform.

[0197] In some implementations, when the simulated delay includes the clock delay corresponding to the second clock port, the target timing parameter includes a first target timing parameter; the test platform also includes at least one second signal input port; the determining module 51 is further configured to: for each second signal input port, determine the delay corresponding to the second signal input port based on the parameter value of the first target timing parameter; and if the delay corresponding to at least one second signal input port does not meet the first preset condition, determine the clock delay corresponding to the second clock port based on the delay corresponding to each second signal input port.

[0198] In some implementations, the determining module 51 is further configured to: determine a first target delay based on the delay corresponding to each second signal input port; and determine the clock delay corresponding to the second clock port based on a first sum between the first target delay and the first target value.

[0199] In some implementations, when the target timing model is a first timing model, the first target timing parameters include the clock period of the second clock port, the clock port delay, the first clock delay set, the first data delay set, and the transmission delay set. The determining module 51 is further configured to: determine a first difference between the clock port delay and the clock delay corresponding to the first target port in the first clock delay set, wherein the first target port is a first signal output port connected to the second signal input port; determine a second difference between the clock period of the second clock port, the data delay corresponding to the first target port in the first data delay set, and the transmission delay of the first register driving the first target port in the transmission delay set; and determine the delay corresponding to the second signal input port based on the first difference and the second difference.

[0200] In some implementations, when the target timing model is a second timing model, the first target timing parameters include clock port delay, a second clock delay set, a setup duration set, and a margin set; the determining module 51 is further configured to determine a second sum between the setup duration of the second register driven by the third target port in the setup duration set and the setup duration margin of the second register driven by the third target port in the margin set; wherein, the third target port is a first signal input port connected to the second signal input port; determine a third difference between the clock port delay and the clock delay corresponding to the third target port in the second clock delay set; and determine the delay corresponding to the second signal input port based on the second sum and the third difference.

[0201] In some implementations, where the simulated delay includes the signal delay corresponding to at least one second signal output port, the target timing parameter includes a second target timing parameter; the determining module 51 is further configured to, for each second signal output port, determine the delay corresponding to the second signal output port based on the second target timing parameter, and determine the signal delay corresponding to the second signal output port based on the delay corresponding to the second signal output port.

[0202] In some implementations, the determining module 51 is further configured to use the delay corresponding to the second signal output port as the signal delay corresponding to the second signal output port when the target timing model is the first timing model and the delay corresponding to the second signal output port meets the second preset condition, or when the target timing model is the second timing model.

[0203] In some implementations, when the target timing model is a first timing model, the second target timing parameters include clock port delay, a second clock delay set, a hold duration set, and a second data delay set; the determining module 51 is further configured to determine a fourth difference between the clock port delay and the clock delay corresponding to the second target port in the second clock delay set; wherein, the second target port is a first signal input port connected to the second signal output port; determine a fifth difference between the data delay corresponding to the second target port in the second data delay set and the hold duration of the second register driven by the second target port in the hold duration set; and determine the delay corresponding to the second signal output port based on the fourth and fifth differences.

[0204] In some implementations, when the target timing model is a second timing model, the second target timing parameters include clock port delay, a first clock delay set, a first data delay set, and a transmission delay set; the determining module 51 is further configured to determine a sixth difference between the clock port delay and the clock delay corresponding to the fourth target port in the first clock delay set; wherein, the fourth target port is a first signal output port connected to the second signal output port; determine a third sum between the data delay corresponding to the fourth target port in the first data delay set and the transmission delay of the first register driving the fourth target port in the transmission delay set; and determine the delay corresponding to the second signal output port based on the sixth difference and the third sum.

[0205] The description of the above apparatus embodiments is similar to that of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the apparatus embodiments of this disclosure, please refer to the description of the method embodiments of this disclosure for understanding.

[0206] It should be noted that, in the embodiments of this disclosure, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this disclosure, or the parts that contribute to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this disclosure are not limited to any specific hardware and software combination.

[0207] This disclosure provides an electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the above-described method.

[0208] This disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method. The computer-readable storage medium can be transient or non-transient.

[0209] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0210] It should be noted that, Figure 6 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of the present disclosure, such as... Figure 6 As shown, the hardware entity of the electronic device 600 includes: a processor 601, a communication port 602, and a memory 603, wherein: The processor 601 typically controls the overall operation of the electronic device 600.

[0211] Communication port 602 enables electronic devices to communicate with other terminals or servers over a network.

[0212] The memory 603 is configured to store instructions and applications executable by the processor 601, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 601 and various modules in the electronic device 600. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 601, communication port 602, and memory 603 can be performed via bus 604.

[0213] It should be noted that the descriptions of the storage medium and device embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0214] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0215] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0216] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some ports, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0217] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0218] In addition, each functional unit in the embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0219] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0220] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0221] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A post-simulation method, characterized in that, The method includes: Using a target timing model, target timing parameters are determined from multiple timing parameters in a timing parameter set. Based on the parameter values ​​of the target timing parameters, the simulated delay when the test platform and the target system interact with signals is determined. The target timing model is determined based on the current interaction scenario between the test platform and the target system, where the current interaction scenario represents the communication mode or connection method between the test platform and the target system. Different timing models use at least some different timing parameters. The first connection file is marked according to the simulated delay to obtain the second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file is the first connection file with the simulated delay added; Post-simulation of the target system is performed based on the second connection file.

2. The method according to claim 1, characterized in that, The method further includes: The target time series model is determined based on the current interaction scenario between the test platform and the target system; wherein, the interaction path between the test platform and the target system is at least partially different under different interaction scenarios.

3. The method according to claim 2, characterized in that, The current interaction scenario includes: A first interaction scenario, wherein the first interaction scenario indicates that the test platform is located outside the target system; or... The second interaction scenario, wherein the second interaction scenario represents that the test platform is located inside the target system.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: obtaining the parameter values ​​of multiple timing parameters in the timing parameter set at the target process angle; wherein the timing parameters have different parameter values ​​at different process angles.

5. The method according to any one of claims 1 to 3, characterized in that, The target system includes a first clock port, at least one first signal output port, a first register driving each of the first signal output ports, at least one first signal input port, and a second register driven by each of the first signal input ports; the test platform includes a second clock port. The timing parameter set includes at least one of the following: Clock port delay characterizes the delay from the target clock source to the first clock port; The first clock delay set includes the clock delay corresponding to each of the first signal output ports, wherein the clock delay corresponding to the first signal output port is the clock delay from the target clock source to the corresponding first register driving the first signal output port; The first data delay set includes the data delay corresponding to each of the first signal output ports. The data delay corresponding to the first signal output port is the data delay from the first register driving the first signal output port to the first signal output port. The transmission delay set includes the transmission delay of each first register driving the first signal output port; The second clock delay set includes the clock delay corresponding to each of the first signal input ports, where the clock delay corresponding to the first signal input port is the clock delay from the target clock source to the second register driven by the first signal input port. The setup duration set includes the setup duration of the second register driven by each of the first signal input ports; The hold duration set includes the hold duration of the second register driven by each of the first signal input ports; The second data delay set includes the data delay corresponding to each of the first signal input ports. The data delay corresponding to the first signal input port is the data delay from the first signal input port to the second register driven by the first signal input port. The margin set includes the setup time margin of the second register driven by each of the first signal input ports based on the actual timing. The clock cycle of the second clock port of the test platform.

6. The method according to any one of claims 1 to 3, characterized in that, When the simulated delay includes the clock delay corresponding to the second clock port, the target timing parameter includes the first target timing parameter; the test platform also includes at least one second signal input port; The determination of the simulated delay during signal interaction between the test platform and the target system based on the parameter values ​​of the target timing parameters includes: For each of the second signal input ports, the delay corresponding to the second signal input port is determined based on the parameter value of the first target timing parameter; If the delay corresponding to at least one of the second signal input ports does not meet the first preset condition, the clock delay corresponding to the second clock port is determined based on the delay corresponding to each of the second signal input ports.

7. The method according to claim 6, characterized in that, Determining the clock delay corresponding to the second clock port based on the delay corresponding to each of the second signal input ports includes: The first target delay is determined based on the delay corresponding to each of the second signal input ports; The clock delay corresponding to the second clock port is determined based on the first sum between the first target delay and the first target value.

8. The method according to claim 6, characterized in that, When the target timing model is a first timing model, the first target timing parameters include the clock period of the second clock port, the clock port delay, the first clock delay set, the first data delay set, and the transmission delay set; Determining the delay corresponding to the second signal input port based on the parameter value of the first target timing parameter includes: Determine a first difference between the clock port delay and the clock delay corresponding to the first target port in the first clock delay set; the first target port is a first signal output port connected to the second signal input port. Determine a second difference between the clock period of the second clock port, the data delay corresponding to the first target port in the first data delay set, and the transmission delay of the first register driving the first target port in the transmission delay set; Based on the first difference and the second difference, the delay corresponding to the second signal input port is determined.

9. The method according to claim 6, characterized in that, When the target timing model is the second timing model, the first target timing parameters include clock port delay, second clock delay set, setup duration set, and margin set; Determining the delay corresponding to the second signal input port based on the parameter value of the first target timing parameter includes: Determine a second sum between the setup duration of the second register driven by the third target port in the setup duration set and the setup duration margin of the second register driven by the third target port in the margin set; wherein, the third target port is a first signal input port connected to the second signal input port; Determine a third difference between the clock port delay and the clock delay corresponding to the third target port in the second clock delay set; Based on the second sum and the third difference, the delay corresponding to the second signal input port is determined.

10. The method according to any one of claims 1 to 3, characterized in that, When the simulated delay includes the signal delay corresponding to at least one second signal output port, the target timing parameter includes a second target timing parameter; The determination of the simulated delay during signal interaction between the test platform and the target system based on the parameter values ​​of the target timing parameters includes: For each second signal output port, based on the second target timing parameters, the delay corresponding to the second signal output port is determined, and based on the delay corresponding to the second signal output port, the signal delay corresponding to the second signal output port is determined.

11. The method according to claim 10, characterized in that, Determining the signal delay corresponding to the second signal output port based on the delay corresponding to the second signal output port includes: When the target timing model is the first timing model and the delay corresponding to the second signal output port meets the second preset condition, or when the target timing model is the second timing model, the delay corresponding to the second signal output port is taken as the signal delay corresponding to the second signal output port.

12. The method according to claim 10, characterized in that, When the target timing model is the first timing model, the second target timing parameters include clock port delay, second clock delay set, hold duration set, and second data delay set; The step of determining the delay corresponding to the second signal output port based on the second target timing parameters includes: Determine a fourth difference between the clock port delay and the clock delay corresponding to the second target port in the second clock delay set; wherein the second target port is a first signal input port connected to the second signal output port; Determine the fifth difference between the data delay corresponding to the second target port in the second data delay set and the hold duration of the second register driven by the second target port in the hold duration set; Based on the fourth difference and the fifth difference, the delay corresponding to the second signal output port is determined.

13. The method according to claim 10, characterized in that, When the target timing model is a second timing model, the second target timing parameters include clock port delay, a first clock delay set, a first data delay set, and a transmission delay set; The step of determining the delay corresponding to the second signal output port based on the second target timing parameters includes: Determine a sixth difference between the clock port delay and the clock delay corresponding to the fourth target port in the first clock delay set; wherein, the fourth target port is a first signal output port connected to the second signal output port; Determine the third sum value between the data delay corresponding to the fourth target port in the first data delay set and the transmission delay of the first register driving the fourth target port in the transmission delay set; Based on the sixth difference and the third sum, the delay corresponding to the second signal output port is determined.

14. A post-simulation device, characterized in that, include: A determination module is used to determine target timing parameters from multiple timing parameters in a timing parameter set using a target timing model, and to determine the simulated delay when the test platform and the target system interact with signals based on the parameter values ​​of the target timing parameters; wherein, the target timing model is determined based on the current interaction scenario between the test platform and the target system, the current interaction scenario characterizing the communication mode or connection method between the test platform and the target system, and different timing models use at least some different timing parameters; A marking module is used to mark a first connection file according to the simulated delay to obtain a second connection file; wherein, the first connection file includes a signal mapping table and / or connection description file between the test platform and the target system; the second connection file is based on the first connection file with the simulated delay added; The post-simulation module is used to perform post-simulation of the target system based on the second connection file.

15. An electronic device comprising a processor and a memory, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the computer program, it implements the method according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method described in any one of claims 1 to 13.

17. A computer program product, characterized in that, The computer program product includes a non-transitory computer-readable storage medium storing a computer program that, when read and executed by a computer, implements the method of any one of claims 1 to 13.

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