Method for checking resistance of integrated circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-06-02
Smart Images
Figure CN121615587B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a method for checking the resistance of an integrated circuit. Background Technology
[0002] With the development of semiconductor process technology and the increasing complexity of integrated circuit design, improving the reliability of integrated circuits has become a key focus for those skilled in the art. It is well known that static electricity can generate huge current or voltage pulses instantaneously during the discharge process, potentially damaging integrated circuits. Therefore, to minimize damage from static electricity, integrated circuits are typically equipped with ESD (Electro-Static Discharge) circuits, which protect the integrated circuit in the event of static electricity.
[0003] In ESD circuits, the resistance of the entire discharge path often affects the efficiency or reliability of the entire ESD circuit's discharge. Therefore, checking the resistance of ESD circuits is an important task in the chip development process. Traditional resistance sampling methods can only simply sample the resistance between two points. If the resistance between two points is incorrect, it is necessary to re-sample the resistance at different points, gradually narrowing down the range until the incorrect location is found. This method is inefficient and prone to errors. Summary of the Invention
[0004] In view of this, the embodiments of this application aim to provide a method for checking the resistance of integrated circuits, so as to solve the problems of low efficiency and easy error in the resistance checking of the prior art.
[0005] This application provides a method for checking the resistance of an integrated circuit, including:
[0006] Provide the circuit design information of the integrated circuit, as well as the first and second locations to be inspected of the integrated circuit;
[0007] Based on the circuit design information, obtain all conductive paths between the first location to be inspected and the second location to be inspected;
[0008] Illegal paths are filtered out from the conductive paths based on the resistance of each conductive path;
[0009] Obtain all interconnect segments in the illegal path, wherein the interconnect segments are used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads in the illegal path to the pins of devices; and,
[0010] Illegal segments are selected from the interconnect segments based on the resistance of each interconnect segment.
[0011] In some embodiments, the circuit design information includes netlist information or layout information.
[0012] In some embodiments, the first location to be inspected includes n first inspection points, the second location to be inspected includes m second inspection points, and n+m is greater than 2; and...
[0013] Any first point to be checked and any second point to be checked are paired together to obtain all the conductive paths between the first point to be checked and the second point to be checked in each pair. The set of conductive paths of all pairs is all the conductive paths between the first position to be checked and the second position to be checked.
[0014] In some embodiments, before obtaining all the conductive paths between the first location to be inspected and the second location to be inspected, the method further includes:
[0015] Obtain all pads, all components, and all pins of each component from the circuit design information;
[0016] The pads, devices, and pins in the circuit design information are classified. Pads with the same function belong to the same category, devices of the same type belong to the same category, and pins of the same function of devices of the same type belong to the same category.
[0017] In some embodiments, the first location to be inspected is used to indicate a type of pad or a type of pin, and the n first inspection points are all pads of that type of pad or all pins of that type of pin; and
[0018] The second inspection location is used to indicate a type of pad or a type of pin, and the m second inspection points are all the pads of that type of pad or all the pins of that type of pin.
[0019] In some embodiments, after obtaining all the conductive paths between the first location to be inspected and the second location to be inspected, all the interconnect segments in each conductive path are obtained, and the resistance of all the interconnect segments in each conductive path is obtained. The resistances of all the interconnect segments in each conductive path are added together to obtain the resistance of each conductive path.
[0020] In some embodiments, the conductive path with a resistance greater than a predetermined value is the illegal path.
[0021] In some embodiments, the interconnect segment with the highest resistance in the illegal path is the illegal segment.
[0022] In some embodiments, after the illegal segments are selected, the illegal segments are back-annotated to the circuit design information.
[0023] In some embodiments, the integrated circuit is an ESD circuit.
[0024] This application provides a resistance inspection method for integrated circuits, comprising: providing circuit design information of the integrated circuit and a first and second inspection location of the integrated circuit; obtaining all conductive paths between the first and second inspection locations based on the circuit design information; filtering out illegal paths from the conductive paths based on the resistance of each conductive path; obtaining all interconnect segments in the illegal paths, wherein the interconnect segments are used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads in the illegal path to the pins of devices; and filtering out illegal segments from the interconnect segments based on the resistance of each interconnect segment. An unexpected benefit of this application is that it first obtains all conductive paths between the first and second inspection locations, filters out illegal paths using the resistance of each conductive path, and then obtains all interconnect segments in the illegal paths, filtering out illegal segments using the resistance of each interconnect segment. This application can quickly and accurately locate illegal segments in the integrated circuit, facilitating modification and reducing development cycle and cost. Attached Figure Description
[0025] Figure 1 A flowchart of a resistance checking method for an integrated circuit provided in an embodiment of this application.
[0026] Figure 2 This is a schematic diagram of a simplified ESD circuit provided in one embodiment of this application.
[0027] Figure 3 This is a schematic diagram of a conductive path provided in an embodiment of this application.
[0028] Figure 4 This is a schematic diagram of all interconnect segments of a first path provided in an embodiment of this application.
[0029] Figure 5 This is a schematic diagram of all interconnect segments of a second path provided in an embodiment of this application.
[0030] The attached figures are labeled as follows:
[0031] VDD - Power supply terminal; VSS - Ground terminal; IN - Signal input terminal; M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; Path1 - First path; Path2 - Second path; net1 - First interconnect segment; net2 - Second interconnect segment; net3 - Third interconnect segment; net4 - Fourth interconnect segment; net5 - Fifth interconnect segment. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] Figure 1 A flowchart illustrating a resistance checking method for an integrated circuit provided in an embodiment of this application. Figure 1 As shown, the resistance testing methods for integrated circuits include:
[0034] Step S100: Provide the circuit design information of the integrated circuit and the first and second locations to be inspected of the integrated circuit;
[0035] Step S200: Obtain all conductive paths between the first location to be inspected and the second location to be inspected based on the circuit design information;
[0036] Step S300: Illegal paths are filtered out from the conductive paths based on the resistance of each conductive path;
[0037] Step S400: Obtain all interconnect segments in the illegal path. Interconnect segments are used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads and device pins in the illegal path; and...
[0038] Step S500: Illegal segments are selected from the interconnect segments based on the resistance of each interconnect segment.
[0039] Specifically, step S100 is executed first to provide circuit design information for the integrated circuit. This information can be netlist or layout information, such as GDS (Graphics Display System) file information or Oasis (Open Artwork System Interchange Standard) file information. The circuit design information includes details about the structure of various devices, metal lines, vias, and other components within the integrated circuit.
[0040] Furthermore, the integrated circuit can be an ESD circuit, which can contain diodes, transistors (NPN or PNP), MOSFETs (NMOS or PMOS), resistors, capacitors, inductors, and various silicon controlled thyristors (SCRs). Figure 2 A simplified schematic diagram of an ESD circuit provided for one embodiment of this application is shown below. Figure 2As shown, the ESD circuit may include a power supply terminal VDD, a ground terminal VSS, a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The power supply terminal VDD is electrically connected to the drains of the first MOSFET M1 and the third MOSFET M3. The source of the first MOSFET M1 is electrically connected to the drain of the second MOSFET M2. The sources of the second MOSFET M2 and the third MOSFET M3 are both electrically connected to the ground terminal VSS. The gates of the first MOSFET M1 and the second MOSFET M2 are both electrically connected to the signal input terminal IN. The gate of the third MOSFET M3 is electrically connected to the power supply terminal VDD.
[0041] Understandable, Figure 2 The layout information of the ESD circuit should have pads corresponding to the power supply terminal VDD, the ground terminal VSS, and the signal input terminal IN, respectively. These three types of pads can be referred to as power supply pads, ground pads, and signal input pads. The first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 each have three pins, namely the source pin, the drain pin, and the gate pin. According to Figure 2 The electrical connections are as follows: the drain pins of the first MOSFET M1 and the third MOSFET M3 are electrically connected to the power pad through corresponding interconnect structures; the source pin of the first MOSFET M1 is electrically connected to the drain pin of the second MOSFET M2 through corresponding interconnect structures; the source pins of the second MOSFET M2 and the third MOSFET M3 are electrically connected to the ground pad through corresponding interconnect structures; the gate pins of the first MOSFET M1 and the second MOSFET M2 are electrically connected to the signal input pad through corresponding interconnect structures; and the gate pin of the third MOSFET M3 is electrically connected to the power pad through corresponding interconnect structures. The interconnect structures can include at least one of metal lines and vias. For example, assuming the source pin of the first MOSFET M1 is interconnected to the power pad through 5 layers of metal lines, and adjacent metal lines are interconnected through at least one via, then the interconnect structure between the source pin of the first MOSFET M1 and the power pad includes these 5 metal lines and all the vias connecting these 5 metal lines.
[0042] For ease of description, we will assume that the first MOSFET M1 and the third MOSFET M3 are NMOS transistors, and the second MOSFET M2 is a PMOS transistor.
[0043] It should be noted that, Figure 2 The ESD circuit shown is only used to illustrate the subsequent steps of the resistance testing method for integrated circuits. In practical applications, the ESD circuit can be any possible circuit, and there can also be other possible devices for the ESD circuit.
[0044] Furthermore, it is also necessary to provide a first and a second location to be inspected in the integrated circuit. The first and second locations to be inspected can be any two different locations within the integrated circuit. For example, the first and second locations to be inspected could be the locations of power supply / ground / signal input / signal output terminals, or any port of any device. Providing the first and second locations to be inspected essentially provides two resistance inspection locations within the integrated circuit. Subsequently, the resistance between the first and second locations to be inspected needs to be checked to determine if there are any violations between them. Figure 2 For example, the first location to be checked can be the power supply terminal VDD, and the second location to be checked can be the ground terminal VSS. The resistance between the power supply terminal VDD and the ground terminal VSS needs to be checked. As another example, the first location to be checked can be the power supply terminal VDD, and the second location to be checked can be the source of the NMOS transistor. The resistance between the power supply terminal VDD and the sources of all NMOS transistors needs to be checked.
[0045] Furthermore, the first position to be checked includes n first check points, and the second position to be checked includes m second check points, where n and m can both be equal to 1. For example, the first location to be inspected can be the power supply terminal VDD, in which case the first inspection point is the power pad. The second location to be inspected can be the ground terminal VSS, in which case the second inspection point is the ground pad. If there is only one power pad and one ground pad, then the number of first inspection points n and the number of second inspection points m are both 1. Checking the resistance between the first and second inspection locations is actually checking the resistance between the power pad and the ground pad. As another example, the first location to be inspected can be the power supply terminal VDD, in which case the first inspection point is the power pad. The second location to be inspected can be the source of a PMOS transistor, in which case the second inspection point is the source pin of the second MOS transistor M2. If there is only one power pad, then the number of first inspection points n and the number of second inspection points m are both 1. Checking the resistance between the first and second inspection locations is actually checking the resistance between the power pad and the source pin of the second MOS transistor M2.
[0046] In some embodiments, n+m can be greater than 2. For example, the first location to be inspected can be the power supply terminal VDD, in which case the first inspection point is the power supply pad. The second location to be inspected can be the source of an NMOS transistor, in which case the second inspection point is the source pin of the first MOS transistor M1 and the source pin of the third MOS transistor M3. If there is only one power supply pad, then the number of first inspection points n is 1, and the number of second inspection points m is 2. Inspecting the resistance between the first and second inspection locations is actually inspecting the resistance between the power supply pad and the source pin of the first MOS transistor M1, and inspecting the resistance between the power supply pad and the source pin of the third MOS transistor M3.
[0047] Next, step S200 is executed to obtain all pads, all components, and all pins of each component from the circuit design information. Then, the pads, components, and pins in the circuit design information are categorized. Pads with the same function belong to the same category, components of the same type belong to the same category, and pins of the same function within the same category of components belong to the same category. Specifically, pads can be categorized by function as follows: power pads, ground pads, signal input pads, and signal output pads, etc. All pads in the circuit design information are categorized by function, and all pads within the same category have the same function. Components can be categorized by type as follows: diodes, NPN transistors, PNP transistors, NMOS transistors, PMOS transistors, resistors, capacitors, inductors, etc. All components in the circuit design information are categorized by type, and all components within the same category have the same type. Pins can be categorized by component type and pin function as follows: the negative terminal of a diode... The circuit design information categorizes all pins according to their device type and function, including the anode of a diode, the base, collector, and emitter of an NPN transistor, the base, collector, and emitter of a PNP transistor, the source, gate, and drain of an NMOS transistor, the source, gate, and drain of a PMOS transistor, the high-voltage terminal and low-voltage terminal of a resistor, the high-voltage terminal and low-voltage terminal of a capacitor, and the high-voltage terminal and low-voltage terminal of an inductor.
[0048] In some embodiments, power pads with different voltages can be considered as pads with different functions and can be classified into different types of power pads; signal input pads / signal output pads with different input / output signals can be considered as pads with different functions and can be classified into different types of signal input pads / signal output pads; devices with different parameters (such as resistors with different resistance values, capacitors with different capacitance values, or inductors with different inductance values) can be considered as devices of different types and can be classified into different types of devices.
[0049] Based on this, the first inspection location is actually used to indicate a type of pad or a type of pin, and n first inspection points are all pads of that type of pad or all pins of that type of pin. The second inspection location is used to indicate a type of pad or a type of pin, and m second inspection points are all pads of that type of pad or all pins of that type of pin. Only after classifying all pads in the circuit design information according to their functions can we quickly find all first inspection points in the first inspection location and all second inspection points in the second inspection location.
[0050] by Figure 2 For example, Figure 2 The design information for the ESD circuit includes three types of pads, two types of devices, and six types of pins. The three types of pads are power pads (corresponding to power supply terminal VDD), ground pads (corresponding to ground terminal VSS), and signal input pads (signal input terminal IN). The two types of devices are NMOS transistors (corresponding to the first MOS transistor M1 and the third MOS transistor M3) and PMOS transistors (corresponding to the second MOS transistor M2). The six types of pins are the source pin of the NMOS transistor (corresponding to the source of the first MOS transistor M1 and the third MOS transistor M3), the gate pin of the source pin of the NMOS transistor (corresponding to the gate of the first MOS transistor M1 and the third MOS transistor M3), the drain pin of the NMOS transistor (corresponding to the drain of the first MOS transistor M1 and the third MOS transistor M3), the source pin of the PMOS transistor (corresponding to the source of the second MOS transistor M2), the gate pin of the source pin of the PMOS transistor (corresponding to the gate of the second MOS transistor M2), and the drain pin of the PMOS transistor (corresponding to the drain of the second MOS transistor M2). Assuming the first location to be checked is the power supply terminal VDD, since... Figure 2 There is only one power supply pad, so there is only one first inspection point in the first inspection location, which is the power supply pad. Assuming the second inspection location is the source pin of an NMOS transistor, etc., since... Figure 2 There are two source pins of the NMOS transistor. At this time, there are only two second inspection points in the second inspection location, namely the source pins of the first MOS transistor M1 and the third MOS transistor M3.
[0051] Furthermore, all conductive paths between the first and second locations to be inspected are obtained. As explained above, the first location to be inspected may include one or more first inspection points, and the second location to be inspected may include one or more second inspection points. When the first location to be inspected includes one first inspection point and the second location to be inspected includes one second inspection point, all conductive paths between the first and second locations to be inspected are actually all conductive paths between the first inspection point and the second inspection point. However, when the first location to be inspected includes more than one first inspection point and / or the second location to be inspected includes more than one second inspection point, it is necessary to combine any first inspection point with any second inspection point in pairs and obtain all conductive paths between the first inspection point and the second inspection point in each combination. The set of conductive paths of all combinations is the total number of conductive paths between the first and second locations to be inspected.
[0052] Furthermore, there may be only one or multiple conductive paths between the first and second locations to be inspected, and the number of conductive paths does not affect the implementation of this application.
[0053] To further explain "all conductive paths between the first and second inspection locations", assume that the first inspection location includes first inspection points A1 and A2, and the second inspection location includes second inspection points B1 and B2. By pairing any first inspection point with any second inspection point, we get four possible combinations: A1B1, A2B1, A2B1, and A2B2. Then, all conductive paths between the first and second inspection locations are the set of all conductive paths between A1 and B1, A2 and B1, A2 and B2, and A2 and B2.
[0054] It should be noted that when obtaining all conductive paths between the first and second locations to be inspected, a specific device can be identified as a wire, thereby avoiding the device from affecting the search for conductive paths.
[0055] Figure 3 This is a schematic diagram of a conductive path provided in one embodiment of this application. For example... Figure 3 As shown, assuming the first and second locations to be inspected are the power supply terminal VDD and the ground terminal VSS respectively, then there are two conductive paths between the first and second locations to be inspected, namely... Figure 3 The power supply terminal VDD—first MOSFET M1—second MOSFET M2—ground terminal VSS ( Figure 3The red conductive path in the diagram is referred to as the first path Path1), and the power supply terminal VDD—the third MOSFET M3—the ground terminal VSS ( Figure 3 The green conductive path in the image is referred to as the second path, Path2.
[0056] Step S300 is executed to calculate the resistance of each conductive path, thereby filtering out illegal paths from the conductive paths based on the resistance of each conductive path. In some embodiments, illegal paths can be filtered by designing a threshold method. Since the first and second inspection positions are specified, the resistance between the first and second inspection positions should have an ideal range (corresponding rules are designed during integrated circuit design). Generally speaking, when the resistance of a conductive path is less than a predetermined value, it indicates that the resistance of the conductive path is within the ideal range, and the conductive path can be determined to be legal. If the resistance of a conductive path is greater than or equal to the predetermined value, it indicates that the resistance of the conductive path exceeds the ideal range, and the conductive path can be determined to be illegal and needs to be modified. That is, conductive paths with a resistance greater than the predetermined value are identified as illegal paths.
[0057] For example, please continue reading Figure 3 The resistance of the first path Path1 and the second path Path2 is calculated, and then the relationship between the resistance of the first path Path1 and the second path Path2 and a predetermined value is determined, thereby determining whether the first path Path1 and the second path Path2 are illegal. For ease of subsequent description, it is assumed that both the first path Path1 and the second path Path2 are illegal, in which case both the first path Path1 and the second path Path2 can be regarded as illegal paths.
[0058] It should be noted that the predetermined value can be an empirical value. Different combinations of the first and second inspection positions can correspond to different predetermined values, which will not be illustrated here.
[0059] In some embodiments, the resistance of each conductive path can be calculated using internal data from the circuit design information. For example, if the circuit design information provides the dimensions of the interconnect structure, the resistance of each conductive path can be calculated based on the sheet resistance value and the dimensions. Alternatively, the resistance of each conductive path can be calculated using the resistivity and dimensions of the conductive material.
[0060] In some embodiments, the resistance of each conductive path can also be extracted using computer-aided design software tools. That is, excitation signals are applied to the two ports of the conductive path according to the circuit simulation method, and then the resistance of the conductive path is obtained by analyzing the voltage and current.
[0061] Execute step S400 to obtain all interconnect segments in the illegal path. Each interconnect segment is used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads in the illegal path to the pins of a device. Alternatively, after identifying the illegal path, each illegal path can be divided into interconnect segments, with each interconnect segment corresponding to an interconnect structure within the illegal path.
[0062] Figure 4 A schematic diagram of all interconnected segments of the first path Path1 provided in an embodiment of this application is shown below. Figure 4 As shown, the first path Path1 has three interconnect segments, namely the first interconnect segment net1, the second interconnect segment net2, and the third interconnect segment net3. The first interconnect segment net1 is directly electrically connected to the power pad and the drain pin of the first MOSFET M1. The second interconnect segment net2 is directly electrically connected to the source pin of the first MOSFET M1 and the drain pin of the second MOSFET M2. The third interconnect segment net3 is directly electrically connected to the source pin of the second MOSFET M2 and the ground pad. Figure 5 This is a schematic diagram of all interconnected segments of the second path Path2 provided in an embodiment of this application, as shown below. Figure 5 As shown, the second path Path2 has two interconnect segments, namely the fourth interconnect segment net4 and the fifth interconnect segment net5. The fourth interconnect segment net4 is directly electrically connected to the power supply pad and the drain pin of the third MOSFET M3. The fifth interconnect segment net5 is directly electrically connected to the source pin of the third MOSFET M3 and the ground pad.
[0063] Next, step S500 is executed to calculate the resistance of each interconnect segment. Based on the resistance of each interconnect segment, illegal segments can be screened out from the interconnect segments. This illegal segment is the cause of the illegal path. Since the higher the resistance of an interconnect segment, the more likely it is to violate the law, the resistances of all interconnect segments in each illegal path can be sorted to find the interconnect segment with the highest resistance in each illegal path. This interconnect segment with the highest resistance in each illegal path is the illegal segment and needs to be modified. Therefore, this application first obtains all conductive paths between the first and second inspection locations, filters out illegal paths using the resistance of each conductive path, and then obtains all interconnect segments in the illegal path. The illegal segment can then be screened out using the resistance of each interconnect segment. This application can quickly and accurately locate illegal segments in integrated circuits, facilitating modification and reducing R&D cycle and cost.
[0064] For example, please continue reading Figure 4 and Figure 5Calculate the resistance of the first interconnect segment net1, the second interconnect segment net2, the third interconnect segment net3, the fourth interconnect segment net4, and the fifth interconnect segment net5. Then find the segment with the largest resistance among the first interconnect segment net1, the second interconnect segment net2, and the third interconnect segment net3, and use it as the illegal segment of the first path Path1. Find the segment with the largest resistance between the fourth interconnect segment net4 and the fifth interconnect segment net5, and use it as the illegal segment of the second path Path2.
[0065] In some embodiments, the resistance of each interconnect segment can be calculated using internal data from the circuit design information. For example, if the circuit design information provides the dimensions of the interconnect structure, the resistance of each interconnect segment can be calculated based on the sheet resistance value and the dimensions. Alternatively, the resistance of each interconnect segment can be calculated using the resistivity and dimensions of the conductive material.
[0066] In some embodiments, the resistance of each interconnect segment can also be extracted using computer-aided design software tools. That is, excitation signals are applied to the two ports of the interconnect segment according to the circuit simulation method, and then the resistance of the interconnect segment is obtained by analyzing the voltage and current.
[0067] In some embodiments, after obtaining all conductive paths between the first and second locations to be inspected, before calculating the resistance of each conductive path, all interconnect segments of each conductive path can be obtained first, and the resistance of all interconnect segments in each conductive path can be obtained. Since each conductive path is composed of interconnect segments, and the specific device is treated as a wire (which can be ignored), the resistances of all interconnect segments in each conductive path can be added together to obtain the resistance of each conductive path. In this way, the difficulty of obtaining the resistance of conductive paths can be simplified, and the amount of computation can be saved.
[0068] Furthermore, after identifying the illegal segments, these segments can be back-annotated to the circuit design information. This allows circuit designers to quickly locate the illegal segments and modify the design, further reducing the development cycle and costs.
[0069] In summary, this embodiment provides a resistance inspection method for integrated circuits, including: providing circuit design information of the integrated circuit and a first and second inspection location of the integrated circuit; obtaining all conductive paths between the first and second inspection locations based on the circuit design information; filtering out illegal paths from the conductive paths based on the resistance of each conductive path; obtaining all interconnect segments in the illegal paths, wherein the interconnect segments are used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads in the illegal path to the pins of devices; and filtering out illegal segments from the interconnect segments based on the resistance of each interconnect segment. An unexpected benefit of this application is that it first obtains all conductive paths between the first and second inspection locations, filters out illegal paths using the resistance of each conductive path, and then obtains all interconnect segments in the illegal paths, using the resistance of each interconnect segment to filter out illegal segments. This application can quickly and accurately locate illegal segments in integrated circuits, facilitating modification and reducing development cycles and costs.
[0070] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0071] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
[0072] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0073] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for checking the resistance of an integrated circuit, characterized in that, include: Provide the circuit design information of the integrated circuit, as well as the first and second locations to be inspected of the integrated circuit; Based on the circuit design information, obtain all conductive paths between the first location to be inspected and the second location to be inspected; Illegal paths are filtered out from the conductive paths based on the resistance of each conductive path; Obtain all interconnect segments in the illegal path, wherein the interconnect segments are used to directly electrically connect the pins of two adjacent devices in the illegal path or to directly electrically connect adjacent pads in the illegal path to the pins of devices; and, Illegal segments are selected from the interconnect segments based on the resistance of each interconnect segment.
2. The method for checking the resistance of an integrated circuit according to claim 1, characterized in that, The circuit design information includes netlist information or layout information.
3. The method for checking the resistance of an integrated circuit according to claim 1, characterized in that, The first location to be inspected includes n first inspection points, and the second location to be inspected includes m second inspection points, where n+m is greater than 2; as well as, Any first point to be checked and any second point to be checked are paired together to obtain all the conductive paths between the first point to be checked and the second point to be checked in each pair. The set of conductive paths of all pairs is all the conductive paths between the first position to be checked and the second position to be checked.
4. The method for checking the resistance of an integrated circuit according to claim 3, characterized in that, Before obtaining all the conductive paths between the first location to be inspected and the second location to be inspected, the method further includes: Obtain all pads, all components, and all pins of each component from the circuit design information; The pads, devices, and pins in the circuit design information are classified. Pads with the same function belong to the same category, devices of the same type belong to the same category, and pins of the same function of devices of the same type belong to the same category.
5. The method for checking the resistance of an integrated circuit according to claim 4, characterized in that, The first location to be inspected is used to indicate a type of pad or a type of pin; the n first inspection points are all pads of that type of pad or all pins of that type of pin; and, The second inspection location is used to indicate a type of pad or a type of pin, and the m second inspection points are all the pads of that type of pad or all the pins of that type of pin.
6. The method for checking the resistance of an integrated circuit according to claim 1, characterized in that, After obtaining all the conductive paths between the first inspection location and the second inspection location, obtain all the interconnect segments in each conductive path and obtain the resistance of all the interconnect segments in each conductive path. Add the resistances of all the interconnect segments in each conductive path to obtain the resistance of each conductive path.
7. The method for checking the resistance of an integrated circuit according to any one of claims 1 to 6, characterized in that, The conductive path with a resistance greater than a predetermined value is the illegal path.
8. The method for checking the resistance of an integrated circuit according to any one of claims 1 to 6, characterized in that, The interconnect segment with the highest resistance in the illegal path is the illegal segment.
9. The method for checking the resistance of an integrated circuit according to any one of claims 1 to 6, characterized in that, After the illegal segments are identified, they are back-annotated to the circuit design information.
10. The method for checking the resistance of an integrated circuit according to claim 1, characterized in that, The integrated circuit is an ESD circuit.