Voltage overshoot suppression circuit and COT control mode buck converter system

Abstract

This application relates to the field of switching power supply control technology, and discloses a voltage overshoot suppression circuit and a COT control mode BUCK converter system. The voltage overshoot suppression circuit includes: a ripple injection module, a drop detection module, a first trigger, and a filter adjustment module. The drop detection module is connected to the first trigger. The first trigger is also connected to the filter adjustment module. The filter adjustment module is also connected to the ripple injection module. The ripple injection module is connected to an external conversion circuit. The filter adjustment module adjusts the time constant for generating a second ripple signal according to a first output signal, so that the falling process of the second ripple signal matches the first ripple signal. This avoids the situation where the first ripple signal is lower than the second ripple signal due to the slow falling of the second ripple signal, resulting in the injection of negative ripple. This reduces the number of times the power transistor in the external conversion circuit is turned on, thereby solving the output voltage overshoot problem of the COT control mode BUCK converter during the transition from light load to heavy load.

Description

Technical Field

[0001] This application relates to the field of switching power supply control technology, and in particular to a voltage overshoot suppression circuit and a COT control mode BUCK converter system. Background Technology

[0002] Common COT-controlled BUCK converter systems, which use ceramic capacitors with low equivalent series resistance as output capacitors, are prone to instability while achieving low output voltage ripple and high efficiency. To avoid this, researchers have proposed several solutions for loop compensation, including adding feedforward capacitors, sampling inductor current ripple injection, simulating inductor current ripple injection, sampling capacitor current ripple injection, and slope compensation.

[0003] When the inductor current ripple is compensated by simulation, the change in inductor current lags behind the change in load current when the output voltage rises to near the target value under heavy load. When the output voltage rises to near the target value under heavy load, the injected negative ripple will promote the conduction of the power transistor, increase the number of switching, and further increase the output voltage. It may exceed the target value under heavy load by a large margin, forming a large overshoot and deteriorating the transient response when the light load turns to heavy load. Summary of the Invention

[0004] The purpose of this application is to provide a voltage overshoot suppression circuit and a COT control mode BUCK converter system, which aims to solve the technical problem of output voltage overshoot in COT control mode BUCK converters when switching from light load to heavy load.

[0005] To achieve the above objectives, this application proposes a voltage overshoot suppression circuit, which includes: a ripple injection module, a drop detection module, a first trigger, and a filter adjustment module;

[0006] The drop detection module is connected to the first trigger; the first trigger is also connected to the filter adjustment module; the filter adjustment module is also connected to the ripple injection module; the ripple injection module is connected to an external conversion circuit.

[0007] The ripple injection module is used to output a first ripple signal and a second ripple signal according to the voltage at the switching node in the external conversion circuit.

[0008] The drop detection module is used to receive the output feedback voltage generated by the external conversion circuit, and generate a high-level signal when the output feedback voltage reaches a preset ratio of the reference voltage.

[0009] The first trigger is used to receive the high-level signal and convert it into a first output signal to the filter adjustment module;

[0010] The filtering adjustment module is used to adjust the time constant of the two ripple signals according to the first output signal, so that the external conversion circuit can suppress the overshoot of the output feedback voltage according to the adjusted two ripple signals.

[0011] In one embodiment, the voltage overshoot suppression circuit further includes: a cycle counting module;

[0012] The period counting module is connected to the first trigger;

[0013] The cycle counting module is used to take the moment when the first output signal is received as the starting point of the adjustment cycle;

[0014] The cycle counting module is also used to output a reset signal to the first trigger when the rising edge of the fourth PWM signal after receiving the first output signal arrives, and to take this moment as the end of the adjustment cycle.

[0015] The first trigger is also used to receive the reset signal and convert it into a second output signal to the filter adjustment module;

[0016] The filtering adjustment module is also used to adjust the time constant of the two-ripple signal according to the second output signal.

[0017] In one embodiment, the cycle counting module includes: a second flip-flop, a third flip-flop, a fourth flip-flop, and a first inverter;

[0018] The first terminal of the second flip-flop is connected to the fourth terminal and the second terminal of the third flip-flop. The second terminal of the second flip-flop is connected to an external PWM signal controller. The third terminal of the second flip-flop is connected to the third terminal of the third flip-flop, the third terminal of the fourth flip-flop, and the fifth terminal of the first flip-flop.

[0019] The first terminal of the third flip-flop is connected to the fourth terminal; the fourth terminal of the third flip-flop is also connected to the second terminal of the fourth flip-flop; the first terminal of the fourth flip-flop is connected to the fourth terminal, the fifth terminal and the first terminal of the first inverter; the second terminal of the first inverter is connected to the third terminal of the first flip-flop.

[0020] In one embodiment, the ripple injection module includes: a voltage divider unit, a first ripple unit, and a second ripple unit;

[0021] The voltage divider unit is connected to the conversion module, the first ripple unit, and the second ripple unit respectively; the second ripple unit is also connected to the filter adjustment unit.

[0022] The voltage divider unit is used to divide the voltage at the switching node in the external conversion circuit and transmit it to the first ripple unit and the second ripple unit.

[0023] The first ripple unit is used to generate the first ripple signal based on the node voltage after voltage division;

[0024] The second ripple unit is used to generate the second ripple signal based on the node voltage after voltage division.

[0025] In one embodiment, the voltage divider unit includes: a first voltage divider resistor and a second voltage divider resistor;

[0026] The first end of the first voltage divider resistor is connected to the external conversion circuit, and the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the first ripple unit, and the second ripple unit; the second end of the second voltage divider resistor is grounded.

[0027] In one embodiment, the first ripple unit includes: a first resistor, a second resistor, and a first capacitor;

[0028] The first end of the first resistor is connected to the voltage divider unit and the first end of the second resistor, and the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is connected to the first end of the first capacitor and the external conversion circuit; the second end of the first capacitor is grounded.

[0029] In one embodiment, the second ripple unit includes: a third resistor, a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor;

[0030] The second end of the third resistor is connected to the first end of the fourth resistor and the filter adjustment module; the second end of the fourth resistor is connected to the filter module, the first end of the second capacitor and the first end of the fifth resistor; the second end of the fifth resistor is connected to the first end of the third capacitor and the external conversion circuit; the second end of the second capacitor is grounded; the second end of the third capacitor is grounded.

[0031] In one embodiment, the filter adjustment module includes: a selector and a switching transistor;

[0032] The input terminal of the selector is connected to the fifth terminal of the first flip-flop, and the output terminal of the selector is connected to the gate of the switching transistor; the drain of the switching transistor is connected to the first terminal of the fourth resistor, and the source of the switching transistor is connected to the second terminal of the fourth resistor.

[0033] In one embodiment, the drop detection module includes: a first MOSFET to a seventh MOSFET, a second inverter, and a third inverter;

[0034] The gate of the first MOSFET is connected to the drain of the second MOSFET, the source of the first MOSFET is grounded, and the drain of the first MOSFET is connected to the drain of the fourth MOSFET.

[0035] The source of the second MOSFET is grounded, and the drain of the second MOSFET is connected to the drain of the fifth MOSFET and the gate of the third MOSFET.

[0036] The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the first terminal of the second inverter and the drain of the seventh MOS transistor.

[0037] The gate of the fourth MOS transistor receives the reference voltage; the source of the fourth MOS transistor is connected to the source of the fifth MOS transistor and the drain of the sixth MOS transistor.

[0038] The gate of the fifth MOS transistor receives the output feedback voltage;

[0039] The gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor, and the source of the sixth MOS transistor is connected to an external power supply and the source of the seventh MOS transistor.

[0040] In addition, to achieve the above objectives, this application also proposes a COT control mode BUCK converter system, which includes the voltage overshoot suppression circuit described above.

[0041] This application proposes a voltage overshoot suppression circuit and a COT control mode BUCK converter system. The voltage overshoot suppression circuit includes: a ripple injection module, a drop detection module, a first trigger, and a filter adjustment module; the drop detection module is connected to the first trigger; the first trigger is also connected to the filter adjustment module; the filter adjustment module is also connected to the ripple injection module; the ripple injection module is connected to an external conversion circuit; the ripple injection module is used to output a first ripple signal and a second ripple signal according to the voltage at the switching node in the external conversion circuit; the drop detection module is used to receive the output feedback voltage generated by the external conversion circuit and generate a high-level signal when the output feedback voltage reaches a preset proportion of the reference voltage; the first trigger is used to receive the high-level signal and convert it into a first output signal to the filter adjustment module; the filter adjustment module is used to adjust the time constant of the two ripple signals according to the first output signal, so that the external conversion circuit suppresses the output feedback voltage overshoot according to the adjusted two ripple signals. The filtering and adjustment module adjusts the time constant of the second ripple signal according to the first output signal, so that the time constant of the second ripple signal matches that of the first ripple signal. This avoids the situation in the prior art where the first ripple signal is lower than the second ripple signal due to the slow decline of the second ripple signal, thus injecting negative ripple. This suppresses unnecessary conduction of the power transistor in the external conversion circuit, reduces the number of switching operations, and ultimately solves the problem of output voltage overshoot in the COT control mode BUCK converter when switching from light load to heavy load. Compared with the prior art, this achieves the effect of enhancing the transient response of the system. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the first embodiment of the voltage overshoot suppression circuit proposed in this application;

[0043] Figure 2 This is a light-load jump-over heavy-load waveform diagram in the first embodiment of the voltage overshoot suppression circuit proposed in this application;

[0044] Figure 3 This is a schematic diagram of the first embodiment of the voltage overshoot suppression circuit proposed in this application;

[0045] Figure 4 This is a schematic diagram of the module of the second embodiment of the voltage overshoot suppression circuit proposed in this application;

[0046] Figure 5 This is a circuit connection diagram of the third embodiment of the voltage overshoot suppression circuit proposed in this application;

[0047] Figure 6 This is a light-load jump-over heavy-load waveform diagram in the third embodiment of the voltage overshoot suppression circuit proposed in this application;

[0048] Figure 7 This is a circuit connection diagram of the COT control mode BUCK converter system proposed in this application.

[0049] Explanation of icon numbers:

[0050] 100. Ripple injection module; 200. Drop detection module; 300. First trigger; 400. Filtering and adjustment module; 500. External conversion circuit; 600. Cycle counting module; 110. Voltage divider unit; 120. First ripple unit; 130. Second ripple unit; DFF2~DFF4. Second to fourth triggers; INV1~INV3. First to third inverters; Q1~Q7. First to seventh MOSFETs; Rsw1~Rsw2. First to second voltage divider resistors; Mc. Switch; R1~R5. First to fifth resistors; C1~C3. First to third capacitors; MUX. Selector. Detailed Implementation

[0051] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0053] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0054] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0055] Reference Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic diagram of the first embodiment of the voltage overshoot suppression circuit proposed in this application; Figure 2 This is a light-load jump-over heavy-load waveform diagram in the first embodiment of the voltage overshoot suppression circuit proposed in this application; Figure 3 This is a schematic diagram of a first embodiment of the voltage overshoot suppression circuit proposed in this application. Based on Figure 1 , Figure 2 and Figure 3 The first embodiment of the voltage overshoot suppression circuit of this application is presented.

[0056] It should be noted that common COT control mode BUCK converter systems, such as Figure 1 As shown. Because a ceramic capacitor with a small equivalent series resistance is used as the output capacitor, while achieving low output voltage ripple and high efficiency, instability is prone to occur. To avoid this, researchers have proposed several schemes for loop compensation, including adding a feedforward capacitor, sampling inductor current ripple injection, simulating inductor current ripple injection, sampling capacitor current ripple injection, and slope compensation. Here, Vin represents the power supply voltage; S1 and S2 are the upper and lower drive transistors of the system, respectively; SW is the switching node; L is the inductor; Co is the output capacitor, and Rco is its equivalent series resistance; Vout is the output voltage; Cfb is the feedforward capacitor; Vfb is a certain proportion of the output voltage, i.e., the output feedback voltage; Vref_fb is the reference voltage; CMP is the comparator; driver is the driver; ontime is the on-time controller for S1 and S2; ripple injection represents ripple injection, used in the COT control mode BUCK converter system to inject the first ripple signal SW_RC1 and the second ripple signal SW_RC2.

[0057] It should be understood that analog inductor current ripple injection is a commonly used compensation method. However, this ripple injection compensation method may cause a large output voltage overshoot during light-load to heavy-load transitions, deteriorating the converter's transient response. (Refer to...) Figure 2The load current (iload) rises rapidly at time t1, while the inductor current (iL) lags behind. When the DC value of the inductor current rises to equal the load current, the output voltage will begin to rise from its lowest point. Since SW_RC1 is in phase with the inductor current, it will also rise rapidly as the switching frequency increases during the rapid rise of the inductor current. The different time constants and filtering speeds of the filter networks cause SW_RC2 to change more slowly than SW_RC1. At time t2, the output voltage (vout) rises to near the target value under heavy load. In the following switching cycles, due to the decrease in switching frequency and the longer conduction time of the lower transistor, the decline time of SW_RC1 will also increase. Because SW_RC2 changes slowly and remains at a relatively high value, this will result in SW_RC1 being significantly lower than SW_RC2 before the next conduction of the upper transistor in adjacent switching cycles (as shown in the time interval from t2 to t3). Injecting negative ripple will promote the conduction of the power transistor, increase the number of switching cycles, and further increase the output voltage. This may exceed the target value under heavy load by a large margin, resulting in a large overshoot and worsening the transient response when switching from light load to heavy load. This is an undesirable but unavoidable problem of this compensation method.

[0058] Furthermore, to address the aforementioned issues, this embodiment proposes a voltage overshoot suppression circuit, which includes: a ripple injection module 100, a drop detection module 200, a first trigger 300, and a filter adjustment module 400.

[0059] It should be noted that, referring to Figure 3 The drop detection module 200 is connected to the first trigger 300; the first trigger 300 is also connected to the filter adjustment module 400; the filter adjustment module 400 is also connected to the ripple injection module 100; the ripple injection module 100 is connected to the external conversion circuit 500.

[0060] The ripple injection module 100 is used to output a first ripple signal and a second ripple signal based on the voltage at the switching node in the external conversion circuit 500.

[0061] It should be noted that the ripple injection module 100 monitors the voltage of the switching node (SW) in the external conversion circuit 500 and generates two ripple signals through a voltage divider resistor network: the first ripple signal (SW_RC1) reflects the real-time change of the inductor current and includes both DC and AC ripple. The second ripple signal (SW_RC2) is the output voltage at a specific ratio after processing by a second-order filter. The phase difference of the signals is related to the filtering time constant and directly affects the transient response characteristics.

[0062] The drop detection module 200 is used to receive the output feedback voltage generated by the external conversion circuit 500, and generate a high-level signal when the output feedback voltage reaches a preset ratio of the reference voltage.

[0063] It should be understood that the drop detection module 200 receives the output feedback voltage (VFB) from the external conversion circuit 500 and compares it with 98% of a preset reference voltage (VREF). When the output feedback voltage drops below 98% of the reference voltage, a low-level signal is output; when the voltage rises back above 98%, a high-level signal (VO_DROPB) is output. This signal triggers subsequent logic control.

[0064] The first trigger 300 is used to receive the high-level signal and convert it into a first output signal to the filter adjustment module 400.

[0065] It should be noted that the first flip-flop 300 adopts a D-type flip-flop structure. When the VO_DROPB signal rises (output feedback voltage recovers), it latches the high level at the input terminal to the output terminal (Q) and maintains this state until the reset signal arrives. Q serves as a control flag bit, determining the intervention timing of the filter adjustment module 400.

[0066] The filter adjustment module 400 is used to adjust the time constant of the two ripple signals according to the first output signal, so that the external conversion circuit 500 can suppress the overshoot of the output feedback voltage according to the adjusted two ripple signals.

[0067] It should be understood that when the first output signal is high, the filter resistor in the ripple injection module 100 is short-circuited (equivalent to the fourth resistor R4 in the following text), reducing the time constant of SW_RC2 so that it decays synchronously with SW_RC1, thus avoiding negative ripple injection caused by SW_RC1 being lower than SW_RC2. When the first output signal is low, the filter resistor is restored to maintain normal filtering characteristics and ensure that the ripple amplitude is reasonable under steady state.

[0068] It should be noted that the adjusted SW_RC2 affects the power transistor control logic as follows: when SW_RC1 and SW_RC2 are matched, the conduction of the upper transistor (S1) is suppressed, reducing the number of switching operations, thereby reducing the output voltage overshoot and optimizing the transient response.

[0069] In this embodiment, the voltage overshoot suppression circuit includes: a ripple injection module 100, a drop detection module 200, a first trigger 300, and a filter adjustment module 400; the drop detection module 200 is connected to the first trigger 300; the first trigger 300 is also connected to the filter adjustment module 400; the filter adjustment module 400 is also connected to the ripple injection module 100; the ripple injection module 100 is connected to an external conversion circuit 500; the ripple injection module 100 is used to output a first ripple based on the voltage at the switching node in the external conversion circuit 500. The signal and the second ripple signal; the drop detection module 200 is used to receive the output feedback voltage generated by the external conversion circuit 500, and generate a high-level signal when the output feedback voltage reaches a preset ratio of the reference voltage; the first trigger 300 is used to receive the high-level signal and convert it into a first output signal to the filter adjustment module 400; the filter adjustment module 400 is used to adjust the time constant of the second ripple signal according to the first output signal, so that the external conversion circuit 500 suppresses the output feedback voltage overshoot according to the adjusted second ripple signal. The filter adjustment module 400 adjusts the time constant of the second ripple signal according to the first output signal, so that the time constant of the second ripple signal matches the first ripple signal, avoiding the situation in the prior art where the first ripple signal is lower than the second ripple signal due to the slow decline of the second ripple signal, thus injecting negative ripple, thereby suppressing unnecessary conduction of the power transistor in the external conversion circuit 500, reducing the number of switching, and finally solving the output voltage overshoot problem of the COT control mode BUCK converter when switching from light load to heavy load. Compared with the prior art, it achieves the effect of enhancing the transient response of the system.

[0070] Reference Figure 4 , Figure 4 This is a schematic diagram of a second embodiment of the voltage overshoot suppression circuit proposed in this application. Based on the first embodiment of the voltage overshoot suppression circuit described above, a second embodiment of the voltage overshoot suppression circuit of this application is proposed.

[0071] The voltage overshoot suppression circuit also includes a cycle counting module 600.

[0072] It should be noted that the cycle counting module 600 is connected to the first trigger 300. The cycle counting module 600 and the first trigger 300 are directly connected to form a closed-loop control link. Its core function is to accurately define the intervention time period of the filter adjustment module 400, so as to avoid the degradation of steady-state performance caused by continuous adjustment.

[0073] The cycle counting module 600 is used to take the moment when the first output signal is received as the starting point of the adjustment cycle.

[0074] It should be understood that when the high-level signal (VO_DROPB) output by the drop detection module 200 triggers the first flip-flop 300, the flip-flop output Q turns high. The cycle counting module 600 synchronously captures the rising edge of the Q signal, marks this moment as the start of the adjustment cycle, and starts the internal counting logic.

[0075] The cycle counting module 600 is also used to output a reset signal to the first trigger 300 when the rising edge of the fourth PWM signal after receiving the first output signal arrives, and to take this moment as the end of the adjustment cycle.

[0076] It should be understood that the cycle counting module 600 continuously monitors the PWM signal generated by the external PWM signal controller. Each time a rising edge of a PWM signal is detected, the internal counter increments once. When the fourth rising edge of the PWM signal is detected, the end of the adjustment cycle is determined, and a reset signal is immediately output.

[0077] The first trigger 300 is also used to receive the reset signal and convert it into a second output signal to the filter adjustment module 400.

[0078] It should be noted that after the first trigger 300 receives the reset signal output by the cycle counting module 600, its output terminal Q changes from high level to low level. This low-level signal (second output signal) is synchronously transmitted to the filter adjustment module 400 as a termination command for the adjustment action.

[0079] The filter adjustment module 400 is also used to adjust the time constant of the two-ripple signal according to the second output signal.

[0080] It should be understood that the filter adjustment module 400 switches its operating mode according to the first output signal and the second output signal: when Q is high: the filter resistor is short-circuited to accelerate the SW_RC2 signal drop and suppress overshoot; when Q is low: the filter resistor is reconnected to restore the filter time constant under steady state and ensure the ripple amplitude and loop stability under normal load.

[0081] It should be noted that when the output feedback voltage rises again from below 98% of the reference voltage to 98% of the reference voltage, the drop detection module 200 re-triggers the VO_DROPB high level, initiating a new adjustment cycle. The cycle counting module 600, the trigger, and the filter adjustment module 400 work together to reproduce the above process, forming an adaptive closed-loop control.

[0082] The ripple injection module 100 includes: a voltage divider unit 110, a first ripple unit 120, and a second ripple unit 130; the voltage divider unit 110 is connected to the conversion module, the first ripple unit 120, and the second ripple unit 130 respectively; the second ripple unit 130 is also connected to the filter adjustment unit.

[0083] It should be understood that the ripple injection module 100 consists of a voltage divider unit 110, a first ripple unit 120, and a second ripple unit 130. The voltage divider unit 110 serves as an input interface, connecting to the switch node (SW) of an external conversion module, and simultaneously transmitting the divided signal in parallel to the first ripple unit 120 and the second ripple unit 130. The output of the second ripple unit 130 is further connected to a filter adjustment unit, forming a signal processing link.

[0084] The voltage divider unit 110 is used to divide the voltage at the switching node in the external conversion circuit 500 and transmit it to the first ripple unit 120 and the second ripple unit 130.

[0085] It should be understood that the voltage divider unit 110 divides the high voltage at the switching node through a resistor network, generating a voltage signal with reduced amplitude that is proportional to the high voltage at the switching node. The divided signal must meet the input voltage range requirements of the subsequent ripple unit, while maintaining phase consistency with the original SW voltage.

[0086] The first ripple unit 120 is used to generate the first ripple signal based on the node voltage after voltage division.

[0087] It is important to understand that the first ripple unit 120 receives the divided SW voltage and generates the first ripple signal (SW_RC1). This signal is in phase with the inductor current and contains harmonic components of the switching frequency, used to reflect the instantaneous changes in the load current.

[0088] The second ripple unit 130 is used to generate the second ripple signal based on the node voltage after voltage division.

[0089] It should be understood that the second ripple unit 130 also uses the divided SW voltage as input to generate a second ripple signal (SW_RC2). This signal is a specific ratio of the output voltage, and its rate of change is significantly slower than SW_RC1, used for steady-state loop compensation.

[0090] It is worth noting that when the output feedback voltage is detected to rise from a set value lower than the reference voltage to the set value, the filter adjustment unit generates a filter time constant of SW_RC2 to force its descent speed to match that of SW_RC1, thereby avoiding negative ripple injection caused by mismatch between the two.

[0091] In this embodiment, the transient response performance of the COT control mode BUCK converter is significantly improved through the coordinated optimization of the cycle counting module 600 and the ripple injection module 100. The cycle counting module 600 precisely defines the adjustment period, ending at the rising edge of the fourth PWM signal, avoiding excessive intervention by the filter adjustment module 400 that could lead to deterioration of steady-state performance, while ensuring rapid suppression of output voltage overshoot during light load to heavy load transitions. The ripple injection module 100 extracts the switching node voltage through the voltage divider unit 110, generating the SW_RC1 signal reflecting the transient change in inductor current and the SW_RC2 signal representing a specific proportion of the output voltage. When the output feedback voltage is detected to rise from a set value lower than the reference voltage to the set value, the filter adjustment module 400 reduces the filtering time constant of SW_RC2 according to the trigger signal, making its descent speed match that of SW_RC1, eliminating the risk of negative ripple injection, and balancing transient response speed and steady-state accuracy.

[0092] Reference Figure 5 and Figure 6 , Figure 5 This is a circuit connection diagram of the third embodiment of the voltage overshoot suppression circuit proposed in this application; Figure 6 This is a light-load transition heavy-load waveform diagram in the third embodiment of the voltage overshoot suppression circuit proposed in this application. Based on the first and second embodiments of the voltage overshoot suppression circuit described above, a third embodiment of the voltage overshoot suppression circuit of this application is proposed.

[0093] It should be noted that, Figure 5 In this context, `reset` is the reset signal, and `RES_ADJ` is the signal output by the selector MUX.

[0094] The cycle counting module 600 includes: a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4, and a first inverter INV1.

[0095] It should be noted that the first terminal of the second flip-flop DFF2 is connected to the fourth terminal and the second terminal of the third flip-flop DFF3; the second terminal of the second flip-flop DFF2 is connected to an external PWM signal controller; the third terminal of the second flip-flop DFF2 is connected to the third terminal of the third flip-flop DFF3, the third terminal of the fourth flip-flop DFF4, and the fifth terminal of the first flip-flop 300; the first terminal of the third flip-flop DFF3 is connected to the fourth terminal; the fourth terminal of the third flip-flop DFF3 is also connected to the second terminal of the fourth flip-flop DFF4; the first terminal of the fourth flip-flop DFF4 is connected to the fourth terminal, the fifth terminal, and the first terminal of the first inverter INV1; the second terminal of the first inverter INV1 is connected to the third terminal of the first flip-flop 300.

[0096] It should be understood that the first terminal of the first flip-flop 300 to the fourth flip-flop DFF4 is the D terminal, the second terminal is the CLK terminal, the third terminal is the Reset terminal, the fourth terminal is the QB terminal, and the fifth terminal is the Q terminal.

[0097] The voltage divider unit 110 includes: a first voltage divider resistor Rsw1 and a second voltage divider resistor Rsw2.

[0098] It should be noted that the resistance ratio of the first voltage divider resistor Rsw1 and the second voltage divider resistor Rsw2 is 3:1. The first terminal of the first voltage divider resistor Rsw1 is connected to the external conversion circuit 500, and the second terminal of the first voltage divider resistor Rsw1 is connected to the first terminal of the second voltage divider resistor Rsw2, the first ripple unit 120, and the second ripple unit 130; the second terminal of the second voltage divider resistor Rsw2 is grounded.

[0099] The first ripple unit 120 includes: a first resistor R1, a second resistor R2, and a first capacitor C1.

[0100] It should be noted that the first end of the first resistor R1 is connected to the voltage divider unit 110 and the first end of the second resistor R2, and the second end of the first resistor R1 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the first end of the first capacitor C1 and the external conversion circuit 500; the second end of the first capacitor C1 is grounded.

[0101] The second ripple unit 130 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a third capacitor C3.

[0102] It should be understood that the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the filter adjustment module 400; the second end of the fourth resistor R4 is connected to the filter module, the first end of the second capacitor C2 and the first end of the fifth resistor R5; the second end of the fifth resistor R5 is connected to the first end of the third capacitor C3 and the external conversion circuit 500; the second end of the second capacitor C2 is grounded; the second end of the third capacitor C3 is grounded.

[0103] The filter adjustment module 400 includes a selector MUX and a switching transistor Mc.

[0104] It should be noted that the input terminal of the selector MUX is connected to the fifth terminal of the first flip-flop 300, and the output terminal of the selector MUX is connected to the gate of the switching transistor Mc; the drain of the switching transistor Mc is connected to the first terminal of the fourth resistor R4, and the source of the switching transistor Mc is connected to the second terminal of the fourth resistor R4.

[0105] The drop detection module 200 includes: a first MOSFET Q1 to a seventh MOSFET Q7, a second inverter INV2 and a third inverter INV3.

[0106] It should be understood that the gate of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2, the source of the first MOSFET Q1 is grounded, and the drain of the first MOSFET Q1 is connected to the drain of the fourth MOSFET Q4; the source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 is connected to the drain of the fifth MOSFET Q5 and the gate of the third MOSFET Q3; the source of the third MOSFET Q3 is grounded, and the drain of the third MOSFET Q3 is connected to the first terminal of the second inverter INV2 and the drain of the seventh MOSFET Q7; the gate of the fourth MOSFET Q4 receives the reference voltage; the source of the fourth MOSFET Q4 is connected to the source of the fifth MOSFET Q5 and the drain of the sixth MOSFET Q6; the gate of the fifth MOSFET Q5 receives the output feedback voltage; the gate of the sixth MOSFET Q6 is connected to the gate of the seventh MOSFET Q7, and the source of the sixth MOSFET Q6 is connected to the external power supply (VDD) and the source of the seventh MOSFET Q7.

[0107] In this embodiment, the entire control and adjustment process is as follows:

[0108] When the output voltage drops, and the output feedback voltage (connected to the gate of the fifth MOSFET Q5) is lower than the set value of the reference voltage (connected to the gate of the fourth MOSFET Q4), the differential pair formed by the fourth MOSFET Q4 and the fifth MOSFET Q5 changes its conduction state. The drain voltage of the fifth MOSFET Q5 rises, and the drain voltage of the third MOSFET Q3 falls accordingly. After being shaped by inverters INV2 and INV3, the output VO_DROPB is low. When the output feedback voltage is higher than the set value of the reference voltage, the differential pair formed by the fourth MOSFET Q4 and the fifth MOSFET Q5 changes its conduction state. The drain voltage of the fifth MOSFET Q5 falls, and the drain voltage of the third MOSFET Q3 rises accordingly. After being shaped by inverters INV2 and INV3, the output VO_DROPB is high, triggering the first flip-flop 300 to mark a load surge event.

[0109] The high-level VO_DROPB signal triggers the first flip-flop 300 to output a high level (Q terminal), which is synchronously transmitted to the second flip-flop DFF2 to the fourth flip-flop DFF4 of the cycle counting module 600. The second flip-flop DFF2, triggered by the rising edge of the PWM signal output from the external PWM signal controller, transmits the signal through the cascaded third flip-flop DFF3 and fourth flip-flop DFF4. When the fourth flip-flop DFF4 detects the fourth rising edge of the PWM signal, its first terminal outputs a high level, which is inverted by the first inverter INV1 to generate a reset signal, transmitted to the third terminal of the first flip-flop 300, forcing its Q terminal to go low. This process sets the moment when V0_DROPB changes from low to high as the start of the adjustment period and the moment of the fourth rising edge of the PWM signal as the end point, forming a precise timing control window.

[0110] During the high level period at the 300Q terminal of the first flip-flop (within the adjustment cycle), the selector MUX receives the signal LG_LV controlling the conduction of the lower transistor and outputs it to the gate of the switching transistor Mc, turning on the switching transistor Mc. The drain and source of the switching transistor Mc are shorted across the fourth resistor R4, effectively bypassing the fourth resistor R4. At this time, the filtering time constant of the second ripple unit 130 decreases (because the fourth resistor R4 is short-circuited), the SW_RC2 signal falls faster, matching the falling slope of the SW_RC1 signal, avoiding negative ripple injection into the output voltage due to mismatch between the two, thereby suppressing overshoot. When the adjustment cycle ends (the 300Q terminal of the first flip-flop goes low), the switching transistor Mc turns off, the fourth resistor R4 is reconnected to the circuit, and the steady-state filtering time constant is restored.

[0111] After the reset signal ends the adjustment cycle, the first flip-flop 300Q remains low, and the cycle counting module 600 and the filter adjustment module 400 stop their special operations. The system returns to the normal COT control mode, relying on the steady-state relationship between SW_RC1 and SW_RC2 to maintain stable output voltage until the next load surge triggers a new cycle.

[0112] In addition, this application also proposes a COT control mode BUCK converter system, referring to Figure 7 , Figure 7 This is a circuit connection diagram of the COT control mode BUCK converter system proposed in this application. The COT control mode BUCK converter system includes the voltage overshoot suppression circuit described above.

[0113] Since the COT control mode BUCK converter system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0114] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0115] The above are merely preferred embodiments of this application and do not limit the scope of this application. Any equivalent structural or procedural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the protection scope of this application.

Claims

1. A voltage overshoot suppression circuit, characterized in that, The voltage overshoot suppression circuit includes: a ripple injection module, a drop detection module, a first trigger, and a filter adjustment module; The drop detection module is connected to the first trigger; the first trigger is also connected to the filter adjustment module; the filter adjustment module is also connected to the ripple injection module; the ripple injection module is connected to an external conversion circuit. The ripple injection module is used to output a first ripple signal and a second ripple signal according to the voltage at the switching node in the external conversion circuit. The drop detection module is used to receive the output feedback voltage generated by the external conversion circuit, and generate a high-level signal when the output feedback voltage rises to a preset ratio of the reference voltage. The first trigger is used to receive the high-level signal and convert it into a first output signal to the filter adjustment module; The filtering and adjustment module is used to adjust the time constant for generating the second ripple signal according to the first output signal, so that the external conversion circuit can suppress the overshoot of the output feedback voltage according to the adjusted second ripple signal. The voltage overshoot suppression circuit further includes: a period counting module; The period counting module is connected to the first trigger; The cycle counting module is used to take the moment when the first output signal is received as the starting point of the adjustment cycle; The cycle counting module is also used to output a reset signal to the first trigger when the rising edge of the fourth PWM signal after receiving the first output signal arrives, and to take this moment as the end of the adjustment cycle. The first trigger is also used to receive the reset signal and convert it into a second output signal to the filter adjustment module; The filtering adjustment module is also used to adjust the time constant for generating the second ripple signal according to the second output signal.

2. The voltage overshoot suppression circuit as described in claim 1, characterized in that, The cycle counting module includes: a second flip-flop, a third flip-flop, a fourth flip-flop, and a first inverter; The first terminal of the second flip-flop is connected to the fourth terminal and the second terminal of the third flip-flop. The second terminal of the second flip-flop is connected to an external PWM signal controller. The third terminal of the second flip-flop is connected to the third terminal of the third flip-flop, the third terminal of the fourth flip-flop, and the fifth terminal of the first flip-flop. The first terminal of the third flip-flop is connected to the fourth terminal; the fourth terminal of the third flip-flop is also connected to the second terminal of the fourth flip-flop; the first terminal of the fourth flip-flop is connected to the fourth terminal, the fifth terminal, and the first terminal of the first inverter; the second terminal of the first inverter is connected to the third terminal of the first flip-flop. The first terminal of the first to fourth flip-flops is the D terminal, the second terminal is the CLK terminal, the third terminal is the Reset terminal, the fourth terminal is the QB terminal, and the fifth terminal is the Q terminal.

3. The voltage overshoot suppression circuit as described in claim 1, characterized in that, The ripple injection module includes: a voltage divider unit, a first ripple unit, and a second ripple unit; The voltage divider unit is connected to the external conversion circuit, the first ripple unit, and the second ripple unit respectively; the second ripple unit is also connected to the filter adjustment module. The voltage divider unit is used to divide the voltage at the switching node in the external conversion circuit and transmit it to the first ripple unit and the second ripple unit. The first ripple unit is used to generate the first ripple signal based on the node voltage after voltage division; The second ripple unit is used to generate the second ripple signal based on the node voltage after voltage division.

4. The voltage overshoot suppression circuit as described in claim 3, characterized in that, The voltage divider unit includes: a first voltage divider resistor and a second voltage divider resistor; The first end of the first voltage divider resistor is connected to the external conversion circuit, and the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the first ripple unit, and the second ripple unit; the second end of the second voltage divider resistor is grounded.

5. The voltage overshoot suppression circuit as described in claim 3, characterized in that, The first ripple unit includes: a first resistor, a second resistor, and a first capacitor; The first end of the first resistor is connected to the voltage divider unit, and the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is connected to the first end of the first capacitor and the external conversion circuit; the second end of the first capacitor is grounded.

6. The voltage overshoot suppression circuit as described in claim 3, characterized in that, The second ripple unit includes: a third resistor, a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor; The second end of the third resistor is connected to the first end of the fourth resistor and the filter adjustment module; the second end of the fourth resistor is connected to the filter adjustment module, the first end of the second capacitor and the first end of the fifth resistor; the second end of the fifth resistor is connected to the first end of the third capacitor and the external conversion circuit; the second end of the second capacitor is grounded; the second end of the third capacitor is grounded.

7. The voltage overshoot suppression circuit as described in claim 6, characterized in that, The filter adjustment module includes: a selector and a switching transistor; The input terminal of the selector is connected to the fifth terminal of the first flip-flop, and the output terminal of the selector is connected to the gate of the switching transistor; the drain of the switching transistor is connected to the first terminal of the fourth resistor, and the source of the switching transistor is connected to the second terminal of the fourth resistor.

8. The voltage overshoot suppression circuit as described in claim 1, characterized in that, The drop detection module includes: a first MOSFET to a seventh MOSFET, a second inverter, and a third inverter; The gate of the first MOSFET is connected to the drain of the second MOSFET, the source of the first MOSFET is grounded, and the drain of the first MOSFET is connected to the drain of the fourth MOSFET. The source of the second MOSFET is grounded, and the drain of the second MOSFET is connected to the drain of the fifth MOSFET and the gate of the third MOSFET. The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is connected to the first terminal of the second inverter and the drain of the seventh MOS transistor. The gate of the fourth MOS transistor receives the reference voltage; the source of the fourth MOS transistor is connected to the source of the fifth MOS transistor and the drain of the sixth MOS transistor. The gate of the fifth MOS transistor receives the output feedback voltage; The gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor, and the source of the sixth MOS transistor is connected to an external power supply and the source of the seventh MOS transistor. The first terminal of the third inverter is connected to the second terminal of the second inverter, and the second terminal of the third inverter is connected to the first trigger.

9. A COT control mode BUCK converter system, characterized in that, The system includes a voltage overshoot suppression circuit as described in any one of claims 1 to 8.

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