A control method of a photolithography machine, the photolithography machine, and a computer readable storage medium

Abstract

The application provides a photolithography machine and a control method thereof and a computer readable storage medium. The control method comprises: judging whether a silicon wafer currently located on a workpiece table is a first silicon wafer of a current batch, if yes, controlling the workpiece table to move and sequentially performing a table leveling operation, a table alignment operation, a silicon wafer leveling operation, a silicon wafer coarse alignment operation and a silicon wafer fine alignment operation; if no, judging whether to perform the table leveling operation and / or the table alignment operation based on a preset condition and judging an execution timing of the table alignment operation, and controlling the workpiece table to move according to a judgment result to at least perform the silicon wafer leveling operation, the silicon wafer coarse alignment operation and the silicon wafer fine alignment operation. The execution of the method takes into account the photolithography precision and yield of the photolithography machine.

Description

Technical Field

[0001] This invention belongs to the field of lithography machine technology, specifically relating to a control method for a lithography machine, a lithography machine, and a computer-readable storage medium. Background Technology

[0002] When performing photolithography on silicon wafers using a photolithography machine, steps such as loading materials, measuring and adjusting the material orientation are required before exposure in order to accurately transfer the pattern on the photomask onto the silicon wafer. To improve the productivity of the photolithography machine, the workflow should be optimized as much as possible, and the operation time of each step should be shortened.

[0003] Existing lithography machines include dual-stage and single-stage lithography machines. Dual-stage lithography machines allow one stage to perform pre-exposure measurements while the other stage carries the pre-measured and adjusted silicon wafer for exposure, maximizing yield. However, dual-stage lithography machines have a large footprint, high cost, and require high precision in their assembly; therefore, they are rarely considered for applications where the critical dimensions of the silicon wafer are greater than 300nm. For single-stage lithography, within the same batch of silicon wafers, without changing the mask, the wafers must undergo at least wafer leveling and alignment after loading before finally being exposed. The specific operations are as follows: Figure 1 As shown, it includes:

[0004] Step S1: Determine whether the silicon wafer currently on the workpiece stage is the first silicon wafer of the current batch. If yes, proceed with steps S2 to S8 in sequence. If no, proceed with steps S4 to S8 in sequence.

[0005] Step S2: Based on the leveling point in the machine constant, control the movement of the workpiece table to perform the leveling operation.

[0006] Step S3: Based on the stage alignment point in the machine constant, control the movement of the workpiece stage to perform the stage alignment operation.

[0007] Step S4: Based on the silicon wafer leveling point in the machine constant, control the movement of the workpiece stage to perform the silicon wafer leveling operation.

[0008] Step S5: Based on the coarse alignment position of the silicon wafer in the machine constant, control the movement of the workpiece stage to perform the coarse alignment operation of the silicon wafer;

[0009] Step S6: Based on the silicon wafer precision alignment position in the machine constant, control the workpiece stage movement to perform the silicon wafer precision alignment operation;

[0010] Step S7: Based on the mask alignment position in the machine constant, control the movement of the workpiece stage to perform the mask alignment operation.

[0011] Step S8: Based on the exposure position in the machine constant, control the movement of the workpiece stage to perform the exposure operation.

[0012] The above operation determines whether stage leveling and alignment are needed based solely on whether the silicon wafer currently on the workpiece stage is the first wafer of the current batch. By default, if the silicon wafer is not the first wafer of the current batch, stage leveling and alignment are not required. However, if the silicon wafer on the workpiece stage is not among the first wafers of the current batch, but the stage zero point deviates from the preset range due to inadequate environmental control or other reasons, the stage leveling and alignment will not be re-executed before exposing the current wafer, resulting in low overlay accuracy. Furthermore, in existing lithography operations, the order of steps S1 to S8 is fixed and cannot be adjusted according to actual working conditions, potentially preventing the lithography machine from achieving optimal yield. Summary of the Invention

[0013] The purpose of this invention is to provide a control method for a lithography machine, as well as a lithography machine and a computer-readable storage medium, aiming to improve the yield of the lithography machine while ensuring lithography accuracy.

[0014] To achieve the above objectives, the present invention provides a control method for a lithography machine, comprising:

[0015] Determine whether the silicon wafer currently on the workpiece stage of the lithography machine is the first silicon wafer of the current batch;

[0016] If so, control the movement of the workpiece stage and sequentially execute the stage leveling operation, stage alignment operation, silicon wafer leveling operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation;

[0017] If not, determine whether to perform stage leveling and / or stage alignment operations based on preset conditions, and determine the relative order of stage alignment and silicon wafer leveling operations. Control the movement of the workpiece stage based on the determination result to perform at least silicon wafer leveling, silicon wafer coarse alignment, and silicon wafer fine alignment operations.

[0018] Optionally, the preset conditions include a first sub-preset condition, a second sub-preset condition, and a third sub-preset condition;

[0019] The steps of determining whether to perform stage leveling and stage alignment operations, determining the relative order of stage alignment and silicon wafer leveling operations, and controlling the movement of the workpiece stage based on the determination results to perform at least silicon wafer leveling, silicon wafer coarse alignment, and silicon wafer fine alignment operations include:

[0020] Determine whether the current operating condition meets the first sub-preset condition;

[0021] If the current working condition meets the first sub-preset condition, then control the movement of the workpiece stage and sequentially execute the stage leveling operation, silicon wafer leveling operation, stage alignment operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation;

[0022] If the current working condition does not meet the first sub-preset condition, then determine whether the current working condition meets the second sub-preset condition and whether the current working condition meets the third sub-preset condition.

[0023] If the current working condition meets the second sub-preset condition, the workpiece table is controlled to move to perform a table leveling operation; if the current working condition does not meet the second sub-preset condition, the table leveling operation is skipped.

[0024] If the current working condition meets the third sub-preset condition, the workpiece stage is controlled to move to perform the stage alignment operation; if the current working condition does not meet the third sub-preset condition, the stage alignment operation is skipped.

[0025] Then, the workpiece stage is controlled to move and the silicon wafer leveling operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation are executed in sequence.

[0026] Optionally, the step of determining whether the current working condition meets the first sub-preset condition includes: determining whether the target parameter is greater than the first threshold; if yes, then determining that the current working condition meets the first sub-preset condition; if no, then determining that the current working condition does not meet the first sub-preset condition.

[0027] Optionally, the target parameter includes a key dimension of the silicon wafer, and the first threshold includes a preset dimension; and / or, the target parameter includes the depth of focus of the silicon wafer alignment sensor of the lithography machine, and the first threshold includes a preset depth of focus;

[0028] When the target parameters include the critical dimensions of the silicon wafer and the depth of focus of the silicon wafer alignment sensor, the target parameters being greater than the first threshold means that the critical dimensions of the silicon wafer are greater than the preset dimensions and / or the depth of focus of the silicon wafer alignment sensor is greater than the preset depth of focus.

[0029] Optionally, the step of determining whether the current operating condition meets the second sub-preset condition includes:

[0030] When the exposure operation on the previous silicon wafer is completed, it is determined whether the offset of the zero position of the workpiece stage in the vertical direction relative to the stage leveling point on the reference plate of the lithography machine is greater than the second threshold. If yes, the current working condition is determined to meet the second sub-preset condition. If no, the current working condition is determined to not meet the second sub-preset condition.

[0031] Optionally, the step of determining whether the current operating condition meets the third sub-preset condition includes:

[0032] When the exposure operation on the previous silicon wafer is completed, it is determined whether the offset of the zero position of the workpiece stage in the horizontal direction relative to the stage alignment point on the reference plate of the lithography machine is greater than the fourth threshold. If yes, the current working condition is determined to meet the third sub-preset condition. If no, the current working condition is determined to not meet the third sub-preset condition.

[0033] Optionally, the silicon wafer is pre-set with multiple silicon wafer leveling points, two silicon wafer coarse alignment points, and multiple silicon wafer fine alignment points; the multiple silicon wafer leveling points are distributed at equal intervals on a first circle and arranged in a first direction; the two silicon wafer coarse alignment points are distributed at equal intervals on a second circle and arranged in a second direction; the multiple silicon wafer fine alignment points are distributed at equal intervals on the second circle and arranged in a third direction; the second silicon wafer coarse alignment point coincides with the first silicon wafer fine alignment point, and the first silicon wafer coarse alignment point coincides with another silicon wafer fine alignment point;

[0034] In a specified coordinate system, the center of the first circle is the center of the objective lens of the lithography machine, and the ratio of the radius of the first circle to the radius of the silicon wafer is a preset value; the center of the second circle is the center of the silicon wafer alignment sensor of the lithography machine, and the ratio of the radius of the second circle to the radius of the silicon wafer is the preset value; the preset value is greater than or equal to 0.65 and less than or equal to 0.8;

[0035] The silicon wafer leveling operation includes the workpiece stage moving and passing through all the silicon wafer leveling points in sequence according to the order; the silicon wafer alignment operation includes the workpiece stage moving and passing through two silicon wafer coarse alignment points in sequence according to the order, and then passing through all the silicon wafer fine alignment points in sequence according to a third predetermined order.

[0036] Optionally, when the stage alignment operation is performed before the silicon wafer leveling operation, the first silicon wafer leveling point is the intersection of the line connecting the stage alignment point on the reference plate of the lithography machine and the center of the objective lens with the first circle near the stage alignment point, and the last silicon wafer leveling point is closer to the second circle than the second silicon wafer leveling point; the two silicon wafer coarse alignment points are the two intersections of the line connecting the last silicon wafer leveling point and the center of the silicon wafer alignment sensor with the second circle, and the first silicon wafer coarse alignment point is closer to the last silicon wafer leveling point than the second silicon wafer coarse alignment point; the last silicon wafer fine alignment point is closer to the first circle than the second silicon wafer fine alignment point;

[0037] The first direction is opposite to the third direction, and the second direction refers to the direction from the last silicon wafer leveling point to the center of the silicon wafer alignment sensor.

[0038] Optionally, when the silicon wafer leveling operation is performed before the stage alignment operation, the first silicon wafer leveling point is the intersection of the line connecting the stage alignment point on the lithography machine's reference plate and the center of the objective lens with the first circle near the stage alignment point; the last silicon wafer leveling point is closer to the second circle than the second silicon wafer leveling point; the two silicon wafer coarse alignment points are the two intersections of the line connecting the stage alignment point on the lithography machine's reference plate and the center of the silicon wafer sensor with the second circle, and the coarse alignment point adjacent to the stage alignment point is the first coarse alignment point; the last silicon wafer fine alignment point is closer to the first circle than the second silicon wafer fine alignment point.

[0039] The first direction is the same as the third direction, and the second direction refers to the direction from the stage alignment point to the center of the silicon wafer alignment sensor.

[0040] To achieve the above objectives, the present invention also provides a computer-readable storage medium having a program stored thereon, which, when executed, performs the control method for the lithography machine as described above.

[0041] To achieve the above objectives, the present invention also provides a lithography machine, including a workpiece stage, a driving mechanism, an exposure system, and a control unit. The driving mechanism is drive-connected to the workpiece stage, and the control unit is communicatively connected to the driving mechanism and the exposure system. The control unit is configured to execute the control method of the lithography machine as described above.

[0042] Compared with the prior art, the control method for the lithography machine, the lithography machine, and the computer-readable storage medium of the present invention have the following advantages:

[0043] The aforementioned control method for the lithography machine includes: determining whether the silicon wafer currently on the workpiece stage of the lithography machine is the first silicon wafer of the current batch; if so, controlling the workpiece stage to move and sequentially performing stage leveling, stage alignment, wafer leveling, coarse alignment, and fine alignment operations; if not, determining whether to perform stage leveling and / or stage alignment operations based on preset conditions, and determining the relative order of stage alignment and wafer leveling operations, and controlling the workpiece stage to move according to the determination result, so as to perform at least wafer leveling, coarse alignment, and fine alignment operations. This method ensures that when exposing each silicon wafer, the zero position of the workpiece stage is within a preset range, preventing low overlay accuracy due to deviation of the workpiece stage's zero position from the preset range. Furthermore, while determining the execution of stage leveling and alignment operations, the relative order of stage alignment and wafer leveling operations is also determined based on the actual working conditions to balance the lithography accuracy and yield of the lithography machine. Attached Figure Description

[0044] The accompanying drawings are provided to better understand the invention and are not intended to unduly limit the scope of the invention. Wherein:

[0045] Figure 1 This is a schematic diagram of the control method of a lithography machine performed by a lithography machine in the existing technology;

[0046] Figure 2 This is a schematic diagram of the hardware structure of a lithography machine;

[0047] Figure 3 This is a detailed flowchart of a control method for a lithography machine according to an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram showing the distribution of workpiece stage positions in a lithography machine control method according to an embodiment of the present invention. The movement path of the workpiece stage is also shown by a dashed line with an arrow in the figure.

[0049] Figure 5 This is a schematic diagram of the workpiece stage position distribution in the control method of a lithography machine provided according to an embodiment of the present invention. The movement path of the workpiece stage is also shown by a dashed line with an arrow in the figure.

[0050] Figure 6 This is a schematic diagram showing the distribution of relevant positions of the workpiece stage in the prior art;

[0051] Figure 7 When the lithography machine is running, the workpiece stage follows... Figure 6 The diagram shows the motion path of the workpiece stage relative position movement in the prior art. The lithography machine in the diagram first performs a stage alignment operation and then a silicon wafer leveling operation.

[0052] Figure 8 When the lithography machine is running, the workpiece stage is based on Figure 6 The diagram shows the motion path of the workpiece stage in the prior art. In the diagram, the lithography machine first performs a silicon wafer leveling operation and then a stage alignment operation.

[0053] [The annotations in the attached figures are explained below]:

[0054] 10-Mask stage, 20-Objective lens, 30-Workpiece stage, 40-Focusing and leveling alignment sensor, 50-Silicon wafer alignment sensor, 60-Mask alignment sensor;

[0055] 1-Silicon wafer;

[0056] 01-Wafer handover position, 02-Stage leveling point, 03-Stage alignment point, 041, 041'-First wafer leveling point, 042, 042'-Second wafer leveling point, 042, 043'-Third wafer leveling point, 051, 051'-First wafer coarse alignment point, 052, 052'-Second wafer coarse alignment point, 061, 061'-First wafer fine alignment point, 062, 062'-Second wafer fine alignment point, 063, 063'-Third wafer fine alignment point, 064, 064'-Fourth wafer fine alignment point, 065, 065'-Fifth wafer fine alignment point, 066, 066'-Sixth wafer fine alignment point, 071-First mask spatial image point, 072-Second mask spatial image point, 08-Exposure field start position, 09-Exposure field end position. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of components in the actual implementation. In the actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex.

[0058] Furthermore, while each embodiment described below possesses one or more technical features, this does not imply that users of the present invention must simultaneously implement all technical features in any embodiment, or can only separately implement some or all technical features in different embodiments. In other words, provided it is feasible, those skilled in the art can, based on the disclosure of the present invention and depending on design specifications or implementation requirements, selectively implement some or all technical features in any embodiment, or selectively implement a combination of some or all technical features in multiple embodiments, thereby increasing the flexibility in implementing the present invention.

[0059] As used herein, the singular forms “a,” “an,” and “the” include plural objects, and the plural form “a plurality” includes two or more objects, unless otherwise expressly indicated. As used herein, the term “or” is generally used to include the meaning of “and / or,” unless otherwise expressly indicated, and the terms “installed,” “connected,” and “linked” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection. Connections can be mechanical or electrical. Connections can be direct or indirect through an intermediate medium, and can be internal communication between two elements or an interaction between two elements. Relational terms such as “first,” “second,” etc., are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations, nor do they indicate or imply relative importance or implicitly specify the number of indicated technical features. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0060] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. The same or similar reference numerals in the drawings represent the same or similar parts.

[0061] Figure 2 A schematic diagram of the hardware structure of a lithography machine is shown. (For example...) Figure 2 As shown, the lithography machine includes a mask stage 10, an objective lens 20, a workpiece stage 30, a focusing and leveling alignment sensor 40, a silicon wafer alignment sensor 50, a mask alignment sensor 60, a reference plate, an exposure system, and other components. The functions, structures, and arrangements of these components can be referred to in the prior art, and will not be elaborated here.

[0062] One objective of this invention is to provide a control method for a lithography machine, comprising:

[0063] Step S10: Determine whether the silicon wafer 1 currently located on the workpiece stage 30 is the first silicon wafer of the current batch. If the determination result of this step is yes, then proceed to steps S30, S40, S50, S60, and S70 in sequence; if the determination result of this step is no, then proceed to step S20.

[0064] Step S20: Determine whether to execute step S30 and / or step S40 based on preset conditions and determine the relative order of step S40 and step S50, and execute at least step S50, step S60 and step S70 in subsequent operations based on the determination results.

[0065] Step S30: Perform the platform leveling operation.

[0066] Step S40: Stage alignment operation.

[0067] Step S50: Perform silicon wafer leveling operation.

[0068] Step S60: Perform coarse alignment of the silicon wafer.

[0069] Step S70: Perform silicon wafer alignment.

[0070] During the execution of the aforementioned lithography machine control method, not only are stage leveling and alignment operations performed on the first silicon wafer of the current batch, but stage leveling and alignment operations are also selectively performed on non-first silicon wafers based on preset conditions. This avoids performing exposure operations on the silicon wafers if the stage leveling and alignment results of the workpiece stage 30 are unsatisfactory, ensuring the overlay accuracy of silicon wafer 1. Furthermore, the execution order of stage alignment and silicon wafer leveling operations is determined based on preset conditions, and subsequent steps are executed according to the determination result. In this way, the runtime of the lithography machine for each silicon wafer 1 can be shortened as much as possible while maintaining overlay accuracy, thereby improving the productivity of the lithography machine.

[0071] It is understood that after step S70 is completed, the lithography machine can be controlled to execute steps S80 and S90 to complete the lithography operation on silicon wafer 1. Step S80 includes performing a mask alignment operation. Step S90 includes performing an exposure operation. That is, the control method of the lithography machine may also include steps S80 and S90.

[0072] In step S20, while determining whether to execute steps S30 and S40 based on preset conditions, the execution order of steps S40 and S50 is also determined. In other words, determining the execution order of the stage alignment operation and the silicon wafer leveling operation is also determined at the same time.

[0073] In an exemplary embodiment, the preset conditions include a first sub-preset condition, a second sub-preset condition, and a third sub-preset condition. Accordingly, step S20 includes:

[0074] Step S21: Determine whether steps S30 and S40 need to be executed based on the first sub-preset condition.

[0075] Step S22: Determine whether step S30 needs to be executed based on the second sub-preset condition.

[0076] Step S23: Determine whether step S40 needs to be executed based on the third sub-preset condition.

[0077] Whether steps S22 and S23 are executed is determined based on the judgment result of step S21.

[0078] Specifically, step S21 involves determining whether the current operating condition meets the first sub-preset condition. If the current operating condition meets the first sub-preset condition, then steps S30 and S40 are executed, with step S40 executed after step S50, while steps S22 and S23 do not need to be executed. If the current operating condition does not meet the first sub-preset condition, then steps S22 and S23 are executed.

[0079] The operation of step S22 is to determine whether the current operating condition meets the second sub-preset condition. If the current operating condition meets the second sub-preset condition, then it is determined that step S30 should be executed; if the current operating condition does not meet the second sub-preset condition, then it is determined that step S30 does not need to be executed.

[0080] Step S23 involves determining whether the current operating condition meets the third sub-preset condition. If the current operating condition meets the third sub-preset condition, then step S40 is executed; otherwise, step S30 is not executed.

[0081] If the judgment results of steps S22 and S23 are both yes, that is, when it is determined through the judgment of steps S22 and S23 to execute steps S30 and S40, step S30 is executed before step S40.

[0082] Therefore, as Figure 3 As shown, in an exemplary embodiment, when step S10 is completed and the determination result of step S10 is negative, the control method of the lithography machine further includes:

[0083] Step S21: Determine whether the current working condition meets the first sub-preset condition. If yes, control the drive mechanism 70 to run and drive the workpiece stage 30 to move, so as to execute steps S30, S50, S40, S60, S70, S80 and S90 in sequence; if no, execute step S22.

[0084] Step S22: Determine whether the current working condition meets the second sub-preset condition. If yes, first control the drive mechanism 70 to run and drive the workpiece stage 30 to move to execute step S30, and then execute step S23; if no, directly execute step S23.

[0085] Step S23: Determine whether the current working condition meets the third sub-preset condition. If yes, first control the drive mechanism 70 to run and drive the workpiece stage 30 to move to execute step S40, and then execute steps S50, S60, S70, S80 and S90 in sequence; if no, control the drive mechanism 70 to run and drive the workpiece stage 30 to move to execute steps S60, S70, S80 and S90 in sequence.

[0086] It should be noted that although the above description uses the example of executing step S22 first and then step S23, in practice, the embodiments of the present invention do not particularly limit the execution order of step S22 and step S23. Step S22 can be executed synchronously with step S23, or even step S22 can be executed after step S23.

[0087] Optionally, the first sub-preset condition includes a target parameter being greater than a first threshold.

[0088] In some embodiments, the target parameter includes the critical dimension of the silicon wafer 1, and the first threshold includes a preset dimension. Therefore, the specific operation of step S21 is to determine whether the critical dimension of the silicon wafer 1 is greater than the preset dimension. Accordingly, the current operating condition meeting the first sub-preset condition means that the critical dimension of the silicon wafer 1 is greater than the preset dimension.

[0089] In other embodiments, the target parameter includes the focal depth of the silicon wafer alignment sensor 50, and the first threshold includes a preset focal depth. Therefore, step S21 specifically involves determining whether the focal depth of the silicon wafer alignment sensor 50 is greater than the preset focal depth. Accordingly, the current operating condition meeting the first sub-preset condition means that the focal depth of the silicon wafer alignment sensor 50 is greater than the preset focal depth.

[0090] In some embodiments, the target parameters include the critical dimensions of the silicon wafer 1 and the focal depth of the silicon wafer alignment sensor 50, and the first threshold includes the preset size and the preset focal depth. Specifically, step S21 involves determining whether the critical dimension of the silicon wafer 1 is greater than the preset size, and whether the focal depth of the silicon wafer alignment sensor 50 is greater than the preset focal depth. In this case, the current operating condition meeting the first sub-preset condition means that the critical dimension of the silicon wafer 1 is greater than the preset size and / or the focal depth of the silicon wafer alignment sensor 50 is greater than the preset focal depth. Conversely, the current operating condition not meeting the first sub-preset condition means that the critical dimension of the silicon wafer 1 is not greater than the preset size, and the focal depth of the silicon wafer alignment sensor 50 is not greater than the preset focal depth.

[0091] When the current operating condition meets the first sub-preset condition, the reason for controlling step S40 to be executed after step S50 is that when the target parameter is greater than the first threshold, it indicates that the overlay accuracy can be relatively low, and the lithography machine is expected to have a high yield. Therefore, by re-executing steps S30 and S40, the required overlay accuracy is ensured. At the same time, by having step S50 be executed before step S40, the movement path of the workpiece stage 30 can be shortened during the lithography process on the current silicon wafer 1, thereby shortening the lithography time and improving the yield of the lithography machine. It can be understood that the preset size and the preset focal depth are both set according to actual needs, for example, the preset size is greater than 1 μm, and the preset focal depth is greater than 10 μm.

[0092] The second sub-preset condition includes that, when the exposure operation on the previous silicon wafer 1 is completed, the zero position of the workpiece stage 30 is vertically relative to the stage leveling point 02 on the reference plate of the lithography machine (e.g., ...). Figure 4 and Figure 5 The offset (as shown) is greater than the second threshold. Therefore, the operation of step S22 includes determining whether the offset of the zero position of the workpiece stage 30 in the vertical direction relative to the stage leveling point 02 is greater than the second threshold when the previous silicon wafer 1 completed the exposure operation. Correspondingly, the current working condition meets the second sub-preset condition when the previous silicon wafer 1 completed the exposure operation and the offset of the zero position of the workpiece stage 30 in the vertical direction relative to the stage leveling point is greater than the second threshold. The second threshold is less than the third threshold.

[0093] It is understood that during the leveling of the workpiece stage 30, if the zero position of the workpiece stage 30 is exactly located at the leveling point 02 in the vertical direction, or if the zero position of the workpiece stage 30 is not located at the leveling point 02 in the vertical direction but its offset relative to the leveling point 02 is within the third threshold (i.e., less than or equal to the third threshold), the leveling result is considered reliable. However, when the previous silicon wafer 1 has completed its exposure operation, if the offset of the zero position of the workpiece stage 30 in the vertical direction relative to the leveling point 02 is greater than the second threshold but less than the third threshold, it indicates that although the current leveling result is still reliable after the previous silicon wafer 1 has finished its exposure, the offset of the zero position of the workpiece stage 30 in the vertical direction relative to the leveling point 02 is about to reach the third threshold, and it is necessary to correct it to ensure the accuracy of subsequent steps. When the previous silicon wafer 1 completes its exposure operation, if the vertical offset of the zero position of the workpiece stage 30 relative to the stage leveling point 02 is greater than the third threshold, it indicates that the current stage leveling result is unreliable and needs to be readjusted after the previous silicon wafer 1's exposure ends. It should be noted that the control method for the lithography machine provided in this embodiment ensures that, during normal operation, the vertical offset of the zero position of the workpiece stage 30 relative to the stage leveling point 02 on the lithography machine's reference plate will not exceed the third threshold. However, it should be understood that if the lithography machine malfunctions or encounters other unexpected situations, i.e., if the lithography machine is not operating normally, the vertical offset of the zero position of the workpiece stage 30 relative to the stage leveling point 02 on the lithography machine's reference plate may exceed the third threshold.

[0094] The third sub-preset condition includes that when the exposure operation of the previous silicon wafer 1 is completed, the zero position of the workpiece stage 30 is horizontally aligned with the stage alignment point 03 on the reference plate (e.g., ...). Figures 4 to 5 The offset (as shown) is greater than the fourth threshold. Therefore, the operation of step S23 includes determining whether the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage alignment point 03 is greater than the fourth threshold when the previous silicon wafer has been exposed. The current working condition meets the third sub-preset condition, which means that when the previous silicon wafer has been exposed, the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage alignment point is greater than the fourth threshold. The fourth threshold is less than the fifth threshold.

[0095] It is understood that when performing a stage alignment operation on the workpiece stage 30, if the zero position of the workpiece stage 30 is exactly located at the stage alignment point 03 in the horizontal direction, or if the zero position of the workpiece stage 30 is not located at the stage alignment point 03 in the horizontal direction but its offset relative to the stage alignment point 03 is within the fifth threshold (i.e., less than or equal to the fifth threshold), the stage alignment result is considered reliable. However, when the previous silicon wafer 1 completes its exposure operation, if the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage alignment point 03 is greater than the fourth threshold but less than the fifth threshold, it indicates that although the current stage alignment result is still reliable when the previous silicon wafer 1 has finished its exposure, the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage alignment point 03 is about to reach the fifth threshold, and it is necessary to correct it to ensure the accuracy of subsequent steps. When the previous silicon wafer 1 completes its exposure operation, if the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage leveling point 02 is greater than the fifth threshold, it indicates that the current stage alignment result is unreliable and realignment is required after the previous silicon wafer 1's exposure ends. It should be noted that the control method for the lithography machine provided in this embodiment ensures that, during normal operation, the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage leveling point 02 on the lithography machine's reference plate will not exceed the fifth threshold. However, it should be understood that if the lithography machine malfunctions or encounters other unexpected situations, i.e., if the lithography machine is not operating normally, the offset of the zero position of the workpiece stage 30 in the horizontal direction relative to the stage leveling point 02 on the lithography machine's reference plate may exceed the fifth threshold.

[0096] Optionally, the control method of the lithography machine may further include steps S01 and S02 (not shown in the figure). Step S01 includes transferring the silicon wafer 1 to the workpiece stage 30. Step S02 includes transferring the mask to the mask stage 10. For the same batch of silicon wafers 1, the number of times step S01 is executed is equal to the number of silicon wafers 1, and step S02 is executed only once. For the first silicon wafer of the same batch, step S02 can be executed simultaneously with step S01. It can be understood that for the first silicon wafer 1 of the current batch, step S10 and its subsequent steps are executed after steps S01 and S02 are completed; for non-first silicon wafers 1, step S10 and its subsequent steps are executed after step S01 is completed.

[0097] Those skilled in the art will understand that the positions involved in the operation of the lithography machine include mask stage-related positions and workpiece stage-related positions. The mask stage-related positions include the mask plate junction positions. The workpiece stage-related positions include, for example,... Figure 4and Figure 5 The diagram shows the wafer junction position 01, the stage leveling point 02, the stage alignment point 03, the wafer leveling point, the wafer coarse alignment point, the wafer fine alignment point, the mask space image position, the exposure field position, the exposure field start position 08, and the exposure field end position 09. Generally, there are at least three wafer leveling points, generally two wafer coarse alignment points, and multiple wafer fine alignment points, with each wafer coarse alignment point coinciding with one wafer fine alignment point.

[0098] Accordingly, step S01 refers to the workpiece stage 30 moving to the silicon wafer junction position 01 and transferring the silicon wafer 1 to the workpiece stage 30 located at the silicon wafer junction position 01. Step S02 refers to the mask stage 10 moving to the mask plate junction position and transferring the mask plate to the mask stage 10 located at the mask plate junction position. The stage leveling operation refers to the workpiece stage 30 moving to the stage leveling point 02. The stage alignment operation refers to the workpiece stage 30 moving to the stage alignment point 03. The silicon wafer leveling operation refers to the workpiece stage 30 moving and passing through each of the silicon wafer leveling points in a predetermined order. The silicon wafer coarse alignment operation refers to the workpiece stage 30 moving and passing through each of the silicon wafer coarse alignment points in a predetermined order. The silicon wafer fine alignment operation refers to the workpiece stage 30 moving and passing through each of the silicon wafer fine alignment points in a predetermined order. The mask alignment operation refers to the workpiece stage 30 moving to the mask space image position. The exposure operation refers to the movement of the workpiece stage 30 from the starting position 08 of the exposure field to the ending position 09 of the exposure field within the position range of the exposure field.

[0099] Those skilled in the art will understand that during the operation of the lithography machine, the lengths of the movement paths of the photomask and the workpiece stage 30 affect the yield of the lithography machine. Therefore, from the perspective of improving the yield of the lithography machine, it is desirable to optimize the movement paths of the photomask and the workpiece stage 30 during the operation of the lithography machine to minimize the movement paths of both the photomask and the workpiece stage 30, thereby increasing the yield of the lithography machine.

[0100] The movement path of the mask is determined by the mask junction position, and the movement path of the workpiece stage 30 is determined by the execution order of each step from step S30 to step S90, as well as the silicon wafer junction position 01, the stage leveling point 02, the stage alignment point 03, the silicon wafer leveling point, the silicon wafer coarse alignment point, the silicon wafer fine alignment point, the mask spatial image position, the exposure field position, the exposure field start position 08, and the exposure field end position 09. Therefore, planning the motion path of the photomask is actually planning the photomask junction position. Planning the motion path of the workpiece stage 30 is actually planning the silicon wafer junction position 01, the stage leveling point 02, the stage alignment point 03, each silicon wafer leveling point, each silicon wafer coarse alignment point, each silicon wafer fine alignment point, the mask spatial image position, the exposure field position, the exposure field start position 08, and the exposure field end position 09 according to the execution order of each step from step S30 to step S90. The goal is to minimize the length of the line connecting the silicon wafer junction position 01, the stage leveling point 02, the stage alignment point 03, each silicon wafer leveling point, each silicon wafer coarse alignment point, each silicon wafer fine alignment point, the mask spatial image position, the exposure field start position 08, and the exposure field end position 09.

[0101] In practice, the silicon wafer junction position 01 and the mask junction position both depend on the overall layout of the lithography machine and cannot be adjusted. The stage leveling point 02 and the stage alignment point 03 are both points located on the reference plate and their positions are immutable. The mask spatial image position is determined by the mask alignment sensor 60 and the mask alignment mark, and can be characterized by the positions defined by the two mask alignment sensors 60, denoted as the first mask spatial image point 071 and the second mask spatial image point 072, respectively. Since the positions of the two mask alignment sensors and the mask alignment mark in the lithography machine are immutable, the position of the mask spatial image is also immutable; that is, the positions of the first mask spatial image point 071 and the second mask spatial image point 072 are both fixed and cannot be adjusted. The position of the exposure field is fixed and cannot be adjusted. The exposure field start position 08 and the exposure field end position 09 can theoretically be adjusted. However, in actual production, once the process document is finalized, the exposure field start position 08 and the exposure field end position 09 will not be easily changed. Therefore, this paper considers the exposure field start position 08 and the exposure field end position 09 to be immutable. The silicon wafer leveling point, the silicon wafer coarse alignment point, and the silicon wafer fine alignment point are all located on the silicon wafer 1, and their specific positions can be adjusted. Thus, in this embodiment of the invention, the silicon wafer leveling point, the silicon wafer coarse alignment point, and the silicon wafer fine alignment point can be planned according to the execution order of the steps S30 to S90.

[0102] In this embodiment of the invention, the coordinates of all workpiece stage positions are transformed to a specified coordinate system, such as the workpiece stage coordinate system. Furthermore, as... Figure 4 and Figure 5 As shown, a first circle C1 and a second circle C2 are defined in the specified coordinate system. The center of the first circle C1 is the center O1 of the objective lens 20, and the ratio of the radius of the first circle C1 to the radius of the silicon wafer 1 is a predetermined value. The center of the second circle C2 is the center O2 of the silicon wafer alignment sensor 50, and the ratio of the radius of the second circle C2 to the radius of the silicon wafer 1 is the predetermined value. The predetermined value is not less than 0.65 and not greater than 0.8. In actual operation, the first circle C1 and the second circle C2 intersect. Furthermore, it should be noted that the coverage area of ​​the silicon wafer alignment sensor 50 should be no less than a third circle, the center of the third circle C3 is the center O2 of the silicon wafer alignment sensor 50, and the ratio of the radius of the third circle C3 to the radius of the silicon wafer 1 is not less than 0.8.

[0103] In this embodiment of the invention, all the silicon wafer leveling points are equally spaced on the first circle C1 and arranged according to a first predetermined direction. Thus, the plurality of silicon wafer leveling points are respectively the first silicon wafer leveling point 041, the second silicon wafer leveling point 042, ..., the (m-1)th silicon wafer leveling point (not labeled in the figure), and the mth silicon wafer leveling point (not labeled in the figure), and the first silicon wafer leveling point 041, the second silicon wafer leveling point 042, ..., the (m-1)th silicon wafer leveling point, and the mth silicon wafer leveling point are arranged along the first predetermined direction. Two silicon wafer coarse alignment points are equally spaced on the second circle C2 and arranged according to a second predetermined direction. That is, the two silicon wafer coarse alignment points are respectively the first silicon wafer coarse alignment point 051 and the second silicon wafer coarse alignment point 052, and the first silicon wafer coarse alignment point 051 and the second silicon wafer coarse alignment point 052 are arranged along the second predetermined direction. All the silicon wafer alignment points are evenly distributed on the second circle C2 and ordered according to a third predetermined direction. That is, all the silicon wafer alignment points are the first silicon wafer alignment point 061, the second silicon wafer alignment point 062, ..., the (n-1)th silicon wafer alignment point (not marked in the figure), and the nth silicon wafer alignment point (not marked in the figure), and the first silicon wafer alignment point 061, the second silicon wafer alignment point 062, ..., the (n-1)th silicon wafer alignment point, and the nth silicon wafer alignment point are arranged along the third predetermined direction. Wherein, m is equal to the number of silicon wafer leveling points, and its value is not less than 2, preferably not less than 3; n is equal to the number of silicon wafer alignment points, and its value is not less than 2, preferably an even number. Furthermore, the first silicon wafer alignment point 061 coincides with the second silicon wafer coarse alignment point 052.

[0104] The specific positions of each silicon wafer leveling point, coarse alignment point, and fine alignment point are determined according to the execution order of steps S40 and S50.

[0105] Specifically, when step S40 is performed before step S50, the first silicon wafer leveling point 041 is the intersection of the line connecting the stage alignment point 03 and the center O1 of the objective lens 20 with the first circle C1 near the stage alignment point 03, and the m-th silicon wafer leveling point is closer to the second circle C2 than the second silicon wafer leveling point 042. The two coarse alignment points are the two intersections of the line connecting the m-th silicon wafer leveling point and the center O2 of the silicon wafer alignment sensor 50 with the second circle C2. The coarse alignment point near the m-th silicon wafer leveling point is the first coarse alignment point 051, and the coarse alignment point far from the m-th silicon wafer leveling point is the second coarse alignment point 052. That is, the first coarse alignment point 051 and the second coarse alignment point 052 are arranged along the direction from the m-th silicon wafer leveling point towards the center O2 of the silicon wafer alignment sensor 50. In other words, the aforementioned second predetermined direction refers to the direction from the m-th silicon wafer leveling point towards the center O2 of the silicon wafer alignment sensor 50. The second coarse alignment point 052 coincides with the first fine alignment point 061, and the n-th fine alignment point is closer to the first circle C1 than the second fine alignment point 062. Specifically... Figure 4 In the directions shown, the first predetermined direction is clockwise, and the third predetermined direction is counterclockwise, which are opposite.

[0106] When step S40 is executed after step S50, the first silicon wafer leveling point 041 is the intersection of the line connecting the stage leveling point 02 and the center O1 of the objective lens 20 with the first circle C1 near the stage leveling point 02, and the m-th silicon wafer leveling point is closer to the second circle C2 than the second silicon wafer leveling point 042. The two silicon wafer coarse alignment points are the two intersections of the line connecting the stage alignment point 03 and the center of the second circle C2 with the second circle C2, and the first silicon wafer coarse alignment point 051 is closer to the stage alignment point 03 than the second silicon wafer coarse alignment point 052. That is, the first silicon wafer coarse alignment point 051 and the second silicon wafer coarse alignment point 052 are arranged along the direction from the stage alignment point 03 to the center O2 of the silicon wafer alignment sensor 50. In other words, the second predetermined direction is the direction from the stage alignment point 03 to the center O2 of the silicon wafer alignment sensor 50. The n-th silicon wafer fine alignment point is closer to the first circle C1 than the second silicon wafer fine alignment point 062. Specifically Figure 5 In the directions shown, the first predetermined direction and the second predetermined direction are the same, both being clockwise.

[0107] Compared with the prior art, during the operation of the lithography machine, the movement path of the workpiece stage 30 when moving along the workpiece stage related position provided in the embodiment of the present invention is shorter than the movement path when moving along the workpiece stage related position in the prior art.

[0108] The following explanation uses an example where the number of silicon wafer leveling points in the workpiece stage relative to the embodiment of the present invention is three, and the number of silicon wafer precision alignment points is six. It can be understood that, in this embodiment of the present invention, the three silicon wafer leveling points are respectively designated as the first silicon wafer leveling point 041, the second silicon wafer leveling point 042, and the third silicon wafer leveling point 043, and the six silicon wafer precision alignment points are respectively designated as the first silicon wafer precision alignment point 061, the second silicon wafer precision alignment point 062, the third silicon wafer precision alignment point 063, the fourth silicon wafer precision alignment point 064, the fifth silicon wafer precision alignment point 065, and the sixth silicon wafer precision alignment point 066 (e.g., ...). Figure 4 and Figure 5 As shown in the figure, it can be understood that at this time, the fourth silicon wafer fine alignment point 064 coincides with the first silicon wafer coarse alignment point 051.

[0109] Therefore, in this embodiment of the invention, when step S40 is executed before step S50, the movement path of the workpiece stage 30 from the end of the exposure of the previous silicon wafer 1 to the start of the exposure of the next silicon wafer 1 is as follows: Figure 4 As shown, the path is as follows: Exposure field end position 09 → silicon wafer handover position 01 → stage leveling point 02 → stage alignment point 03 → first silicon wafer leveling point 041 → second silicon wafer leveling point 042 → third silicon wafer leveling point 042 → first silicon wafer coarse alignment point 051 → second silicon wafer coarse alignment point 052 (first silicon wafer fine alignment point 061) → second silicon wafer fine alignment point 062 → third silicon wafer fine alignment point 063 → fourth silicon wafer fine alignment point 064 → fifth silicon wafer fine alignment point 065 → sixth silicon wafer fine alignment point 066 → first mask space image point 071 → second mask space image point 072 → exposure field start position 08. When step S40 is executed after step S50, the movement path of the workpiece stage 30 is as follows: Figure 5 As shown, the sequence is as follows: Exposure field termination position 09 → Silicon wafer handover position 01 → Stage leveling point 02 → First silicon wafer leveling point 041 → Second silicon wafer leveling point 042 → Third silicon wafer leveling point 042 → Stage alignment point 03 → First silicon wafer coarse alignment point 051 → Second silicon wafer coarse alignment point 052 (First silicon wafer fine alignment point 061) → Second silicon wafer fine alignment point 062 → Third silicon wafer fine alignment point 063 → Fourth silicon wafer fine alignment point 064 → Fifth silicon wafer fine alignment point 065 → Sixth silicon wafer fine alignment point 066 → First mask space image point 071 → Second mask space image point 072 → Exposure field start position 08.

[0110] Figure 6The diagram shows a schematic representation of the distribution of relevant positions of a workpiece stage in a specified coordinate system in the prior art. Figure 6 and Figure 4 The only difference lies in the specific locations of the three silicon wafer leveling points, two silicon wafer coarse alignment points, and six silicon wafer fine alignment points. Figure 6 and Figure 5 The only difference lies in the specific locations of the three silicon wafer leveling points, two silicon wafer coarse alignment points, and six silicon wafer fine alignment points. For ease of distinction, Figure 6 The three silicon wafer leveling points are respectively designated as the first silicon wafer leveling point 041', the second silicon wafer leveling point 042', and the third silicon wafer leveling point 043'; the two silicon wafer coarse alignment points are respectively designated as the first silicon wafer coarse alignment point 051' and the second silicon wafer coarse alignment point 052'; and the six silicon wafer fine alignment points are respectively designated as the first silicon wafer fine alignment point 061', the second silicon wafer fine alignment point 062', the third silicon wafer fine alignment point 063', the fourth silicon wafer fine alignment point 064', the fifth silicon wafer fine alignment point 065', and the sixth silicon wafer fine alignment point 066'.

[0111] At Figure 6 In the diagram, the first silicon wafer leveling point 041', the second silicon wafer leveling point 042', and the third silicon wafer leveling point 043' are arranged clockwise around the center of the first circle C1. One of the three silicon wafer leveling points is near the exposure field end position 09, another is near the exposure field start position 08, and the third is far from both the exposure field start position 08 and the exposure field end position 09. The line connecting the silicon wafer leveling point near the exposure field end position 09 and the silicon wafer leveling point near the exposure field start position 08 is parallel to the line connecting the exposure field end position 09 and the exposure field start position 08. The line connecting the first coarse alignment point 051' and the second coarse alignment point 052' is parallel to the line connecting the exposure field end position 09 and the exposure field start position 08, and the first coarse alignment point 051' is closer to the first circle C1 than the second coarse alignment point 052'. The first silicon wafer alignment point 071', the second silicon wafer alignment point 072', the third silicon wafer alignment point 073', the fourth silicon wafer alignment point 074', the fifth silicon wafer alignment point 075', and the sixth silicon wafer alignment point 076' are arranged clockwise on the second circle C2.

[0112] When step S40 is performed before step S50, and the workpiece stage 30 is along Figure 6 When the workpiece stage moves to the relevant position as shown, the silicon wafer leveling point near the end position 09 of the exposure field is taken as the first silicon wafer leveling point 041'. Therefore, the movement path of the workpiece stage 30 is as follows: Figure 7 As shown. Comparison Figure 7 and Figure 4 You can see Figure 7 The distance from the alignment point 03 to the first silicon wafer leveling point 041' is significantly greater than Figure 4 The distance from the alignment point 03 to the first silicon wafer leveling point 041 in the figure. Figure 7 The distance from the third silicon wafer leveling point 043' to the first silicon wafer coarse alignment point 061' is significantly greater than Figure 4 The distance from the third silicon wafer leveling point 043 to the first silicon wafer coarse alignment point 061, and, Figure 7 The distance from the sixth silicon wafer alignment point 066' to the first mask spatial image point 71 is significantly greater than Figure 4 The distance from the sixth silicon wafer alignment point 066 to the first mask spatial image point 71. That is, Figure 7 The motion path of the middle workpiece stage 30 is longer than Figure 4 The motion path of the intermediate worktable 30.

[0113] When step S40 is performed after step S50, and the workpiece stage 30 along Figure 6 When the workpiece stage moves to the relevant position as shown, a silicon wafer leveling point near the starting position 08 of the exposure field is taken as the first silicon wafer leveling point 041'. Therefore, the movement path of the workpiece stage 30 is as follows: Figure 8 As shown. Comparison Figure 8 and Figure 5 As you can see, Figure 8 The distance from the leveling point 02 on the platform to the leveling point 041' on the first silicon wafer is significantly greater than... Figure 5 The distance from leveling point 02 on the platform to leveling point 041 on the first silicon wafer. Figure 8 The distance from the third silicon wafer leveling point 043' to the stage alignment point 03 is significantly greater than Figure 5 The distance from the third silicon wafer leveling point 043 to the stage alignment point 03. Figure 8 The distance from alignment point 03 on the platform to coarse alignment point 051' on the first silicon wafer is significantly greater than... Figure 5 The distance from the stage alignment point 03 to the first silicon wafer coarse alignment point 051, and Figure 8 The distance from the sixth silicon wafer alignment point 066' to the first mask spatial image point 71 is significantly greater than Figure 5 The distance from the sixth silicon wafer alignment point 066 to the first mask spatial image point 71. That is, Figure 8 The motion path of the middle workpiece stage 30 is longer than Figure 5 The motion path of the intermediate worktable 30.

[0114] Furthermore, an embodiment of the present invention also provides a lithography machine, the lithography machine including a driving mechanism, a control unit, and a workpiece stage 30 (e.g., Figure 2As shown in the figure, the drive mechanism is connected to the workpiece stage 30, the control unit is connected to the drive mechanism in communication, and is configured to execute the control method of the lithography machine as described above.

[0115] Furthermore, embodiments of the present invention also provide a computer-readable storage medium storing a program that, when executed, performs the control method for the lithography machine as described above.

[0116] While the present invention has been disclosed above, it is not limited thereto. Those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention also intends to include such modifications and variations.

Claims

1. A control method for a lithography machine, characterized in that, include: Determine whether the silicon wafer currently on the workpiece stage of the lithography machine is the first silicon wafer of the current batch; If so, control the movement of the workpiece stage and sequentially execute the stage leveling operation, stage alignment operation, silicon wafer leveling operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation; If not, determine whether to perform stage leveling and / or stage alignment operations based on preset conditions, and determine the relative order of stage alignment and silicon wafer leveling operations. Control the movement of the workpiece stage based on the determination result to perform at least silicon wafer leveling, silicon wafer coarse alignment, and silicon wafer fine alignment operations.

2. The control method for a lithography machine according to claim 1, characterized in that, The preset conditions include a first sub-preset condition, a second sub-preset condition, and a third sub-preset condition; The steps of determining whether to perform stage leveling and stage alignment operations, determining the relative order of stage alignment and silicon wafer leveling operations, and controlling the movement of the workpiece stage based on the determination results to perform at least silicon wafer leveling, silicon wafer coarse alignment, and silicon wafer fine alignment operations include: Determine whether the current operating condition meets the first sub-preset condition; If the current working condition meets the first sub-preset condition, then control the movement of the workpiece stage and sequentially execute the stage leveling operation, silicon wafer leveling operation, stage alignment operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation; If the current working condition does not meet the first sub-preset condition, then determine whether the current working condition meets the second sub-preset condition and whether the current working condition meets the third sub-preset condition. If the current working condition meets the second sub-preset condition, the workpiece table is controlled to move to perform a table leveling operation; if the current working condition does not meet the second sub-preset condition, the table leveling operation is skipped. If the current working condition meets the third sub-preset condition, the workpiece stage is controlled to move to perform the stage alignment operation; if the current working condition does not meet the third sub-preset condition, the stage alignment operation is skipped. Then, the workpiece stage is controlled to move and the silicon wafer leveling operation, silicon wafer coarse alignment operation, and silicon wafer fine alignment operation are executed in sequence.

3. The control method for a lithography machine according to claim 2, characterized in that, The step of determining whether the current working condition meets the first sub-preset condition includes: determining whether the target parameter is greater than the first threshold; if yes, then the current working condition meets the first sub-preset condition; if no, then the current working condition does not meet the first sub-preset condition.

4. The control method for a lithography machine according to claim 3, characterized in that, The target parameters include key dimensions of the silicon wafer, and the first threshold includes a preset dimension; and / or, the target parameters include the depth of focus of the silicon wafer alignment sensor of the lithography machine, and the first threshold includes a preset depth of focus; When the target parameters include the critical dimensions of the silicon wafer and the depth of focus of the silicon wafer alignment sensor, the target parameters being greater than the first threshold means that the critical dimensions of the silicon wafer are greater than the preset dimensions and / or the depth of focus of the silicon wafer alignment sensor is greater than the preset depth of focus.

5. The control method for a lithography machine according to claim 2, characterized in that, The step of determining whether the current operating condition meets the second sub-preset condition includes: When the exposure operation on the previous silicon wafer is completed, it is determined whether the offset of the zero position of the workpiece stage in the vertical direction relative to the stage leveling point on the reference plate of the lithography machine is greater than the second threshold. If yes, the current working condition is determined to meet the second sub-preset condition. If no, the current working condition is determined to not meet the second sub-preset condition.

6. The control method for a lithography machine according to claim 2, characterized in that, The step of determining whether the current operating condition meets the third sub-preset condition includes: When the exposure operation on the previous silicon wafer is completed, it is determined whether the offset of the zero position of the workpiece stage in the horizontal direction relative to the stage alignment point on the reference plate of the lithography machine is greater than the fourth threshold. If yes, the current working condition is determined to meet the third sub-preset condition. If no, the current working condition is determined to not meet the third sub-preset condition.

7. The control method for a lithography machine according to claim 1, characterized in that, The silicon wafer is pre-set with multiple silicon wafer leveling points, two silicon wafer coarse alignment points, and multiple silicon wafer fine alignment points; the multiple silicon wafer leveling points are equally spaced on a first circle and arranged in a first direction; the two silicon wafer coarse alignment points are equally spaced on a second circle and arranged in a second direction; the multiple silicon wafer fine alignment points are equally spaced on the second circle and arranged in a third direction; the second silicon wafer coarse alignment point coincides with the first silicon wafer fine alignment point, and the first silicon wafer coarse alignment point coincides with another silicon wafer fine alignment point; In a specified coordinate system, the center of the first circle is the center of the objective lens of the lithography machine, and the ratio of the radius of the first circle to the radius of the silicon wafer is a preset value; the center of the second circle is the center of the silicon wafer alignment sensor of the lithography machine, and the ratio of the radius of the second circle to the radius of the silicon wafer is the preset value; the preset value is greater than or equal to 0.65 and less than or equal to 0.8; The silicon wafer leveling operation includes the workpiece stage moving and passing through all the silicon wafer leveling points in sequence according to the order; the silicon wafer alignment operation includes the workpiece stage moving and passing through two silicon wafer coarse alignment points in sequence according to the order, and then passing through all the silicon wafer fine alignment points in sequence according to a third predetermined order.

8. The control method for a lithography machine according to claim 7, characterized in that, When the stage alignment operation is performed before the silicon wafer leveling operation, the first silicon wafer leveling point is the intersection of the line connecting the stage alignment point on the lithography machine's reference plate and the center of the objective lens with the first circle near the stage alignment point, and the last silicon wafer leveling point is closer to the second circle than the second silicon wafer leveling point; the two silicon wafer coarse alignment points are the two intersections of the line connecting the last silicon wafer leveling point and the center of the silicon wafer alignment sensor with the second circle, and the first silicon wafer coarse alignment point is closer to the last silicon wafer leveling point than the second silicon wafer coarse alignment point; the last silicon wafer fine alignment point is closer to the first circle than the second silicon wafer fine alignment point; The first direction is opposite to the third direction, and the second direction refers to the direction from the last silicon wafer leveling point to the center of the silicon wafer alignment sensor.

9. The control method for a lithography machine according to claim 7, characterized in that, When the silicon wafer leveling operation is performed before the stage alignment operation, the first silicon wafer leveling point is the intersection of the line connecting the stage alignment point on the lithography machine's reference plate and the center of the objective lens with the first circle near the stage alignment point; the last silicon wafer leveling point is closer to the second circle than the second silicon wafer leveling point; the two silicon wafer coarse alignment points are the two intersections of the line connecting the stage alignment point on the lithography machine's reference plate and the center of the silicon wafer sensor with the second circle, and the coarse alignment point adjacent to the stage alignment point is the first coarse alignment point; the last silicon wafer fine alignment point is closer to the first circle than the second silicon wafer fine alignment point. The first direction is the same as the third direction, and the second direction refers to the direction from the stage alignment point to the center of the silicon wafer alignment sensor.

10. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed, the control method for the lithography machine as described in any one of claims 1-9 is performed.

11. A lithography machine, characterized in that, The system includes a workpiece stage, a drive mechanism, an exposure system, and a control unit. The drive mechanism is drive-connected to the workpiece stage, and the control unit is communicatively connected to the drive mechanism and the exposure system. The control unit is configured to execute the control method of the lithography machine as described in any one of claims 1-9.

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