FPGA-based isar imaging multi-channel data high-bandwidth dual-mode transmission system and method

Abstract

This invention relates to the field of data transmission mechanism technology, specifically to an FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system. This system supports multiple independently configured data transmission channels. Each data transmission channel works collaboratively with DDR data processing modules A and B through a data channel selection module, implementing multi-channel data transmission functionality on the FPGA platform. This meets the requirements of high-real-time signal processing applications such as ISAR imaging for continuous high-bandwidth data transmission. The invention employs two independent sets of DDR data processing modules A and B, each with its own independent data path and control logic. Within one clock cycle, one module can perform a data write or in-order read operation while the other performs a transpose read or other read / write operation, thus achieving dual-channel concurrent access and eliminating read / write conflicts and pipeline congestion in traditional single-channel architectures.

Description

Technical Field

[0001] This invention relates to the field of data transmission mechanism technology, specifically to an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system and method. Background Technology

[0002] Inverse Synthetic Aperture Radar (ISAR) imaging technology is widely used in high-resolution target imaging and identification. As radar systems increasingly demand higher real-time processing capabilities, traditional implementations based on general-purpose processors or digital signal processors (DSPs) are no longer sufficient to meet the demands of high-performance imaging in terms of computational latency and data throughput. Field-Programmable Gate Arrays (FPGAs), due to their highly parallel hardware architecture and reconfigurable characteristics, have become an ideal platform for accelerating ISAR imaging algorithms.

[0003] In the ISAR signal processing workflow, key algorithm modules such as envelope alignment, Keystone transform, and azimuth autofocus typically involve rearranging and accessing multidimensional data, leading to frequent data transposition requirements during data flow. Due to the large volume of ISAR imaging data, intermediate processing results usually need to be cached in external DDR (Double Data Rate) memory. In traditional implementations, data transposition operations rely on non-contiguous address jumps in DDR memory, resulting in a significant decrease in memory bandwidth utilization and severely limiting the overall data throughput of the system. Summary of the Invention

[0004] The purpose of this invention is to provide an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system and method to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, one aspect of the present invention provides an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, including a data channel selection module, a DDR data processing module A, and a DDR data processing module B. The DDR data processing module A and the DDR data processing module B have identical structures. The data channel selection module selects a specific data transmission channel according to requirements. The data channel selection module sends data from the selected data transmission channel to one of the DDR data processing modules A and B for writing, and sends the data transmission mode of the selected data transmission channel to one of the DDR data processing modules A and B to control its read mode. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, reads it in original order transmission mode, and sends it to the data channel selection module. The data channel selection module allocates the received data to the selected data transmission channel, completing data scheduling and output.

[0006] Preferably, the data transmission mode information includes: Original sequence transfer mode: The control read unit reads data from the DDR memory in row-priority order; Transpose transfer mode: The control read unit reads data from the DDR memory in column priority order to achieve matrix transpose output.

[0007] Preferably, both DDR data processing module A and DDR data processing module B include: The writing unit has a writing port width of 64 bits and an output port width of 512 bits. The read unit has a write port width of 512 bits and an output port width of 64 bits. The AXI4 dual-mode control unit is used to generate write or read commands that conform to the AXI4 protocol. The MIG controller is used to execute write or read commands. DDR memory, which is used to store data.

[0008] Another aspect of the present invention provides a method for high-bandwidth dual-mode transmission of multi-channel data in ISAR imaging based on FPGA, comprising the following steps: S1. Schedule at least one data transmission channel through the data channel selection module and write its data to one of the DDR data processing module A and DDR data processing module B for execution. S2. At least one data transmission channel is scheduled through the data channel selection module, and its data reading task is assigned to one of the DDR data processing module A and DDR data processing module B for execution. The data reading task is performed in the original transmission mode or in the transposed transmission mode based on the transmission mode information. S3. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, and sends it to the data channel selection module for output. The data transmission channels scheduled in step S1 and step S2 may be the same or different.

[0009] Preferably, step S1 specifically includes: S11. The data channel selection module selects a specific data transmission channel m according to the requirements, where 1≤m≤M, and M is the total number of data transmission channels. The data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B. S12, the write unit of one of the DDR data processing modules A and B completes the data bit width conversion and writes the 512-bit data into the AXI4 dual-mode control module; the first counter of the 512-bit data is set to locate the current data transmission; S13. Based on the address mapping formula, the writing unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual-mode control module. The S14 and AXI4 dual-mode control modules receive 512-bit data and a write burst transfer address, generate a write command conforming to the AXI4 protocol, and output the data and the write burst transfer address to the MIG controller to complete the data write operation.

[0010] Preferably, step S2 specifically includes: S21. The data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B. Here, 1 indicates the original transmission mode and 0 indicates the transposed transmission mode. At the same time, it initiates a read command to trigger the data read operation. S22, the read unit of one of the DDR data processing modules A and B completes the data bit width conversion, and the write port of the read unit receives the output data from the AXI4 dual-mode control module; a second counter of 512 bits is set to locate the currently transmitted data; S23. When set to original sequence transmission mode, the reading unit generates the corresponding read burst transmission address according to the current value of the second counter based on the address mapping formula and in a row-first access manner, and outputs it to the AXI4 dual-mode control module. When set to transpose transmission mode, the reading unit generates the corresponding read burst transmission address based on the address mapping formula and the current value of the second counter, in a column-first access manner, and transmits it to the AXI4 dual-mode control module. The S24 and AXI4 dual-mode control modules receive the read burst transmission address required for reading data, generate read commands conforming to the AXI4 protocol, and access the DDR memory through the MIG controller to read the corresponding data; then, the read data is sent back to the data FIFO group of the read unit. S25. When set to original order transmission mode, the data read by the AXI4 dual-mode control module is sent to the original order read data FIFO group. At this time, each FIFO is used to buffer the data of the same row. The number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs. When set to transpose transmission mode, the data read by the AXI4 dual-mode control module is sent to the transpose read data FIFO group. At this time, each FIFO is used to cache the data of the same column. The number of FIFOs in this FIFO group is the same as the number of columns of the sub-matrix to which the data belongs. S26. The reading unit sequentially reads the data from each FIFO in the data FIFO group and monitors the current amount of data read by setting a third counter. In the original sequence transmission mode, when the output data of a certain FIFO reaches the number of columns of the sub-matrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading; In transposed transmission mode, when the output data of a certain FIFO reaches the number of rows of the submatrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading.

[0011] Preferably, step S3 specifically includes: S31. One of the DDR data processing modules A and B outputs the processed data and transmits it to the other of the DDR data processing modules A and B to achieve data backup and caching. S32, after the other of DDR data processing module A and DDR data processing module B receives and buffers the data, it is fixed to read the data in the original order transmission mode and sends the data to the data channel selection module; S33. After receiving the data, the data channel selection module allocates the data to the output interface of the data transmission channel n, where 1≤n≤M, thus completing the data scheduling and external output.

[0012] Preferably, the address mapping formula is: (1); In equation (1), This indicates the mapping result, i.e., writing to or reading from the burst transfer address; and These represent the row and column coordinates of the submatrix to which the current data belongs, respectively. , , This represents the total number of rows in the submatrix. This represents the total number of columns in the submatrix; and These represent the row and column coordinates of the current data within the submatrix, respectively. , , and These represent the number of rows and columns of data within the submatrix, respectively.

[0013] Compared with the prior art, the beneficial effects of the present invention are: 1. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system provided by this invention is designed for multiple independently configured data transmission channels. Each data transmission channel works in collaboration with the data channel selection module, DDR data processing module A, and DDR data processing module B to realize multi-channel data transmission on the FPGA platform, meeting the demand for continuous high-bandwidth data transmission in high real-time signal processing applications such as ISAR imaging. 2. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system provided by the present invention adopts two independent DDR data processing modules A and B. DDR data processing module A and DDR data processing module B correspond to independent data paths and control logic, which supports one of them to perform data writing or in-order reading operations while the other performs transpose reading or other read / write operations within one clock cycle, thereby realizing dual-channel concurrent access and eliminating read / write conflicts and pipeline blockages in the traditional single-channel architecture. 3. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method provided by this invention allows each data transmission channel to be independently configured into either in-order transmission mode or transposed transmission mode, and dynamically switched via control signals. In in-order transmission mode, data is read and written continuously in row-priority order; in transposed transmission mode, a block storage strategy is adopted, combined with an address remapping mechanism to achieve matrix transpose output. The transmission mode of each data transmission channel can be set independently without affecting each other, thereby supporting the processing and flexible scheduling of multi-channel heterogeneous data streams. Attached Figure Description

[0014] Figure 1 A structural block diagram of an FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system provided for embodiments of the present invention; Figure 2 The structural block diagram of DDR data processing module A and DDR data processing module B in an FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system provided for embodiments of the present invention. Figure 3 A flowchart of an FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method provided for embodiments of the present invention; Figure 4 A schematic diagram of the original sequence transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided for the embodiments of the present invention; Figure 5 A schematic diagram of the transposed transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided for embodiments of the present invention; Figure 6 The diagram shows the data block structure in the FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method provided for embodiments of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Figure 1 A block diagram of a high-bandwidth dual-mode ISAR imaging multi-channel data transmission system based on an embodiment of the present invention is shown. Figure 1As shown, the embodiments of the present invention provide an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, including a data channel selection module, a DDR data processing module A, and a DDR data processing module B. The DDR data processing module A and the DDR data processing module B have identical structures. The data channel selection module selects a specific data transmission channel according to requirements. The data channel selection module sends data from the selected data transmission channel to one of the DDR data processing modules A and B for writing, and sends the data transmission mode of the selected data transmission channel to one of the DDR data processing modules A and B to control its read mode. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, reads it in original order transmission mode, and sends it to the data channel selection module. The data channel selection module allocates the received data to the selected data transmission channel, completing data scheduling and output.

[0017] The data channel selection module has M data transmission channels, each of which can independently perform data writing and reading operations; DDR data processing module A and DDR data processing module B have the same structure and function, both of which are used to write data into DDR memory and implement in-order transmission mode reading or transposed transmission mode reading according to reading requirements.

[0018] The present invention provides an FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system for multiple independently configured data transmission channels. Each data transmission channel works collaboratively with DDR data processing modules A and B through a data channel selection module, realizing multi-channel data transmission on the FPGA platform. This meets the requirements of high real-time signal processing applications such as ISAR imaging for continuous high-bandwidth data transmission. The present invention employs two independent sets of DDR data processing modules A and B, each with its own independent data path and control logic. This allows one module to perform a data write or in-order read operation while the other performs a transpose read or other read / write operation within one clock cycle, thereby achieving dual-channel concurrent access and eliminating read / write conflicts and pipeline blockages in traditional single-channel architectures.

[0019] In one embodiment of the present invention, the data transmission mode information includes: Original sequence transfer mode: The control read unit reads data from the DDR memory in row-priority order; Transpose transfer mode: The control read unit reads data from the DDR memory in column priority order to achieve matrix transpose output.

[0020] To standardize the description of the input timing and storage mapping logic of data streams, this invention unifies the input data into a row-first transmission mode, meaning that data is input sequentially according to the row order of the matrix, with each row's elements arranged consecutively. Under this convention, the original-order transmission mode maintains the row-first reading order; while the transpose transmission mode implements column-first output, equivalent to performing a matrix transpose operation.

[0021] Figure 2 This diagram illustrates the structural block diagrams of DDR data processing module A and DDR data processing module B in an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by an embodiment of the present invention. In one embodiment of the present invention, as shown... Figure 2 As shown, both DDR data processing module A and DDR data processing module B include: The writing unit has a writing port width of 64 bits and an output port width of 512 bits. The read unit has a write port width of 512 bits and an output port width of 64 bits. The AXI4 dual-mode control unit is used to generate write or read commands that conform to the AXI4 protocol. The MIG controller is used to execute write or read commands. DDR memory, which is used to store data.

[0022] Figure 3 A flowchart of a high-bandwidth dual-mode transmission method for multi-channel ISAR imaging data based on an embodiment of the present invention is shown. Figure 3 As shown, in one embodiment of the present invention, another aspect of the present invention provides a method for high-bandwidth dual-mode transmission of multi-channel data in ISAR imaging based on FPGA, comprising the following steps: S1. Schedule at least one data transmission channel through the data channel selection module and write its data to one of the DDR data processing module A and DDR data processing module B for execution. S2. At least one data transmission channel is scheduled through the data channel selection module, and its data reading task is assigned to one of the DDR data processing module A and DDR data processing module B for execution. The data reading task is performed in the original transmission mode or in the transposed transmission mode based on the transmission mode information. S3. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, and sends it to the data channel selection module for output. The data transmission channels scheduled in step S1 and step S2 may be the same or different.

[0023] The number of data transmission channels described in this invention is not limited to a specific value and can be flexibly adjusted according to the actual needs of the application scenario or the resource capacity of the target hardware platform. In different embodiments, the number of channels can be set to 4, 12, or any other positive integer. Increasing or decreasing the number of channels does not change the core architecture and working principle of this invention and is therefore within the scope of protection of this invention.

[0024] The present invention provides an FPGA-based high-bandwidth dual-mode transmission method for multi-channel ISAR imaging data. Each data transmission channel can be independently configured into either in-order transmission mode or transposed transmission mode, and dynamically switched via control signals. DDR data processing module A and DDR data processing module B work collaboratively, each capable of executing their respective data transmission tasks in parallel. In in-order transmission mode, data is read and written continuously in row-priority order. In transposed transmission mode, a block storage strategy is employed, combined with an address remapping mechanism to achieve matrix transpose output. The transmission mode of each data transmission channel can be set independently without affecting each other, thus supporting the processing and flexible scheduling of multi-channel heterogeneous data streams.

[0025] In one embodiment of the present invention, step S1 specifically includes: S11. The data channel selection module selects a specific data transmission channel m according to the requirements, where 1≤m≤M, and M is the total number of data transmission channels. The data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B. S12, the write unit of one of the DDR data processing modules A and B completes the data bit width conversion and writes the 512-bit data into the AXI4 dual-mode control module; the first counter of the 512-bit data is set to locate the current data transmission; S13. Based on the address mapping formula, the writing unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual-mode control module. The S14 and AXI4 dual-mode control modules receive 512-bit data and a write burst transfer address, generate a write command conforming to the AXI4 protocol, and output the data and the write burst transfer address to the MIG controller to complete the data write operation.

[0026] Figure 4 A schematic diagram of the original sequence transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiments of the present invention is shown. Figure 5This diagram illustrates the transposed transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by an embodiment of the present invention. In one embodiment of the present invention, step S2 specifically includes: S21. The data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B. Here, 1 indicates the original transmission mode and 0 indicates the transposed transmission mode. At the same time, it initiates a read command to trigger the data read operation. S22, the read unit of one of the DDR data processing modules A and B completes the data bit width conversion, and the write port of the read unit receives the output data from the AXI4 dual-mode control module; a second counter of 512 bits is set to locate the currently transmitted data; S23. When set to in-order transmission mode, the read unit generates the corresponding read burst transmission address based on the address mapping formula and the current value of the second counter, using a row-first access method, and outputs it to the AXI4 dual-mode control module, such as... Figure 4 As shown; When set to transpose transfer mode, the read unit generates the corresponding read burst transfer address based on the address mapping formula and the current value of the second counter, using a column-first access method, and transmits it to the AXI4 dual-mode control module, such as... Figure 5 As shown; The S24 and AXI4 dual-mode control modules receive the read burst transmission address required for reading data, generate read commands conforming to the AXI4 protocol, and access the DDR memory through the MIG controller to read the corresponding data; then, the read data is sent back to the data FIFO group of the read unit. S25. When set to original order transmission mode, the data read by the AXI4 dual-mode control module is sent to the original order read data FIFO group. At this time, each FIFO is used to buffer the data of the same row. The number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs. When set to transpose transmission mode, the data read by the AXI4 dual-mode control module is sent to the transpose read data FIFO group. At this time, each FIFO is used to cache the data of the same column. The number of FIFOs in this FIFO group is the same as the number of columns of the sub-matrix to which the data belongs. S26. The reading unit sequentially reads the data from each FIFO in the data FIFO group and monitors the current amount of data read by setting a third counter. In the original sequence transmission mode, when the output data of a certain FIFO reaches the number of columns of the sub-matrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading; In transposed transmission mode, when the output data of a certain FIFO reaches the number of rows of the submatrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading.

[0027] In one embodiment of the present invention, step S3 specifically includes: S31. One of the DDR data processing modules A and B outputs the processed data and transmits it to the other of the DDR data processing modules A and B to achieve data backup and caching. S32, after the other of DDR data processing module A and DDR data processing module B receives and buffers the data, it is fixed to read the data in the original order transmission mode and sends the data to the data channel selection module; S33. After receiving the data, the data channel selection module allocates the data to the output interface of the data transmission channel n, where 1≤n≤M, thus completing the data scheduling and external output.

[0028] This invention proposes a multi-channel, high-bandwidth, dual-mode data transmission method based on FPGA. Utilizing a dual-group DDR memory structure and introducing a data channel selection module, it constructs a data transmission mechanism supporting high bandwidth, multiple channels, simultaneous dual-channel read / write, and flexible dual-mode switching. This effectively solves the bandwidth bottleneck and real-time performance degradation problems caused by single-channel limitations, fixed modes, and read / write conflicts in traditional architectures. It significantly improves the parallel processing capability and overall system throughput of complex ISAR imaging algorithms on the FPGA platform, providing reliable data path support for achieving high-performance, real-time ISAR imaging processing.

[0029] Figure 6 This diagram illustrates the data block structure in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by an embodiment of the present invention. In one embodiment of the present invention, the ISAR imaging data is a block containing... OK, The data matrix consists of columns, each with a width of 64 bits. To improve data transfer bandwidth, DDR memory employs a block storage strategy, with a structure as follows: Figure 6 As shown. By Figure 6 It can be seen that the entire data matrix is ​​divided into multiple parts of size 1. OK The columns are submatrices, and the data within each submatrix is ​​stored contiguously in row-major order, with contiguous storage addresses. Furthermore, the storage arrangement between the submatrices also follows a row-major order.

[0030] Furthermore, the address mapping formula is as follows: (1); In equation (1), Indicates based on Figure 6 The mapping result of the DDR memory data block storage structure shown is the writing burst transfer address or reading burst transfer address; and These represent the row and column coordinates of the submatrix to which the current data belongs, respectively. , , This represents the total number of rows in the submatrix. This represents the total number of columns in the submatrix; and These represent the row and column coordinates of the current data within the submatrix, respectively. , , and These represent the number of rows and columns of data within the submatrix, respectively.

[0031] This invention avoids storing the complete data matrix on the FPGA on-chip storage resources through a block storage strategy and address mapping multiplexing mechanism, significantly reducing the consumption of scarce logic resources such as BRAM; at the same time, multi-channel shared control logic and dual DDR architecture improve resource utilization and achieve optimized resource configuration while ensuring high performance.

[0032] In the block storage strategy adopted in this invention, the size of the submatrix is ​​not fixed, but can be dynamically set according to the system's requirements for data transmission bandwidth, latency, and the usage of on-chip storage resources (such as BRAM) on the FPGA. In different embodiments, smaller submatrixes (such as 2×2 or 4×4) can be selected to reduce resource consumption, suitable for resource-constrained scenarios; larger submatrixes (such as 16×16 or 32×32) can be selected to improve burst transmission efficiency and bandwidth utilization. All size configurations are based on the same address mapping mechanism and read / write control logic, which fall within the technical scope of this invention.

[0033] In embodiments of the present invention, for application scenarios that do not require support for simultaneous dual-channel read / write functionality, the system architecture of the present invention can be simplified: only one DDR data processing module (e.g., only DDR data processing module A) is retained, and the data scheduling strategy is adjusted accordingly. Although this simplified version sacrifices some concurrency capabilities, it still supports multi-channel, dual-mode data transmission functions and is suitable for scenarios with strict limitations on cost, power consumption, or logic resources. This single-DDR architecture, as an alternative implementation of the present invention, does not depart from its basic technical concept and should be included within the scope of protection of the present invention.

[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, characterized in that, The system includes a data channel selection module, a DDR data processing module A, and a DDR data processing module B. DDR data processing module A and DDR data processing module B have identical structures. The data channel selection module selects a specific data transmission channel according to requirements. The data channel selection module sends data from the selected data transmission channel to one of the DDR data processing modules A and B for writing, and also sends the data transmission mode of the selected data transmission channel to one of the DDR data processing modules A and B to control its read mode. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, reads it in original order transmission mode, and sends it to the data channel selection module. The data channel selection module allocates the received data to the selected data transmission channel, completing data scheduling and output. The data transmission modes include: Original sequence transfer mode: The control read unit reads data from the DDR memory in row-priority order; Transpose transfer mode: The control read unit reads data from the DDR memory in column priority order to achieve matrix transpose output.

2. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission system according to claim 1, characterized in that, Both DDR data processing module A and DDR data processing module B include: The writing unit has a writing port width of 64 bits and an output port width of 512 bits. The read unit has a write port width of 512 bits and an output port width of 64 bits. The AXI4 dual-mode control unit is used to generate write or read commands that conform to the AXI4 protocol. The MIG controller is used to execute write or read commands. DDR memory, which is used to store data.

3. A method for high-bandwidth dual-mode transmission of multi-channel data in ISAR imaging based on FPGA, characterized in that, Includes the following steps: S1. Schedule at least one data transmission channel through the data channel selection module and write its data to one of the DDR data processing module A and DDR data processing module B for execution. S2. At least one data transmission channel is scheduled through the data channel selection module, and its data reading task is assigned to one of the DDR data processing module A and DDR data processing module B for execution. The data reading task is performed in the original transmission mode or in the transposed transmission mode based on the transmission mode information. S3. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, and sends it to the data channel selection module for output. The data transmission channels scheduled in step S1 and step S2 may be the same or different.

4. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method according to claim 3, characterized in that, Step S1 specifically includes: S11. The data channel selection module selects a specific data transmission channel m according to the requirements, where 1≤m≤M, and M is the total number of data transmission channels. The data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B. S12, the write unit of one of the DDR data processing modules A and B completes the data bit width conversion and writes the 512-bit data into the AXI4 dual-mode control module; the first counter of the 512-bit data is set to locate the current data transmission; S13. Based on the address mapping formula, the writing unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual-mode control module. The S14 and AXI4 dual-mode control modules receive 512-bit data and a write burst transfer address, generate a write command conforming to the AXI4 protocol, and output the data and the write burst transfer address to the MIG controller to complete the data write operation.

5. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method according to claim 4, characterized in that, Step S2 specifically includes: S21. The data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B. Here, 1 indicates the original transmission mode and 0 indicates the transposed transmission mode. At the same time, it initiates a read command to trigger the data read operation. S22, the read unit of one of the DDR data processing modules A and B completes the data bit width conversion, and the write port of the read unit receives the output data from the AXI4 dual-mode control module; a second counter of 512 bits is set to locate the currently transmitted data; S23. When set to original sequence transmission mode, the reading unit generates the corresponding read burst transmission address according to the current value of the second counter based on the address mapping formula and in a row-first access manner, and outputs it to the AXI4 dual-mode control module. When set to transpose transmission mode, the reading unit generates the corresponding read burst transmission address based on the address mapping formula and the current value of the second counter, in a column-first access manner, and transmits it to the AXI4 dual-mode control module. The S24 and AXI4 dual-mode control modules receive the read burst transmission address required for reading data, generate read commands conforming to the AXI4 protocol, and access the DDR memory through the MIG controller to read the corresponding data; then, the read data is sent back to the data FIFO group of the read unit. S25. When set to original order transmission mode, the data read by the AXI4 dual-mode control module is sent to the original order read data FIFO group. At this time, each FIFO is used to buffer the data of the same row. The number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs. When set to transpose transmission mode, the data read by the AXI4 dual-mode control module is sent to the transpose read data FIFO group. At this time, each FIFO is used to cache the data of the same column. The number of FIFOs in this FIFO group is the same as the number of columns of the sub-matrix to which the data belongs. S26. The reading unit sequentially reads the data from each FIFO in the data FIFO group and monitors the current amount of data read by setting a third counter. In the original sequence transmission mode, when the output data of a certain FIFO reaches the number of columns of the sub-matrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading; In transposed transmission mode, when the output data of a certain FIFO reaches the number of rows of the submatrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading.

6. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method according to claim 5, characterized in that, Step S3 specifically includes: S31. One of the DDR data processing modules A and B outputs the processed data and transmits it to the other of the DDR data processing modules A and B to achieve data backup and caching. S32, after the other of DDR data processing module A and DDR data processing module B receives and buffers the data, it is fixed to read the data in the original order transmission mode and sends the data to the data channel selection module; S33. After receiving the data, the data channel selection module allocates the data to the output interface of the data transmission channel n, where 1≤n≤M, thus completing the data scheduling and external output.

7. The FPGA-based ISAR imaging multi-channel high-bandwidth dual-mode transmission method according to claim 6, characterized in that, ISAR imaging data is a collection OK, The data matrix is ​​divided into multiple columns of size. OK The columns are submatrices, and the data within each submatrix is ​​stored contiguously in row-major order with contiguous storage addresses; The address mapping formula is: （1）； In equation (1), This indicates the mapping result, i.e., writing to or reading from the burst transfer address; and These represent the row and column coordinates of the submatrix to which the current data belongs, respectively. , , This represents the total number of rows in the submatrix. This represents the total number of columns in the submatrix; and These represent the row and column coordinates of the current data within the submatrix, respectively. , , and These represent the number of rows and columns of data within the submatrix, respectively.

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