A method and system for evaluating hot carrier degradation in integrated circuits

Abstract

The application relates to the technical field of reliability evaluation of semiconductor devices, and discloses a method and system for evaluating thermal carrier degradation of integrated circuits, initial model parameter extraction of a transistor, initial model parameter extraction is performed on an undegraded transistor; interface trap density ΔN th and oxide layer trap density ΔN sat are calculated through a degradation amount ΔV IT of a threshold voltage and a degradation amount ΔID OT of a saturation drain current; a degradation amount of a transistor transmission parameter is calculated, a degradation amount of a plurality of transistor transmission parameters is calculated through preset physical relations for the interface trap density ΔN IT and the oxide layer trap density ΔN OT ; transistor current-voltage characteristics are predicted, the degradation amount of the transistor transmission parameter is substituted into a compact model of the transistor, and the current-voltage characteristics of the degraded transistor are predicted. The method adopted by the application can comprehensively predict the change of complex I-V characteristics by only measuring the degradation of two key parameters V th and ID sat , and greatly reduces the experimental test amount and time cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device reliability assessment technology, and in particular to a method and system for assessing the degradation of hot carriers in integrated circuits. Background Technology

[0002] As complementary metal-oxide-semiconductor (CMOS) process dimensions continue to shrink to nanometer nodes, transistor reliability issues are becoming increasingly prominent. The hot carrier injection effect is one of the key mechanisms leading to device performance degradation. The interface traps and oxide layer traps it causes can significantly alter the transport characteristics of the device, thereby affecting the lifetime and stability of integrated circuits.

[0003] Traditional reliability assessment methods typically focus only on the degradation of a single parameter, such as threshold voltage or saturation leakage current, for example, by monitoring threshold voltage drift or saturation current decay to assess device aging. However, hot carrier degradation is a complex process involving multiple coupled parameters. In addition to threshold voltage and saturation current, key transport parameters such as subthreshold slope, effective mobility, and drain-induced barrier reduction factor also change significantly. Relying on a single parameter cannot comprehensively reflect the overall degradation of device transport characteristics, leading to biased predictions of circuit-level performance degradation.

[0004] Furthermore, compact models widely used in industry, such as the BSIM series models, typically contain hundreds of parameters. The extraction process is complex and computationally intensive, making efficient integration into circuit simulation workflows difficult and limiting their practical application in reliability-oriented design. Therefore, existing technologies lack an efficient method that can accurately and comprehensively predict the performance degradation of devices and their circuits under long-term operating conditions based on limited experimental data. Summary of the Invention

[0005] This invention addresses the problems in existing technologies by providing a method and system for evaluating hot carrier degradation in integrated circuits. Through minimized experimental testing, it achieves a seamless link from device degradation to circuit performance prediction, providing a practical and efficient solution for the reliability design and optimization of nanoscale integrated circuits.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A method for evaluating the degradation of hot carriers in integrated circuits, the method comprising: Initial model parameter extraction for transistors; extraction of initial model parameters for non-degraded transistors; degradation amount of threshold voltage. and degradation of saturation leakage current The measurement involves applying hot carrier stress to the transistor and measuring the degradation of the threshold voltage before and after applying the hot carrier stress. Degradation of saturation leakage current ; Interface trap density caused by hot carrier injection and oxide layer trap density The calculation is based on the degradation amount of the threshold voltage. and degradation of saturation leakage current Perform interface trap density and oxide layer trap density Calculation; The degradation of transistor transport parameters is calculated using a pre-defined physical formula for the interface trap density. and oxide layer trap density Calculate the degradation of multiple transistor transfer parameters; The prediction of transistor current-voltage characteristics involves substituting the degradation of transistor transfer parameters into a compact model of the transistor to predict the degraded transistor current-voltage characteristics.

[0007] Preferably, the method also includes prediction of circuit-level reliability simulation, in which the degradation of transmission parameters is embedded into a circuit simulator using a hardware description language, and the target circuit is simulated to predict circuit performance degradation.

[0008] Preferably, the initial model parameters of the transistor are extracted by fitting the IV characteristic curve of the initial transistor to a virtual source model.

[0009] Preferably, the interface trap density caused by hot carrier injection and oxide layer trap density The calculation of the interface trap density caused by hot carrier injection is performed by extrapolating the stress voltage. and oxide layer trap density The calculation.

[0010] Preferably, the interface trap density caused by hot carrier injection is calculated by extrapolating the stress voltage. and oxide layer trap density The calculations include: Obtain the degradation rate factor under different accelerating stress voltages; Establish the functional relationship between the degradation rate factor and the stress voltage under different accelerating stress voltages; By using the degradation rate factor as a function of stress voltage under different accelerating stress voltages, the interface trap density under actual operating voltages is extrapolated. and oxide layer trap density .

[0011] Preferably, the degradation of the transistor transfer parameters includes the threshold voltage degradation. Subthreshold slope coefficient degradation Effective migration rate degradation DIBL coefficient degradation .

[0012] Preferably, the initial model parameters of the transistor include the zero bias threshold voltage. Subthreshold swing coefficient n, leakage-induced barrier reduction coefficient δ, effective carrier mobility Source-drain series resistance RSD and saturated carrier velocity .

[0013] As a preferred choice, the hardware description language is Verilog-A.

[0014] Preferably, the degradation rate factor under accelerated stress voltage has an exponential decay relationship with the stress voltage.

[0015] To address the aforementioned technical problems, the present invention also provides a system for evaluating the degradation of hot carriers in integrated circuits, which is implemented using an integrated circuit hot carrier degradation prediction method. The system includes: The transistor initial model parameter extraction module extracts the initial model parameters for non-degraded transistors; Degradation of threshold voltage and degradation of saturation leakage current The measurement module applies hot carrier stress to the transistor and measures the degradation of the threshold voltage before and after the application of hot carrier stress. Degradation of saturation leakage current ; Interface trap density caused by hot carrier injection and oxide layer trap density The calculation module uses the degradation amount of the threshold voltage. and degradation of saturation leakage current Perform interface trap density and oxide layer trap density Calculation; The module for calculating the degradation of transistor transport parameters uses a preset physical formula to determine the interface trap density. and oxide layer trap density Calculate the degradation of multiple transistor transfer parameters; The transistor current-voltage characteristic prediction module substitutes the degradation of transistor transfer parameters into the compact model of the transistor to predict the degraded transistor current-voltage characteristics.

[0016] This invention, by adopting the above technical solutions, has significant technical effects: The method used in this invention only requires measurement and The degradation of two key parameters can comprehensively predict complex IV characteristic changes, greatly reducing the amount of experimental testing and time costs.

[0017] This invention correlates trap density with multiple core transport parameters through a physical model, which can more accurately reflect the physical nature of hot carrier degradation, and the prediction results are in high agreement with experimental data.

[0018] The method of this invention is applicable to a variety of device structures, including planar MOSFETs and FinFETs.

[0019] This invention achieves a seamless link from device-level degradation to circuit-level performance prediction, providing a practical simulation platform and optimization basis for reliability-oriented integrated circuit design. Attached Figure Description

[0020] Figure 1 This is a flowchart of the present invention.

[0021] Figure 2 This is a flowchart of Embodiment 2 of the present invention.

[0022] Figure 3 This is a flowchart of the stress voltage extrapolation process of the present invention.

[0023] Figure 4 This is a schematic diagram of the degradation rate factor and stress-voltage curve of the present invention.

[0024] Figure 5 This is a schematic diagram of the current-voltage characteristic curve of the present invention.

[0025] Figure 6 This is a flowchart of the circuit reliability simulation based on Verilog-A according to the present invention.

[0026] Figure 7 This is a schematic diagram of the output frequency curve of the ring oscillator of the present invention.

[0027] Figure 8 This is a schematic diagram of the amplifier gain and phase shift curves of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0029] Example 1

[0030] A method for evaluating hot carrier degradation in integrated circuits. Figure 1 The methods include: Initial model parameters for transistors are extracted, specifically for non-degraded transistors. These initial model parameters include the zero-bias threshold voltage. Subthreshold swing coefficient n, leakage-induced barrier reduction coefficient Effective carrier mobility Source-drain series resistance and saturated carrier velocity ; Degradation of threshold voltage and degradation of saturation leakage current The measurement involves applying hot carrier stress to the transistor and measuring the degradation of the threshold voltage before and after applying the hot carrier stress. Degradation of saturation leakage current ; Interface trap density caused by hot carrier injection and oxide layer trap density The calculation is based on the degradation amount of the threshold voltage. and degradation of saturation leakage current Perform interface trap density and oxide layer trap density Calculation; The degradation of transistor transport parameters is calculated using a pre-defined physical formula for the interface trap density. and oxide layer trap density Calculate the degradation of multiple transistor transfer parameters; The prediction of transistor current-voltage characteristics involves substituting the degradation of transistor transfer parameters into a compact model of the transistor to predict the degraded transistor current-voltage characteristics.

[0031] The initial model parameters of the transistor are extracted by fitting the IV characteristic curve of the initial transistor to the virtual source model.

[0032] Interface trap density caused by hot carrier injection and oxide layer trap density The calculation of the interface trap density caused by hot carrier injection is performed by extrapolating the stress voltage. and oxide layer trap density The calculation.

[0033] Interface trap density caused by hot carrier injection is calculated by extrapolating stress voltage. and oxide layer trap density The calculations include: Obtain the degradation rate factor under different accelerating stress voltages; Establish the functional relationship between the degradation rate factor and the stress voltage under different accelerating stress voltages; By using the degradation rate factor as a function of stress voltage under different accelerating stress voltages, the interface trap density under actual operating voltages is extrapolated. and oxide layer trap density .

[0034] The degradation of transistor transfer parameters includes the threshold voltage degradation. Subthreshold slope coefficient degradation Effective migration rate degradation DIBL coefficient degradation .

[0035] The degradation rate factor under accelerated stress voltage has an exponential decay relationship with the stress voltage.

[0036] Example 2

[0037] Based on Example 1, this example Figure 2 The initial model parameters of the transistor were extracted by fitting the current-voltage characteristic curve of the initial transistor without experiencing hot carrier stress using a virtual source model, thereby extracting a set of initial physical parameters. The initial model parameters of the transistor include the zero-bias threshold voltage. Subthreshold swing coefficient n, leakage-induced barrier reduction coefficient Effective carrier mobility Source-drain series resistance and saturated carrier velocity .

[0038] Accelerated stress experiments and key parameter measurements involve applying accelerated stress conditions to the transistor, i.e., a gate stress voltage higher than the normal operating voltage. and drain stress voltage The threshold voltage of the transistor was measured before and after stress. and saturation leakage current And calculate its degradation amount. and .

[0039] Based on the measured and Based on the established trap-type transport degradation model, the density of interface traps generated by hot carrier injection is calculated. and oxide layer trap density The calculation method is as follows: ; ; Parameter degradation calculation is based on the extracted interface trap density. and oxide layer trap density The degradation of each key transmission parameter is calculated using physical relationships; Threshold voltage degradation ; Subthreshold slope coefficient degradation ; Effective migration rate degradation ; DIBL coefficient degradation ; Where q is the electron charge. Gate oxide capacitor, Thermoelectric voltage, The energy width of the interface trap distribution. , , These are the fitting parameters.

[0040] Current-voltage characteristic prediction, using the calculated degraded parameters Substituting the current equations into the virtual source model, we predict the complete current-voltage (IV) characteristic curves of the transistor after experiencing hot carrier degradation.

[0041] Figure 3-5 In the stress-voltage extrapolation process, the relationship between the degradation rate factor and voltage is first fitted using experimental data under different accelerated stress conditions. Then, this relationship is used to extrapolate the trap density at the actual operating voltage VDD, thereby predicting the device performance after long-term operation at this voltage.

[0042] exist Figure 6 In the circuit-level reliability simulation flowchart, the trap-type transmission degradation model describing parameter degradation is written into Verilog-A code and integrated into the circuit simulator. By calling this model, the target circuit is simulated to predict its performance degradation after long-term operation, such as the frequency drop of the ring oscillator or the gain loss of the amplifier.

[0043] Figure 7-8 By combining the degradation model (defect-based transport degradation model TTD) with the compact model (virtual source model VSM) and embedding it into standard circuits such as Cadence simulation environment through Verilog-A interface, the simulation and analysis of circuit performance degradation can be realized.

[0044] Example 3

[0045] Based on the above embodiments, this embodiment Figure 3 To predict device degradation under actual operating voltage, a stress voltage extrapolation method is used: Figure 4 In this study, the degradation rate factors under different accelerating stress voltages were obtained through experiments. ;in, Generate a rate for the interface trap; For the rate of oxide trap generation, This is the upper limit for normalized interface traps; Establish degradation rate factor With drain stress voltage The functional relationship. Using this functional relationship, the trap density... and Extrapolation to actual operating voltage The values ​​below predict the degradation of the device's IV characteristics under normal operating conditions. Figure 5 The curve of drain current versus gate voltage is obtained.

[0046] Example 4

[0047] This embodiment is a system for evaluating the degradation of hot carriers in integrated circuits. The system, implemented using an integrated circuit hot carrier degradation prediction method, includes: The transistor initial model parameter extraction module extracts the initial model parameters for non-degraded transistors; the initial model parameters of the transistor include the zero bias threshold voltage. Subthreshold swing coefficient n, leakage-induced barrier reduction coefficient Effective carrier mobility Source-drain series resistance and saturated carrier velocity ; Degradation of threshold voltage and degradation of saturation leakage current The measurement module applies hot carrier stress to the transistor and measures the degradation of the threshold voltage before and after the application of hot carrier stress. Degradation of saturation leakage current ; Interface trap density caused by hot carrier injection and oxide layer trap density The calculation module uses the degradation amount of the threshold voltage. and degradation of saturation leakage current Perform interface trap density and oxide layer trap density Calculation; The module for calculating the degradation of transistor transport parameters uses a preset physical formula to determine the interface trap density. and oxide layer trap density Calculate the degradation of multiple transistor transfer parameters; The transistor current-voltage characteristic prediction module substitutes the degradation of transistor transfer parameters into the compact model of the transistor to predict the degraded transistor current-voltage characteristics.

Claims

1. A method for evaluating the degradation of hot carriers in an integrated circuit, the method comprising: Extraction of initial model parameters for transistors; The initial model parameters for the transistor include the zero bias threshold voltage. Subthreshold swing coefficient n, leakage-induced barrier reduction coefficient Effective carrier mobility Source-drain series resistance and saturated carrier velocity ; Accelerated stress experiments and key parameter measurements were conducted by applying different accelerated stress conditions to the transistor and measuring the threshold voltage of the transistor before and after each accelerated stress condition. and saturation leakage current And obtain the change. and ; Based on the measured and Calculate the density of interface traps caused by hot carrier injection. and oxide layer trap density Specifically, it includes: Obtain the degradation rate factor under different accelerating stress voltages ( , , );in, Generate a rate for the interface trap; For the rate of oxide trap generation, This is the upper limit for normalized interface traps; A functional relationship between the degradation rate factor and the stress voltage under different accelerating stress voltages was established. Using this functional relationship, the interface trap density under the actual operating voltage was extrapolated. and oxide layer trap density ; or ; ； Based on the interface trap density under actual operating voltage and oxide layer trap density Calculate the degradation of key transmission parameters: Threshold voltage degradation or ; Subthreshold slope coefficient degradation ; Effective migration rate degradation ; DIBL coefficient degradation ; Where q is the electron charge. Gate oxide capacitor, Thermoelectric voltage, Let k1, k2, and m be the energy width of the interface trap distribution, and k1, k2, and m be the fitting parameters. Current-voltage characteristic prediction, using the calculated degraded parameters Substitute it into the virtual source model to predict the complete current-voltage characteristic curve of the transistor after experiencing hot carrier degradation.

2. The method for evaluating the degradation of hot carriers in an integrated circuit according to claim 1, characterized in that, It also includes predictions based on circuit-level reliability simulation, which embeds the degradation of transmission parameters into a circuit simulator using a hardware description language to simulate the target circuit in order to predict circuit performance degradation.

3. The method for evaluating the degradation of hot carriers in an integrated circuit according to claim 1, characterized in that, The initial model parameters of the transistor are extracted by fitting the IV characteristic curve of the initial transistor to a virtual source model.

4. The method for evaluating the degradation of hot carriers in an integrated circuit according to claim 2, characterized in that, The hardware description language is Verilog-A.

5. The method for evaluating the degradation of hot carriers in an integrated circuit according to claim 1, characterized in that, The degradation rate factor under accelerated stress voltage has an exponential decay relationship with the stress voltage.

6. A system for evaluating the degradation of hot carriers in integrated circuits, characterized in that, A method for evaluating the degradation of hot carriers in an integrated circuit as described in any one of claims 1-5 includes: The transistor initial model parameter extraction module extracts the initial model parameters for non-degraded transistors; Degradation of threshold voltage and degradation of saturation leakage current The measurement module applies hot carrier stress to the transistor and measures the degradation of the threshold voltage before and after the application of hot carrier stress. Degradation of saturation leakage current ; Interface trap density caused by hot carrier injection and oxide layer trap density The calculation module uses the degradation amount of the threshold voltage. and degradation of saturation leakage current Perform interface trap density and oxide layer trap density Calculation; The module for calculating the degradation of transistor transport parameters uses a preset physical formula to determine the interface trap density. and oxide layer trap density Calculate the degradation of multiple transistor transfer parameters; The transistor current-voltage characteristic prediction module substitutes the degradation of transistor transfer parameters into the compact model of the transistor to predict the degraded transistor current-voltage characteristics.

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