Memory and its reading circuit
By introducing a first signal precharge circuit and optimizing the bit line precharge circuit design in the memory read circuit, the problems of slow read speed and false '1' generation of multiple programmable non-volatile memory are solved, and faster data '0' read speed is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-08-30
- Publication Date
- 2026-07-31
AI Technical Summary
Existing multi-programmable non-volatile memories suffer from slow read speeds during read operations, especially when reading data '0', which is prone to generating false '1', leading to extended read times.
By introducing a first signal pre-charge circuit into the memory read circuit, the establishment of the first signal is accelerated by using the pre-charge signal. Combined with the optimized design of the bit line pre-charge circuit and the reference signal generation circuit, the reference signal is established quickly, reducing the generation of false '1'.
It improves the speed of reading data '0', reduces the occurrence of false '1', and improves the overall efficiency of the read operation.
Smart Images
Figure CN121641091B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to information storage, and more particularly to a memory, and also to a memory read circuit. Background Technology
[0002] Based on whether stored data will be lost after power failure, memory can be divided into volatile memory (RAM) and non-volatile memory (NVM). NVM generally includes three basic operation modes: programming, erasing, and reading. Programming and erasing operations change the initial electrical state of the memory cell, thereby "storing" data. Reading operations distinguish the different states of the memory cell and output the read result.
[0003] Taking a multi-times programmable non-volatile memory (MTP) as an example: the initial state of the memory cell is "0". After programming, the electrical state of the memory cell changes, that is, the data "1" is stored. Then, after erasing, the memory cell can be restored to its initial state, that is, the data "0" is stored.
[0004] With continuous technological advancements, the industry hopes to further improve the read speed of MTP (Medium-Terminal Packet) memory. However, as storage capacity continues to increase, a single bit line (bl) typically needs to support a large number of cells (memory units), resulting in a heavy load. If the bl is charged solely by the current from the cell storing data "1" during a read operation, the setup time will be long, leading to slow read speeds. To improve read speed, a common method is to precharge the bl at the start of the read operation. The goal is to precharge the bl to near, but slightly below, the switching voltage of the sense amplifier (SA). After this precharge, if a cell storing data "1" is being read, the current from that cell will quickly raise the bl to the switching voltage, allowing the "1" to be read. Therefore, precharging can significantly improve the speed of reading "1".
[0005] However, precharged memory is prone to generating false "1s," which slows down the reading of "0s." A false "1" means that when reading a cell containing data "0," a "1" is read first, and the correct "0" is read only after a period of time. Although the reading of "0" is eventually correct, the generation of false "1s" significantly slows down the reading speed.
[0006] The industry has made numerous attempts to optimize precharge schemes by adjusting precharge voltage and other methods, and has also tried to solve the problem of generating false "1"s, but has not completely solved the problem. The main issues are as follows: 1. When precharge is enabled, the access time (tacc) for reading "0" operations increases with the increase of the power supply voltage. 2. Under different corners, some results are improved, while others are worse. 3. When precharge is enabled, the improvement in tacc for reading "1" operations is not significant compared to when precharge is disabled. Summary of the Invention
[0007] Therefore, it is necessary to provide a memory and its reading circuit that can improve the reading speed of the memory cell.
[0008] A memory read circuit includes: a first signal generation circuit for generating a first signal; a reference signal generation circuit connected to the first signal generation circuit for establishing a reference signal based on the first signal; a bit line precharge circuit connected to a bit line for precharging the bit line upon receiving a precharge signal; a comparison circuit connected to the reference signal generation circuit, the bit line, and a selected memory cell for comparing an electrical signal obtained from reading the selected memory cell with an electrical signal from a precharged bit line, and outputting a comparison result; a data output port for outputting data stored in the memory cell based on the comparison result; and a first signal precharge circuit connected to the first signal generation circuit for precharging the first signal generation circuit upon receiving the precharge signal, thereby accelerating the establishment of the first signal.
[0009] The aforementioned memory read circuit, by setting a first signal pre-charge circuit, accelerates the establishment of the first signal when the pre-charge signal arrives, thereby enabling the reference signal to be established more quickly. Since false "1"s are less likely to occur when reading data "0" from the memory cell after the reference signal is established, the read speed when reading data "0" can be improved.
[0010] In one embodiment, the memory read circuit further includes a pre-charge source, wherein the bit line pre-charge circuit and the first signal pre-charge circuit are powered by the pre-charge source; the resistance between the endpoint of the first signal pre-charge circuit receiving power from the pre-charge source and the first signal generation circuit is greater than the resistance between the endpoint of the bit line pre-charge circuit receiving power from the pre-charge source and the reference signal generation circuit, thereby enabling the electrical signal from the pre-charged bit line to be established faster than the first signal.
[0011] In one embodiment, the first signal pre-charge circuit includes: a first NMOS transistor, the drain of which is connected to the pre-charge source to obtain power, and the gate of which is used to obtain the pre-charge signal so as to control the conduction of the first NMOS transistor by the pre-charge signal; a second NMOS transistor, the drain of which is connected to the source of the first NMOS transistor, and the gate of which is used to obtain the pre-charge signal so as to control the conduction of the second NMOS transistor by the pre-charge signal; and a third NMOS transistor, the drain of which is connected to the gate of the third NMOS transistor and the source of the second NMOS transistor, and the source of the third NMOS transistor is grounded; wherein, the first signal generation circuit is connected to the common terminal of the drain of the second NMOS transistor and the source of the first NMOS transistor.
[0012] In one embodiment, the first signal generation circuit includes a fourth NMOS transistor, the drain of which is connected to the gate of the fourth NMOS transistor and acquires the current provided when two memory cells storing data "1" are read, and the source of the fourth NMOS transistor is grounded; the first signal is the voltage signal of the gate of the fourth NMOS transistor, and the first signal pre-charge circuit pre-charges the first signal generation circuit through the gate of the fourth NMOS transistor; the reference signal generation circuit includes a fifth NMOS transistor, the gate of which is used to acquire the first signal, the source of which is grounded, and the drain of which is connected to the comparator circuit, the selected memory cell, and the bit line, and the drain current signal of the fifth NMOS transistor is the reference signal.
[0013] In one embodiment, the comparison circuit includes: a sixth NMOS transistor, the gate of which is connected to the drain of the fifth NMOS transistor, and the source of which is grounded; a sensitive amplifier, the input of which is connected to the drain of the sixth NMOS transistor, and the output of which is connected to the data output port for outputting the comparison result; a first PMOS transistor, the drain of which is connected to the input of the sensitive amplifier, and the source of which is connected to the VDD terminal; a second PMOS transistor, the source of which is connected to the VDD terminal, and the gate of which is connected to the gate of the first PMOS transistor; and a seventh NMOS transistor, the gate of which is used to acquire the first signal, the drain of which is connected to the gates of the second and first PMOS transistors, and the source of which is grounded.
[0014] In one embodiment, the memory read circuit further includes a level-assisted establishment circuit, which includes: an eighth NMOS transistor, the drain of which is connected to the common terminal of the drain of the second PMOS transistor and the drain of the seventh NMOS transistor, and the gate of the eighth NMOS transistor is used to acquire the pre-charge signal; and a ninth NMOS transistor, the gate of which is connected to the drain of the ninth NMOS transistor and to the source of the eighth NMOS transistor, and the source of the ninth NMOS transistor is grounded.
[0015] In one embodiment, the pre-charge source includes: a third PMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, the source of which is connected to VDD, and the drain of which serves as the output terminal of the pre-charge source; a fourth PMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, and the source of which is connected to VDD; a tenth NMOS transistor, the gate of which is connected to the drain of the fourth PMOS transistor, the source of which is connected to the drain of the third PMOS transistor, and the drain of which is connected to VDD; an eleventh NMOS transistor, the source of which is grounded, and the gate of which is connected to the drain of the third PMOS transistor; when the output terminal of the pre-charge source outputs power, the eleventh NMOS transistor operates in the subthreshold region; and a twelfth NMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, the source of which is connected to VDD; a twelfth NMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, the source of which is connected to VDD; a tenth NMOS transistor, the gate of which is connected to VDD; and a twelfth NMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, the source of which is connected to VDD; a twelfth NMOS transistor, the source of which is grounded, and the gate of which is connected to the drain of the third PMOS transistor; when the output terminal of the pre-charge source outputs power, the eleventh NMOS transistor operates in the subthreshold region; and a twelfth NMOS transistor, the gate of which is used to acquire a read enable signal for a read operation, the source of which is connected to VDD; a twelfth NMOS transistor, the source of which is connected to VDD; and a twelfth NMOS transistor, the source of which is connected to VDD; a twelfth NMOS transistor, the source of which is connected to VDD; and a twelf To acquire the pre-charge signal, the source of the twelfth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the drain of the fifth PMOS transistor is connected to the drain of the twelfth NMOS transistor and to the common terminal of the gate of the tenth NMOS transistor and the drain of the fourth PMOS transistor; the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor and to the drain of the sixth PMOS transistor; the drain of the seventh PMOS transistor is connected to the source of the fifth PMOS transistor, and the source of the seventh PMOS transistor is connected to the VDD terminal, and the gate of the seventh PMOS transistor is used to acquire the inverted signal of the read enable signal; the drain of the eighth PMOS transistor is connected to the source of the sixth PMOS transistor, and the source of the eighth PMOS transistor is connected to the VDD terminal, and the gate of the eighth PMOS transistor is used to acquire the inverted signal of the read enable signal; a current source has its positive terminal connected to the drain of the sixth PMOS transistor and its negative terminal grounded.
[0016] In one embodiment, the current source is implemented through the bias current of the memory, or the current source is implemented by a resistor, or the current source is implemented by a transistor with an inverse size operating in the linear region.
[0017] In one embodiment, the precharge signal is a pulse signal that also changes from low to high when the read enable signal of the read operation changes from low to high.
[0018] A memory comprising the read circuit described in any of the foregoing embodiments.
[0019] The aforementioned memory, by setting a first signal pre-charge circuit, accelerates the establishment of the first signal when the pre-charge signal arrives, thereby enabling the reference signal to be established more quickly. Since false "1"s are less likely to occur when reading data "0" from the memory cell after the reference signal is established, the read speed when reading data "0" can be improved.
[0020] In one embodiment, the memory is a multiple-programmable non-volatile memory. Attached Figure Description
[0021] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.
[0022] Figure 1 This is a circuit schematic of an exemplary pre-charge circuit.
[0023] Figure 2 This is a schematic diagram illustrating the working principle of the sensitive amplifier SA.
[0024] Figure 3 This is a circuit diagram of a matching circuit for an exemplary sensitive amplifier SA.
[0025] Figure 4 This is a waveform diagram of an exemplary readout circuit.
[0026] Figure 5 This is a circuit block diagram of the memory read circuit in one embodiment of this application.
[0027] Figure 6 This is a circuit diagram of a portion of the circuit structure of the memory read circuit in one embodiment of this application.
[0028] Figure 7 This is a circuit diagram of a pre-charge power supply in one embodiment of this application. Detailed Implementation
[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0032] Figure 1 This is a schematic diagram of an exemplary pre-charge circuit, including four NMOS transistors (M0~M3). The drain of NMOS transistor M3 is used to obtain the pre-charge source voltage vprec provided by the pre-charge source, and the gate is used to obtain the pre-charge signal dlsenpc, which is a narrow high-level pulse. The source of NMOS transistor M3 is connected to the drain of NMOS transistor M2. The gate of NMOS transistor M2 is used to obtain the secondary selection switch signal yblv. For the selected bit line bl, yblv is high, so NMOS transistor M2 is always on. The source of NMOS transistor M2 is connected to node dl, which is the node after bit line bl passes through ymux (the selection circuit in the y direction). Figure 1 In this context, cload represents the capacitive load of bit line bl. The drain of NMOS transistor M1 is connected to the source of NMOS transistor M2. The gate of NMOS transistor M1 is used to obtain the precharge signal dlsenpc. The source of NMOS transistor M1 is connected to the drain and gate of NMOS transistor M0. The source of NMOS transistor M0 is grounded (VSS).
[0033] When the read enable signal arrives during a read operation, the precharge signal dlsenpc transitions from low to high, turning on NMOS transistors M3 and M1, and charging node dl to a high level. If the pulse of the precharge signal dlsenpc is wide enough, node dl will eventually be charged to the sum of the gate-source voltage Vgs of NMOS transistor M0 and the drain-source voltage Vds of NMOS transistor M1. This value is definitely greater than the threshold voltage of the input transistor (NMOS) of the sensitive amplifier.
[0034] Figure 2 This is a schematic diagram illustrating the working principle of the sensitive amplifier SA. The current Icell from the selected memory cell (i.e., the current obtained by reading the data stored in the memory cell) is compared with a reference current Iref. If the current Icell is greater than the reference current Iref, the voltage at node dl gradually increases, causing the SA's output voltage dout to flip. If the current Icell is less than the reference current Iref, the voltage at node dl decreases, and the output voltage dout does not flip.
[0035] Figure 3 This is a circuit schematic of an exemplary sensitive amplifier SA. The current (2 × Icell_1) superimposed from two memory cells with data set to "1" is read to generate a first signal sref. This first signal sref is used to generate the reference current Iref of the SA and to provide bias current for the SA. Because the bit line bl runs through the entire memory matrix and connects to numerous devices, the capacitive load on the bit line bl is significant. Figure 1 The pre-charge circuit in the circuit charges node dl high when the read enable signal arrives.
[0036] We through Figure 4 To illustrate with waveforms Figure 3 and Figure 1The circuit shown exhibits a false "1" due to the following: rdlv is the read enable signal; dl_0cell is the voltage of node dl when reading the stored data "0" (referred to as 0 cell); dl_1cell is the voltage of node dl when reading the stored data "1" (referred to as 1 cell). The precharge signal dlsenpc is a pulse signal. When the read enable signal rdlv transitions from low to high, the precharge signal dlsenpc also transitions from low to high. As can be seen, because node dl is precharged by the precharge circuit, both dl_1cell and dl_0cell are charged quickly while the precharge signal dlsenpc is high. After the precharge signal dlsenpc ends, dl_1cell continues to charge high because its current Icell is greater than the reference current Iref; dl_0cell is pulled low because its current Icell is less than the reference current Iref. It is important to note that the load of the first signal sref is comparable to that of the bit line bl, so its setup is slower. At the end of the precharge signal dlsenpc, the first signal sref has not yet risen to the voltage that the reference current Iref can establish. After time t1 elapses after the end of the precharge signal dlsenpc, the first signal sref rises to the voltage that allows the reference current Iref to establish. Figure 3 The voltage at which the NMOS transistor MS0 is turned on is constant, so the voltage value of dl_0cell remains unchanged during the time interval t1. dl_0cell is only pulled low after the voltage of the first signal sref rises to the point that the NMOS transistor MS0 is turned on. Because the precharge signal dlsenpc is not stable—for example, it is generated through a gate delay within the memory circuit—the pulse width of the precharge signal dlsenpc varies depending on the process, power supply voltage, and temperature. In some cases, dl_0cell may be charged to a higher value, causing the SA output voltage dou to flip, outputting an incorrect "1". Only after the NMOS transistor MS0 is turned on will dl_0cell be pulled low, outputting a correct "0". A "1" generated during the reading of a "0" is called a false "1". The default state of the SA output voltage dou is "0". Without false "1s", the speed of reading "0" is faster than the speed of reading "1", therefore, tacc depends on the time to read "1". However, the appearance of a false "1" means that reading "0" may take longer than reading "1", thus increasing the overall tacc time.
[0037] Figure 5This is a circuit block diagram of a memory read circuit in one embodiment of this application, including a first signal generation circuit 10, a reference signal generation circuit 20, a bit line precharge circuit 30, a comparison circuit 40, a data output port 50, and a first signal precharge circuit 60. The first signal generation circuit 10 generates a first signal sref. The reference signal generation circuit 20 is connected to the first signal generation circuit 10 and is used to establish a reference signal based on the first signal sref. In one embodiment of this application, the reference signal is a reference current Iref. The bit line precharge circuit 30 is connected to the bit line bl and is used to precharge the bit line bl when a precharge signal dlsenpc is received. Node dl is the node located between the mux (multiplexer) and the reference signal generation circuit 20 after the bit line bl passes through the mux (multiplexer). In one embodiment of this application, the bit line precharge circuit 30 can be... Figure 1 The circuit shown. The comparator circuit 40 is connected to the reference signal generation circuit 20, the bit line bl, and the selected memory cell. Figure 5 In the illustrated embodiment, node dl connects to comparator circuit 40, bit line precharge circuit 30, reference signal generation circuit 20, and the selected memory cell. Comparator circuit 40 superimposes the electrical signal obtained from reading data from the selected memory cell with the electrical signal from the precharged bit line bl, compares this superposition with the reference signal, and outputs the comparison result. Figure 5 In the illustrated embodiment, the comparator circuit 40 is used to output the comparison result between the current Icell obtained by reading the data stored in the memory cell and the reference current Iref. The data output port 50 is connected to the comparator circuit 40 and is used to output whether the data stored in the memory cell is "0" or "1" based on the comparison result. The first signal pre-charge circuit 60 is connected to the first signal generation circuit 10 and is used to pre-charge the first signal generation circuit 10 when the pre-charge signal dlsenpc is received, thereby accelerating the establishment of the first signal sref.
[0038] The aforementioned memory, based on the bit line precharge circuit 30 to improve the read speed when reading data "1", further improves the first signal precharge circuit 60 by accelerating the establishment of the first signal sref when the precharge signal dlsenpc arrives, thereby enabling the reference signal to be established more quickly. Since false "1"s are less likely to occur when reading data "0" from the memory cell after the reference signal is established, the read speed when reading data "0" can be improved.
[0039] Figure 6This is a circuit diagram illustrating a portion of the read circuit structure of a memory in one embodiment of this application. In this embodiment, the first signal pre-charge circuit 60 includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3. The drain of the first NMOS transistor N1 is connected to a pre-charge source to obtain electrical energy, specifically, the pre-charge source voltage vprec. The gate of the first NMOS transistor N1 is used to obtain a pre-charge signal dlsenpc, thereby controlling the conduction of the first NMOS transistor N1 by the pre-charge signal dlsenpc. The drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1, and the gate of the second NMOS transistor N2 is used to obtain the pre-charge signal dlsenpc, thereby controlling the conduction of the second NMOS transistor N2 by the pre-charge signal dlsenpc. The drain of the third NMOS transistor N3 is connected to the gate of the third NMOS transistor N3 and the source of the second NMOS transistor N2, and the source of the third NMOS transistor N3 is grounded (VSS). The first signal generation circuit 10 is connected to the common terminal of the drain of the second NMOS transistor N2 and the source of the first NMOS transistor N1.
[0040] exist Figure 6 In the illustrated embodiment, the first signal generation circuit 10 includes a fourth NMOS transistor N4. The drain of the fourth NMOS transistor N4 is connected to its gate and receives the current supplied when two memory cells storing data "1" are read. The source of the fourth NMOS transistor N4 is grounded (VSS). In this embodiment, the first signal sref is the voltage signal at the gate of the fourth NMOS transistor N4, and the first signal pre-charge circuit 60 pre-charges the first signal generation circuit 10 through its connection to the gate of the fourth NMOS transistor N4.
[0041] In one embodiment of this application, the memory read circuit includes a pre-charge source. The bit line pre-charge path 30 and the first signal pre-charge path 60 are powered by this pre-charge source, i.e., a pre-charge source voltage vprec. The on-resistance of the first signal pre-charge path 60 in the path supplying power to the first signal generation circuit 10 is greater than the on-resistance of the bit line pre-charge path 30 in the bit line pre-charge path. This allows the electrical signal from the pre-charged bit line to be established faster than the first signal sref, i.e., the voltage of node dl is established faster than the voltage of the first signal sref. This improves the read speed when reading a memory cell containing data "1". Specifically, the resistance between the port of the first signal pre-charge path 60 receiving the pre-charge source voltage vprec (i.e., the drain of the first NMOS transistor N1) and the gate of the fourth NMOS transistor N4 is greater than the resistance between the port of the bit line pre-charge path 30 receiving the pre-charge source voltage vprec (i.e., the drain of the first NMOS transistor N1) and the gate of the fourth NMOS transistor N4. Figure 1The resistance between the drain of NMOS transistor M3 in the bit line precharge circuit 30 and node dl. The aforementioned resistance can be adjusted by adjusting the size of the NMOS transistors in the bit line precharge circuit 30 and the first signal precharge circuit 60, i.e., adjusting the precharge speed. To reduce power consumption, in one embodiment of this application, the precharge source voltage vprec is provided to the bit line precharge circuit 30 and the first signal precharge circuit 60 only during the period when the precharge signal dlsenpc is in the target state (e.g., high level).
[0042] exist Figure 6 In the illustrated embodiment, the reference signal generation circuit 20 includes a fifth NMOS transistor N5. The gate of the fifth NMOS transistor N5 is used to acquire a first signal sref, and the source of the fifth NMOS transistor N5 is grounded. The drain of the fifth NMOS transistor N5 is connected to the comparator circuit 40, the selected memory cell, and the bit line bl; specifically, it is connected to node dl. The drain current signal (Iref) of the fifth NMOS transistor N5 is the aforementioned reference signal.
[0043] exist Figure 6 In the illustrated embodiment, the comparator circuit 40 includes a sixth NMOS transistor N6, a sensitive amplifier SA, a first PMOS transistor P1, a second PMOS transistor P2, and a seventh NMOS transistor N7. The gate of the sixth NMOS transistor N6 is connected to the drain of the fifth NMOS transistor N5, and the source of the sixth NMOS transistor N6 is grounded (VSS). The input terminal of the sensitive amplifier SA is connected to the drain of the sixth NMOS transistor N6, and its output terminal dout is connected to the data output port 50 for outputting the aforementioned comparison result. The drain of the first PMOS transistor P1 is connected to the input terminal of the sensitive amplifier SA, and the source of the first PMOS transistor P1 is connected to the VDD (power supply) terminal. The source of the second PMOS transistor P2 is connected to the VDD terminal, and the gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1. The gate of the seventh NMOS transistor N7 is used to acquire the first signal sref, the drain of the seventh NMOS transistor N7 is connected to the gates of the second PMOS transistor P2 and the first PMOS transistor P1, and the source of the seventh NMOS transistor N7 is grounded (VSS). In one embodiment of this application, when the bit line precharge circuit 30 receives the precharge signal dlsenpc, the voltage value for precharging node dl is slightly less than the threshold voltage of the sixth NMOS transistor N6.
[0044] exist Figure 6In the illustrated embodiment, the bias current of the sensitive amplifier SA is generated by the first signal sref. Before the first signal sref is established, the potential of node siref is close to the potential of the power supply voltage VDD, resulting in the bias current of the sensitive amplifier SA being 0. That is, the voltage of node siref can only be established after the first signal sref rises to the turn-on voltage of the seventh NMOS transistor N7. At this time, the drain of the sixth NMOS transistor N6 is in a high-impedance state, which is easily affected by interference and may cause errors. To address this, this embodiment adds a level-assisted establishment circuit 70 connected to node siref, enabling the bias current of the sensitive amplifier SA to be established as early as possible.
[0045] exist Figure 6 In the illustrated embodiment, the level-assisted establishment circuit 70 includes an eighth NMOS transistor N8 and a ninth NMOS transistor N9. The drain of the eighth NMOS transistor N8 is connected to the common terminal of the drain of the second PMOS transistor P2 and the drain of the seventh NMOS transistor N7, and the gate of the eighth NMOS transistor N8 is used to acquire the precharge signal dlsenpc. The gate of the ninth NMOS transistor N9 is connected to the drain of the ninth NMOS transistor N9 and to the source of the eighth NMOS transistor N8, and the source of the ninth NMOS transistor N9 is grounded (VSS). After the read enable signal rdlv arrives, during the period when the precharge signal dlsenpc is high, due to the small parasitic capacitance at node siref, the voltage of node siref is quickly pulled down by the level-assisted establishment circuit 70, and the bias current of the sensitive amplifier SA can be quickly established, which greatly reduces the probability of interference to the output dout of the sensitive amplifier SA, and further reduces the possibility of false "1"s.
[0046] Figure 7This is a circuit schematic of a pre-charge power source according to an embodiment of this application. The pre-charge power source includes a third PMOS transistor P3, a fourth PMOS transistor P4, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, and a current source I. The gate of the third PMOS transistor P3 is used to acquire the read enable signal rdlv for the read operation. The source of the third PMOS transistor P3 is connected to the VDD terminal, and the drain of the third PMOS transistor P3 serves as the output terminal of the pre-charge power source, outputting the pre-charge power source voltage vprec. The gate of the fourth PMOS transistor P4 is used to acquire the read enable signal rdlv, and the source of the fourth PMOS transistor P4 is connected to the VDD terminal. The gate of the tenth NMOS transistor N10 is connected to the drain of the fourth PMOS transistor P4, the source of the tenth NMOS transistor N10 is connected to the drain of the third PMOS transistor P3, and the drain of the tenth NMOS transistor N10 is connected to the VDD terminal. The source of the eleventh NMOS transistor N11 is grounded, and its gate is connected to the drain of the third PMOS transistor P3. When the precharge source outputs the precharge source voltage vprec, the eleventh NMOS transistor N11 operates in the subthreshold region. The gate of the twelfth NMOS transistor N12 is used to acquire the precharge signal dlsenpc, and its source is connected to the drain of the eleventh NMOS transistor N11. The drain of the fifth PMOS transistor P5 is connected to the drain of the twelfth NMOS transistor N12 and to the common terminal of the gate of the tenth NMOS transistor N10 and the drain of the fourth PMOS transistor P4. The gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5 and to the drain of the sixth PMOS transistor P6. The drain of the seventh PMOS transistor P7 is connected to the source of the fifth PMOS transistor P5, and its source is connected to the VDD terminal. The gate of the seventh PMOS transistor is used to acquire the inverted signal rdlvb of the read enable signal rdlv. The drain of the eighth PMOS transistor P8 is connected to the source of the sixth PMOS transistor P6. The source of the eighth PMOS transistor P8 is connected to the VDD terminal. The gate of the eighth PMOS transistor is used to acquire the signal rdlvb. The positive terminal of current source I is connected to the drain of the sixth PMOS transistor P6, and the negative terminal is grounded.
[0047] exist Figure 7In the illustrated embodiment, the sources of the third PMOS transistor P3, the fourth PMOS transistor P4, and the drain of the tenth NMOS transistor N10 are also connected to the output of a low-dropout linear regulator (LDO). The LDO provides a defined potential to the pre-charge source voltage vprec during non-read operations (e.g., programming or erasing operations). During read operations, the pre-charge source voltage vprec is ultimately powered by the power supply VDD. Because the pre-charge source needs to charge each dl node during read operations, requiring a large instantaneous current, using an LDO for power would lower the LDO output voltage, affecting the memory cell current and consequently the read speed. In one embodiment of this application, the LDO output voltage is 2.5V, i.e., v2p5.
[0048] Since the precharge source voltage vprec is controlled by the precharge signal dlsenpc, some glitches are inevitable. This may cause the precharge source voltage vprec to exceed the threshold voltage (the upper limit of the voltage value for precharging node dl by the bit line precharge circuit 30), potentially generating false "1"s. If the precharge source voltage vprec output by the precharge source can be made slightly lower than the threshold voltage of the NMOS transistor, the generation of false "1"s can be avoided. Figure 7 In the illustrated embodiment, the pre-charge source voltage vprec is equal to the gate-source voltage Vgs of the eleventh NMOS transistor N11. By adjusting the transistor size to allow the eleventh NMOS transistor N11 to operate in the subthreshold region, it is possible to ensure that the pre-charge source voltage vprec is slightly lower than the threshold voltage of the eleventh NMOS transistor N11, thereby avoiding the generation of false "1"s.
[0049] In one embodiment of this application, Figure 7 The current source I in the memory circuit can come from the bias current portion of the memory circuit, or be implemented by a resistor, or by a transistor with an inverse size operating in the linear region, etc.
[0050] This application correspondingly proposes a memory that includes the read circuitry of the memory described in any of the foregoing embodiments. In one embodiment of this application, the memory is an MTP memory.
[0051] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0053] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A memory read circuit, characterized in that, include: A first signal generation circuit is used to generate a first signal; A reference signal generation circuit, connected to the first signal generation circuit, is used to establish a reference signal based on the first signal; Bit line pre-charge circuit, connected to the bit line, is used to pre-charge the bit line when a pre-charge signal is received; A comparison circuit, connected to the reference signal generation circuit, the bit line, and the selected memory cell, is used to superimpose the electrical signal obtained from reading the selected memory cell with the electrical signal from the pre-charged bit line, compare it with the reference signal, and output the comparison result. A data output port is used to output the data stored in the storage unit based on the comparison result. A first signal pre-charging circuit is connected to a first signal generation circuit and is used to pre-charge the first signal generation circuit when the pre-charging signal is received, thereby accelerating the establishment of the first signal.
2. The memory read circuit according to claim 1, characterized in that, It also includes a pre-charging power source, wherein the bit line pre-charging circuit and the first signal pre-charging circuit are powered by the pre-charging power source; The resistance between the endpoint of the first signal pre-charging circuit receiving electrical energy from the pre-charging source and the first signal generation circuit is greater than the resistance between the endpoint of the bit line pre-charging circuit receiving electrical energy from the pre-charging source and the reference signal generation circuit, thereby enabling the electrical signal from the pre-charged bit line to be established faster than the first signal.
3. The memory read circuit according to claim 2, characterized in that, The first signal pre-charge circuit includes: The first NMOS transistor has its drain connected to the pre-charge source to obtain electrical energy, and its gate is used to obtain the pre-charge signal so that the pre-charge signal controls the conduction of the first NMOS transistor. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the gate of the second NMOS transistor is used to acquire the precharge signal so that the precharge signal controls the conduction of the second NMOS transistor. The drain of the third NMOS transistor is connected to the gate of the third NMOS transistor and the source of the second NMOS transistor, and the source of the third NMOS transistor is grounded. The first signal generation circuit is connected to the common terminal of the drain of the second NMOS transistor and the source of the first NMOS transistor.
4. The memory read circuit according to claim 1, characterized in that, The first signal generation circuit includes a fourth NMOS transistor, the drain of which is connected to the gate of the fourth NMOS transistor and receives the current provided when two memory cells storing data "1" are read. The source of the fourth NMOS transistor is grounded. The first signal is the voltage signal of the gate of the fourth NMOS transistor. The first signal pre-charge circuit pre-charges the first signal generation circuit through the gate of the fourth NMOS transistor. The reference signal generation circuit includes a fifth NMOS transistor. The gate of the fifth NMOS transistor is used to acquire the first signal. The source of the fifth NMOS transistor is grounded. The drain of the fifth NMOS transistor is connected to the comparator circuit, the selected memory cell, and the bit line. The drain current signal of the fifth NMOS transistor is the reference signal.
5. The memory read circuit according to claim 4, characterized in that, The comparison circuit includes: The sixth NMOS transistor has its gate connected to the drain of the fifth NMOS transistor, and its source grounded. A sensitive amplifier, with its input terminal connected to the drain of the sixth NMOS transistor and its output terminal connected to the data output port for outputting the comparison result; The drain of the first PMOS transistor is connected to the input terminal of the sensitive amplifier, and the source of the first PMOS transistor is connected to the VDD terminal. The second PMOS transistor has its source connected to the VDD terminal and its gate connected to the gate of the first PMOS transistor. The seventh NMOS transistor has its gate used to acquire the first signal, its drain connected to the gates of the second PMOS transistor and the first PMOS transistor, and its source grounded.
6. The memory read circuit according to claim 5, characterized in that, It also includes a level-assisted establishment circuit, which includes: The eighth NMOS transistor has its drain connected to the common terminal of the drain of the second PMOS transistor and the drain of the seventh NMOS transistor, and its gate is used to acquire the precharge signal. The ninth NMOS transistor has its gate connected to its drain and then to the source of the eighth NMOS transistor. The source of the ninth NMOS transistor is grounded.
7. The memory read circuit according to claim 2, characterized in that, The pre-charge source includes: The third PMOS transistor has its gate used to acquire the read enable signal for the read operation, its source connected to the VDD terminal, and its drain serving as the output terminal of the pre-charge source. The fourth PMOS transistor has its gate used to acquire the read enable signal for the read operation, and its source is connected to the VDD terminal. The tenth NMOS transistor has its gate connected to the drain of the fourth PMOS transistor, its source connected to the drain of the third PMOS transistor, and its drain connected to the VDD terminal. The eleventh NMOS transistor has its source grounded and its gate connected to the drain of the third PMOS transistor. When the pre-charge power source outputs power, the eleventh NMOS transistor operates in the subthreshold region. The twelfth NMOS transistor has its gate used to acquire the pre-charge signal, and its source is connected to the drain of the eleventh NMOS transistor. The fifth PMOS transistor has its drain connected to the drain of the twelfth NMOS transistor and to the common terminal of the gate of the tenth NMOS transistor and the drain of the fourth PMOS transistor. The sixth PMOS transistor has its gate connected to the gate of the fifth PMOS transistor and its drain. The seventh PMOS transistor has its drain connected to the source of the fifth PMOS transistor, and its source connected to the VDD terminal. The gate of the seventh PMOS transistor is used to obtain the inverted signal of the read enable signal. The eighth PMOS transistor has its drain connected to the source of the sixth PMOS transistor, and its source connected to the VDD terminal. The gate of the eighth PMOS transistor is used to acquire the inverted signal of the read enable signal. The current source is connected to the drain of the sixth PMOS transistor at its positive terminal and grounded at its negative terminal.
8. The memory read circuit according to claim 7, characterized in that, The current source is implemented through the bias current of the memory, or the current source is implemented by a resistor, or the current source is implemented by a transistor with an inverse size operating in the linear region.
9. A memory, characterized in that, The read circuit includes any one of claims 1-8.
10. The memory according to claim 9, characterized in that, The memory is a multiple-programmable non-volatile memory.