An analog-to-digital converter circuit with low noise and temperature compensation

Abstract

This invention discloses a low-noise, temperature-compensated analog-to-digital converter circuit, comprising multipliers MIX1 and MIX2, resistors R1 and R2, an integrator, a one-bit quantizer circuit, and a feedback loop. The two input terminals of multiplier MIX1 are connected to the input signal Vin. The two output terminals of multiplier MIX1 are connected to the two input terminals of multiplier MIX2 via resistors R1 and R2, respectively. The output terminal of multiplier MIX2 is connected to the input terminal of the integrator and the output terminal of the feedback loop at a summing node. This invention can significantly reduce noise and improve output accuracy.

Description

Technical Field

[0001] This invention relates to an analog-to-digital converter circuit, and more particularly to an analog-to-digital converter circuit with low noise and temperature compensation, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Analog-to-digital converters (ADCs) are key circuit components that convert analog signals into digital signals. Σ-Δ ADCs (Sigma Delta Analog-to-Digital Converters) combine oversampling and noise shaping techniques to achieve extremely high conversion accuracy within a relatively low signal bandwidth, and are widely used in audio analysis, precision measurement instruments, and data acquisition. With the increasing demand for high-precision ADCs in applications such as high-quality audio and precision instruments, the design of low-noise, low-temperature-drift Σ-Δ ADCs has become an important research direction.

[0003] Based on how the loop filter processes the signal, modulators are classified into discrete-time modulators and continuous-time modulators. Discrete-time (DT) modulators use discrete-time circuits, such as switched-capacitor circuits, for their loop filters. Their sampling circuit is located at the very beginning of the loop filter; therefore, DT modulators require anti-aliasing filtering before sampling. Continuous-time (CT) modulators use continuous-time circuits such as gm-c amplifiers for their loop filters. Their input signal is filtered by a low-pass loop filter before being sampled; therefore, CT modulators do not require anti-aliasing filtering before sampling. Based on the characteristics of their circuit modules, discrete-time and continuous-time modulators have different development trends: the gain coefficient of a discrete-time modulator is precisely determined by the capacitor ratio and the circuit module is robust, but it requires the signal to be fully established within the corresponding period. Therefore, discrete-time modulators are more suitable for low-speed, high-precision applications. On the other hand, the coefficients of a continuous-time modulator are realized by the absolute values ​​of the components, which are easily affected by external factors and clock jitter. However, the signal does not need to be fully established within a finite time and there are no large step amplitudes. Therefore, continuous-time modulators are more suitable for high-speed, medium-to-low-precision applications.

[0004] like Figure 3As shown, the continuous-time Σ-Δ modulator uses a resistor-capacitor (RC) integrator network to integrate the signal. Its sampling capacitor is located at the integrator output. This structural characteristic eliminates the need for an additional anti-aliasing filter, making it particularly suitable for high-frequency applications. Compared to discrete-time structures, the CT architecture avoids the use of switched capacitor circuits, significantly reducing system power consumption. However, due to the inherent thermal noise of the integrating resistor, the thermal noise increases in high-temperature operating environments, which typically limits the effective accuracy of the CT-type Σ-Δ modulator to below 14 bits.

[0005] like Figure 4 As shown, the traditional CT-type Σ-Δ modulator circuit uses a first-order, one-bit structure, namely a first-order modulator (an integrator composed of R1, R2, C1, C2, and A1) and a one-bit quantizer. Single-bit quantization, due to its inherent linearity, is suitable for circuits with significant component mismatch and errors. Single-bit quantization only requires a simple quantizer, placing lower demands on circuit design. Multi-bit quantization, on the other hand, requires a more complex quantizer circuit to distinguish more voltage thresholds, making it more difficult to design. Furthermore, the multi-bit feedback DAC required for multi-bit quantizers exhibits nonlinearity, introducing errors. However, multi-bit quantization can improve the modulator's dynamic range, offering more voltage thresholds and enabling more accurate identification and tracking of input voltages. It can reduce quantization errors and improve the signal-to-noise ratio (SNR). Theoretically, each additional bit in multi-bit quantization can improve the SNR by 6.02 dB. Simultaneously, increasing the number of quantization bits reduces the system's overload requirements and limitations, improving the modulator system's stability to some extent. To highlight the advantages and disadvantages of the old and new schemes and eliminate other influences, one-bit quantization is used uniformly.

[0006] like Figure 4 As shown, the thermal noise of resistors R1 to R4 will all be included in the noise of the modulator, and the thermal noise will increase with the increase of temperature.

[0007]

[0008] In addition, the external input signal Vin varies with temperature in many sensor applications, i.e.

[0009] To obtain a relatively stable output (that does not change with temperature), a temperature sensor needs to be added and corresponding compensation needs to be performed in the digital filter. This will greatly increase the chip area cost and significantly increase the design difficulty. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide an analog-to-digital converter circuit with low noise and temperature compensation to improve output accuracy.

[0011] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A low-noise, temperature-compensated analog-to-digital converter circuit includes multipliers MIX1 and MIX2, resistors R1 and R2, an integrator, a one-bit quantizer circuit, and a feedback loop. The two input terminals of multiplier MIX1 are connected to the input signal Vin. The first output terminal of multiplier MIX1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the first input terminal of multiplier MIX2. The second output terminal of multiplier MIX1 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the second input terminal of multiplier MIX2. The first output of multiplier MIX2 is connected to the first input of integrator and the first output of feedback loop at summing node A. The second output of multiplier MIX2 is connected to the second input of integrator and the second output of feedback loop at summing node B. The first output of integrator is connected to the first input of one-bit quantizer circuit. The second output of integrator is connected to the second input of one-bit quantizer circuit. The first output of one-bit quantizer circuit generates the output signal OUT. The second output of one-bit quantizer circuit is connected to the input of feedback loop.

[0012] Furthermore, the integrator includes an operational amplifier A1, a capacitor C1, and a capacitor C2. The non-inverting input terminal of the operational amplifier A1 is connected to one end of the capacitor C1 and serves as the first input terminal of the integrator. The inverting input terminal of the operational amplifier A1 is connected to one end of the capacitor C2 and serves as the second input terminal of the integrator. The inverting output terminal of the operational amplifier A1 is connected to the other end of the capacitor C1 and serves as the first output terminal of the integrator. The non-inverting output terminal of the operational amplifier A1 is connected to the other end of the capacitor C2 and serves as the second output terminal of the integrator.

[0013] Furthermore, the one-bit quantizer circuit includes a comparator COMP, a D flip-flop DFF, a system clock module OSC, and a digital filter. The non-inverting input of the comparator COMP serves as the first input of the one-bit quantizer circuit, and the inverting input serves as the second input. The output of the comparator COMP is connected to the D terminal of the D flip-flop DFF. The Clk terminal of the D flip-flop DFF is connected to the system clock module OSC, and the Q terminal of the D flip-flop DFF is connected to the input of the digital filter. The output of the digital filter serves as the first output of the one-bit quantizer circuit and generates the output signal OUT. The terminal serves as the second output terminal of a one-bit quantizer circuit.

[0014] Furthermore, the feedback loop includes a 1-bit digital-to-analog converter (DAC) MIX4, a buffer, resistors R3 and R4, and a multiplier MIX3. The first input terminal of the DAC MIX4 is connected to the reference voltage VREF+, and the second input terminal of the DAC MIX4 is connected to the reference voltage VREF-. The control terminal of the DAC MIX4 serves as the input terminal of the feedback loop. The first output terminal of the DAC MIX4 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the first input terminal of the multiplier MIX3. The second output terminal of the DAC MIX4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the second input terminal of the multiplier MIX3. The first output terminal of the multiplier MIX3 serves as the first output terminal of the feedback loop, and the second output terminal of the multiplier MIX3 serves as the second output terminal of the feedback loop.

[0015] Furthermore, the reference voltage VREF+ and reference voltage VREF- are provided by a reference generation temperature compensation circuit.

[0016] Further, the reference temperature compensation circuit includes operational amplifiers A2, A3, A4, and A5, NMOS transistors NM1 and NM2, PMOS transistors PM1 and PM2, resistors R5, R6, R7, R8, R9, a variable resistor R10, and a resistor R11. The non-inverting input of operational amplifier A5 is connected to voltage VBE. The output of operational amplifier A5 is connected to one end of resistor R9 and one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R8 and the inverting input of operational amplifier A5. The other end of resistor R8 is grounded. The other end of resistor R9 is connected to the inverting input of operational amplifier A4 and one end of the variable resistor R10. The non-inverting input of operational amplifier A4 is connected to voltage V1. The output of operational amplifier A4 is connected to the other end of the variable resistor R10 and the non-inverting input of operational amplifier A3. The output of operational amplifier A3 is connected to the gates of PMOS transistors PM1 and PM2. The sources of PMOS transistors PM1 and PM2 are connected to power supply VCC. The drain of PMOS transistor PM1 is connected to the inverting input of operational amplifier A3 and one end of resistor R11. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The other end of resistor R11, the source of NMOS transistor NM1, and the source of NMOS transistor NM2 are grounded. The drain of NMOS transistor NM2 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R5 to generate a reference voltage VREF-. The other end of resistor R5 is connected to the inverting input and output of operational amplifier A2 to generate a reference voltage VREF+. The non-inverting input of operational amplifier A2 is connected to voltage V2.

[0017] Furthermore, the NMOS transistors NM1 and NM2 form a first current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:k.

[0018] Furthermore, the PMOS transistors PM1 and PM2 form a second current mirror, and the current ratio flowing through PMOS transistors PM1 and PM2 is 1:1.

[0019] Compared with the prior art, the present invention has the following advantages and effects: 1. This invention provides an analog-to-digital converter circuit with low noise and temperature compensation, which can significantly reduce noise and improve output accuracy; 2. This invention does not require the additional design of a temperature sensor and digital compensation, saving chip area and reducing design complexity; 3. This invention allows for flexible configuration of the temperature compensation curve and absolute value, making it suitable for various application environments. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an analog-to-digital converter circuit with low noise and temperature compensation according to the present invention.

[0021] Figure 2 This is a schematic diagram of the reference generation temperature compensation circuit of the present invention.

[0022] Figure 3 This is a schematic diagram of a conventional CT-type Σ-Δ modulator in existing technology.

[0023] Figure 4 This is the circuit diagram of a conventional first-order, one-bit CT-type Σ-Δ ADC in existing technology. Detailed Implementation

[0024] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0025] like Figure 1 As shown, this invention provides an analog-to-digital converter circuit with low noise and temperature compensation, comprising a multiplier MIX1, a multiplier MIX2, resistors R1 and R2, an integrator, a one-bit quantizer circuit, and a feedback loop. The two input terminals of multiplier MIX1 are connected to the input signal Vin. The first output terminal of multiplier MIX1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the first input terminal of multiplier MIX2. The second output terminal of multiplier MIX1 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the second input terminal of multiplier MIX2. The first output of multiplier MIX2 is connected to the first input of integrator and the first output of feedback loop at summing node A. The second output of multiplier MIX2 is connected to the second input of integrator and the second output of feedback loop at summing node B. The first output of integrator is connected to the first input of one-bit quantizer circuit. The second output of integrator is connected to the second input of one-bit quantizer circuit. The first output of one-bit quantizer circuit generates the output signal OUT. The second output of one-bit quantizer circuit is connected to the input of feedback loop.

[0026] The integrator includes operational amplifier A1, capacitor C1, and capacitor C2. The non-inverting input terminal of operational amplifier A1 is connected to one end of capacitor C1 and serves as the first input terminal of the integrator. The inverting input terminal of operational amplifier A1 is connected to one end of capacitor C2 and serves as the second input terminal of the integrator. The inverting output terminal of operational amplifier A1 is connected to the other end of capacitor C1 and serves as the first output terminal of the integrator. The non-inverting output terminal of operational amplifier A1 is connected to the other end of capacitor C2 and serves as the second output terminal of the integrator.

[0027] A single-bit quantizer circuit includes a comparator COMP, a D flip-flop DFF, a system clock module OSC, and a digital filter. The non-inverting input of the comparator COMP serves as the first input of the single-bit quantizer circuit, and the inverting input serves as the second input. The output of the comparator COMP is connected to the D terminal of the D flip-flop DFF. The Clk terminal of the D flip-flop DFF is connected to the system clock module OSC, and the Q terminal of the D flip-flop DFF is connected to the input of the digital filter. The output of the digital filter serves as the first output of the single-bit quantizer circuit and generates the output signal OUT. The terminal serves as the second output terminal of a one-bit quantizer circuit.

[0028] The feedback loop includes a 1-bit digital-to-analog converter (DAC) MIX4, a buffer, resistors R3 and R4, and a multiplier MIX3. The first input of the DAC MIX4 is connected to the reference voltage VREF+, and the second input of the DAC MIX4 is connected to the reference voltage VREF-. The control terminal of the DAC MIX4 serves as the input of the feedback loop. The first output of the DAC MIX4 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the first input of the multiplier MIX3. The second output of the DAC MIX4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the second input of the multiplier MIX3. The first output of the multiplier MIX3 serves as the first output of the feedback loop, and the second output of the multiplier MIX3 serves as the second output of the feedback loop.

[0029] The input signal Vin is modulated to a high frequency by multiplier MIX1, converted into current through resistors R1 and R2, and then modulated back to a low frequency after flowing through multiplier MIX2, while the thermal noise of resistors R1 and R2 is modulated to a high frequency. The integrator performs continuous-time integration on the net current at summing nodes A and B, and its output voltage is sent to comparator COMP. The result of comparator COMP is sampled by a D flip-flop (DFF) driven by the system clock module OSC, outputting a one-bit digital signal; when the comparator COMP output is positive, it outputs logic '1', otherwise it outputs logic '0'. This digital signal simultaneously controls a one-bit digital-to-analog converter (DAC) MIX4 in the feedback loop; when the digital signal is '1', DAC MIX4 outputs a negative reference voltage VREF-, and when the digital signal is '0', DAC MIX4 outputs a positive reference voltage VREF+. This feedback voltage is converted into current through feedback resistors R3 and R4. When it passes through multiplier MIX3, the noise is modulated to a high frequency and fed back to the input summing node of the integrator, where it is superimposed with the input analog current.

[0030] The above process constitutes a high-speed negative feedback closed loop. The essential function of this loop is to force the average current at the integrator input to approach zero, that is, to force the average value of the feedback signal to track and approximate the input analog signal. Therefore, in the one-bit digital stream output of the D flip-flop (DFF), the density of '1's (i.e., the duty cycle) directly corresponds to the magnitude of the input analog signal. When the input voltage increases, the feedback loop provides more negative feedback to maintain balance by generating more '1's; conversely, when the input voltage decreases, it generates more '0's. Simultaneously, due to the effect of the feedback loop, the quantization error (i.e., noise) introduced by the quantization process is pushed to the high-frequency band, achieving noise shaping. Finally, this noise-shaped one-bit stream is sent to the subsequent digital filter to filter out the high-frequency quantization noise, thus recovering the high-precision digital signal.

[0031] In summary, this first-order, one-bit continuous-time Σ-Δ modulator effectively achieves high-precision analog-to-digital conversion through a simple analog circuit structure combined with oversampling and negative feedback techniques.

[0032] As can be seen, compared to the traditional Σ-Δ converter, multipliers MIX1, MIX2, and MIX3 modules are added. For the input signal Vin, the input signal remains unchanged after passing through multipliers MIX1 and MIX2. For the thermal noise and mismatch of resistors R1 and R2, only multiplier MIX2 is used, thus shifting the thermal noise and mismatch to a higher frequency (MIX2 frequency). Similarly, the thermal noise and mismatch of feedback resistors R3 and R4 are also shifted to a higher frequency by multiplier MIX3. Subsequent filtering greatly compresses the energy of noise and mismatch, significantly improving the signal-to-noise ratio and increasing the number of effective output bits.

[0033] The reference voltages VREF+ and VREF- are provided by the reference generation temperature compensation circuit.

[0034] like Figure 2 As shown, the reference temperature compensation circuit includes operational amplifiers A2, A3, A4, and A5, NMOS transistors NM1 and NM2, PMOS transistors PM1 and PM2, resistors R5, R6, R7, R8, R9, a variable resistor R10, and a resistor R11. The non-inverting input of operational amplifier A5 is connected to voltage VBE. The output of operational amplifier A5 is connected to one end of resistor R9 and one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R8 and the inverting input of operational amplifier A5. The other end of resistor R8 is grounded. The other end of resistor R9 is connected to the inverting input of operational amplifier A4 and one end of the variable resistor R10. The non-inverting input of operational amplifier A4 is connected to voltage V1. The output of operational amplifier A4 is connected to the other end of the variable resistor R10 and the non-inverting input of operational amplifier A3. The output of operational amplifier A3 is connected to the gates of PMOS transistors PM1 and PM2. The sources of PMOS transistors PM1 and PM2 are connected to power supply VCC. The drain of PMOS transistor PM1 is connected to the inverting input of operational amplifier A3 and one end of resistor R11. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The other end of resistor R11, the source of NMOS transistor NM1, and the source of NMOS transistor NM2 are grounded. The drain of NMOS transistor NM2 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R5 to generate a reference voltage VREF-. The other end of resistor R5 is connected to the inverting input and output of operational amplifier A2 to generate a reference voltage VREF+. The non-inverting input of operational amplifier A2 is connected to voltage V2.

[0035] NMOS transistors NM1 and NM2 form the first current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:k.

[0036] PMOS transistors PM1 and PM2 form a second current mirror, and the current ratio flowing through PMOS transistors PM1 and PM2 is 1:1.

[0037] Voltages V1 and V2 are two independent, stable voltages, neither of which has a temperature coefficient. Voltage VBE is a voltage with a negative temperature coefficient.

[0038] Operational amplifier A1 is connected as a voltage follower or buffer, receiving a temperature-coefficient-free voltage V2 at its non-inverting input, thus providing a low-impedance common-mode voltage point at its output equal to V2. Operational amplifiers A3, A4, and A5, along with resistors R7, R8, R9, R10, and R11, form a branch acting on a negative temperature-coefficient voltage VBE and a temperature-coefficient-free voltage V1, used to generate a current I1 proportional to absolute temperature. Due to the different temperature characteristics of V1 and VBE, their difference voltage exhibits a positive temperature coefficient. This positive temperature-coefficient voltage is applied to resistor R11, thereby generating a current I1 with a positive temperature coefficient.

[0039] The positive temperature coefficient current I1 is precisely mirrored by a current mirror with a ratio of 1:k, generating a positive temperature coefficient current with a ratio of k*I1. This current is injected into the output voltage divider network consisting of resistors R5 and R6. Simultaneously, the output of operational amplifier A2 (i.e., the temperature-independent voltage V1) is applied to one end of resistor R5, providing the common-mode voltage point of VREF. Finally, at the output node VREF, the temperature-independent voltage component is superimposed on the positive temperature coefficient voltage drop generated by the positive temperature coefficient current across resistor R5. By precisely designing the ratio k of the current mirror and the values ​​of resistors R5, R6, and R10, the positive temperature coefficient voltage drop can precisely compensate for the inherent negative temperature coefficient component in the bandgap reference core (mainly reflected in VBE), thereby synthesizing a reference voltage VREF that remains highly stable over a wide temperature range.

[0040] This invention achieves precise temperature compensation by utilizing the inherent voltage resources within the bandgap reference and by flexibly adjusting the gain through a current mirror and resistor ratio. The circuit structure is simple and requires no complex adjustment or external compensation circuitry.

[0041] like Figure 2 The reference temperature compensation circuit shown can be calculated to produce the following:

[0042] V1, V2, and VBE are all generated by the BangGap circuit, requiring no additional circuitry. V1 and V2 are obtained by voltage division from the bandgap reference and have no temperature coefficient. k1=(R7+R8) / R7, k2=R10 / R9, k3=R5 / R11. Therefore, only VBE in the VREF generation has a temperature coefficient. Thus, different VREF values ​​with varying temperature coefficients can be obtained simply by changing the resistor ratios, thereby offsetting the effect of temperature drift in the input signal Vin on the output code value. Furthermore, the VREF value can be adjusted to match Vin by modulating the resistor values.

[0043] This invention provides an analog-to-digital converter circuit with low noise and temperature compensation, which can significantly reduce noise and improve output accuracy. This invention does not require the design of additional temperature sensors and digital compensation, saving chip area and reducing design difficulty. This invention can flexibly configure the temperature compensation curve and absolute value, making it suitable for various application environments.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An analog-to-digital converter circuit with low noise and temperature compensation, characterized in that: It includes multiplier MIX1, multiplier MIX2, resistors R1 and R2, integrator, one-bit quantizer circuit, and feedback loop. The two input terminals of multiplier MIX1 are connected to the input signal Vin. The first output terminal of multiplier MIX1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the first input terminal of multiplier MIX2. The second output terminal of multiplier MIX1 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the second input terminal of multiplier MIX2. The first output terminal of multiplier MIX2 is connected to the first input terminal of integrator and the first output terminal of feedback loop at summing node A. The second output terminal of multiplier MIX2 is connected to the second input terminal of integrator and the second output terminal of feedback loop at summing node B. The first output terminal of integrator is connected to the first input terminal of one-bit quantizer circuit, and the second output terminal of integrator is connected to the second input terminal of one-bit quantizer circuit. The first output terminal of one-bit quantizer circuit generates the output signal OUT, and the second output terminal of one-bit quantizer circuit is connected to the input terminal of feedback loop.

2. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 1, characterized in that: The integrator includes an operational amplifier A1, a capacitor C1, and a capacitor C2. The non-inverting input terminal of the operational amplifier A1 is connected to one end of the capacitor C1 and serves as the first input terminal of the integrator. The inverting input terminal of the operational amplifier A1 is connected to one end of the capacitor C2 and serves as the second input terminal of the integrator. The inverting output terminal of the operational amplifier A1 is connected to the other end of the capacitor C1 and serves as the first output terminal of the integrator. The non-inverting output terminal of the operational amplifier A1 is connected to the other end of the capacitor C2 and serves as the second output terminal of the integrator.

3. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 1, characterized in that: The one-bit quantizer circuit includes a comparator COMP, a D flip-flop DFF, a system clock module OSC, and a digital filter. The non-inverting input of the comparator COMP serves as the first input of the one-bit quantizer circuit, and the inverting input serves as the second input. The output of the comparator COMP is connected to the D terminal of the D flip-flop DFF. The Clk terminal of the D flip-flop DFF is connected to the system clock module OSC, and the Q terminal of the D flip-flop DFF is connected to the input of the digital filter. The output of the digital filter serves as the first output of the one-bit quantizer circuit and generates the output signal OUT. The terminal serves as the second output terminal of a one-bit quantizer circuit.

4. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 1, characterized in that: The feedback loop includes a 1-bit digital-to-analog converter (DAC) MIX4, a buffer, resistors R3 and R4, and a multiplier MIX3. The first input terminal of the DAC MIX4 is connected to the reference voltage VREF+, and the second input terminal of the DAC MIX4 is connected to the reference voltage VREF-. The control terminal of the DAC MIX4 serves as the input terminal of the feedback loop. The first output terminal of the DAC MIX4 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the first input terminal of the multiplier MIX3. The second output terminal of the DAC MIX4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the second input terminal of the multiplier MIX3. The first output terminal of the multiplier MIX3 serves as the first output terminal of the feedback loop, and the second output terminal of the multiplier MIX3 serves as the second output terminal of the feedback loop.

5. The analog-to-digital converter circuit with temperature compensation for low noise as described in claim 4, characterized in that: The reference voltages VREF+ and VREF- are provided by a reference generation temperature compensation circuit.

6. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 5, characterized in that: The reference temperature compensation circuit includes operational amplifiers A2, A3, A4, and A5, NMOS transistors NM1 and NM2, PMOS transistors PM1 and PM2, resistors R5, R6, R7, R8, R9, a variable resistor R10, and a resistor R11. The non-inverting input of operational amplifier A5 is connected to voltage VBE. The output of operational amplifier A5 is connected to one end of resistor R9 and one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R8 and the inverting input of operational amplifier A5. The other end of resistor R8 is grounded. The other end of resistor R9 is connected to the inverting input of operational amplifier A4 and one end of the variable resistor R10. The non-inverting input of operational amplifier A4 is connected to voltage V1. The output of operational amplifier A4 is connected to the other end of the variable resistor R10 and the non-inverting input of operational amplifier A3. The output of amplifier A3 is connected to the gates of PMOS transistors PM1 and PM2. The sources of PMOS transistors PM1 and PM2 are connected to power supply VCC. The drain of PMOS transistor PM1 is connected to the inverting input of operational amplifier A3 and one end of resistor R11. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The other end of resistor R11, the source of NMOS transistor NM1, and the source of NMOS transistor NM2 are grounded. The drain of NMOS transistor NM2 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R5 to generate a reference voltage VREF-. The other end of resistor R5 is connected to the inverting input and output of operational amplifier A2 to generate a reference voltage VREF+. The non-inverting input of operational amplifier A2 is connected to voltage V2.

7. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 6, characterized in that: The NMOS transistors NM1 and NM2 form a first current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:k.

8. The analog-to-digital converter circuit with low noise and temperature compensation according to claim 6, characterized in that: The PMOS transistors PM1 and PM2 form a second current mirror, and the current ratio flowing through PMOS transistors PM1 and PM2 is 1:1.

Images