Power device and method of manufacturing the same

Abstract

This invention discloses a power device, comprising: an interlayer film. A semiconductor substrate is divided into an active region and a termination region. A device unit structure is formed in the active region; a field oxide layer is formed around the periphery of the active region in the termination region. In the active region, the interlayer film covers the top surface of the semiconductor substrate where the device unit structure is formed and forms a first contact hole through the interlayer film. In the termination region, the interlayer film covers the top surface of the field oxide layer. The interlayer film is patterned and etched so that the first thickness of the interlayer film in the termination region and the second thickness of the interlayer film in the active region are independently set. The second thickness is less than or equal to the thickness required by the aspect ratio of the first contact hole, and the first thickness is greater than the second thickness. The reliability of the power device is ensured by increasing the first thickness. This invention also discloses a method for manufacturing the power device. This invention can improve the long-term reliability of the device and is beneficial for expanding the application of the device in the automotive field.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a power device. This invention also relates to a method for manufacturing a power device. Background Technology

[0002] As a core component for energy conversion and transmission, IGBTs have been widely used in key areas such as new energy vehicles, new energy power generation, and smart grids. These applications place unprecedentedly stringent demands on their operational lifespan, environmental adaptability, and stability under extreme conditions. Existing traditional industrial-grade standards are insufficient to meet the stringent failure rate and durability requirements of automotive-grade (AEC-Q101) and industrial control fields. Especially under conditions of high temperature, high humidity, high power density, and continuous power cycling, ensuring the long-term reliability and robustness of IGBTs has become a core bottleneck restricting system safety and technological progress. Therefore, comprehensively improving the intrinsic reliability of IGBTs through technological innovation has significant practical industrial implications. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a power device that improves the long-term reliability of the device and facilitates its application in the automotive field. To this end, this invention also provides a method for manufacturing the power device.

[0004] To solve the above-mentioned technical problems, the power device provided by the present invention includes: an interlayer film formed on the top of a semiconductor substrate.

[0005] The semiconductor substrate is divided into an active region and a terminal region surrounding the active region.

[0006] A device unit structure is formed in the semiconductor substrate in the active region; a field oxide layer is formed on the top surface of the semiconductor substrate in the terminal region, surrounding the periphery of the active region.

[0007] In the active region, the interlayer film covers the top surface of the semiconductor substrate on which the device unit structure is formed, and a first contact hole through the interlayer film is formed on the top of the doped region corresponding to the device unit structure.

[0008] In the terminal region, the interlayer film covers the top surface of the field oxide layer.

[0009] The interlayer film is patterned and etched so that the first thickness of the interlayer film in the terminal region and the second thickness of the interlayer film in the active region are set independently. The second thickness is less than or equal to the thickness required by the aspect ratio of the first contact hole. The first thickness is greater than the second thickness, and the reliability of the power device is ensured by increasing the first thickness.

[0010] A further improvement is that the device unit structure includes a trench gate, the trench gate including a gate trench formed in the semiconductor substrate, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench.

[0011] A second conductivity type doped well region is also formed in the surface region of the semiconductor substrate, and the trench gate extends longitudinally through the well region.

[0012] A heavily doped source region of a first conductivity type is formed in the surface region of the well region, and the top of the source region is connected to the source electrode composed of the front metal layer through the corresponding first contact hole.

[0013] A further improvement is that the terminal region includes a transition region adjacent to the active region; the field oxide layer has an inner surface with an inclined morphology, and the inner surface of the field oxide layer is located in the transition region.

[0014] A gate-connecting polysilicon layer extends from the active region across the inner side of the field oxide layer and to the top surface of the field oxide layer; in the active region, the gate-connecting polysilicon layer and the polysilicon gate connection are present; at the top of the field oxide layer, the top of the gate-connecting polysilicon layer is connected to a gate composed of a front-side metal layer through a second contact hole.

[0015] A further improvement is that the interface of the patterned etching of the interlayer film is located outside the outer side of the gate connection polysilicon layer, and the outer side of the gate connection polysilicon layer is a side extending to the top surface of the field oxide layer.

[0016] After being patterned and etched, the interlayer film undergoes annealing and reflowing, so that the top surface of the interlayer film smoothly transitions from a high position in the terminal region to a low position in the active region.

[0017] A further improvement is that one or more polysilicon field plates are formed on the top surface of the field oxide layer outside the outer side of the gate-connected polysilicon layer.

[0018] The first thickness is the distance between the top surface of the polycrystalline silicon field plate and the top surface of the interlayer film.

[0019] A further improvement is that the interlayer film comprises one or more of undoped silicon dioxide (USG), borosilicate glass (BPSG), phosphosilicate glass (PSG), PETEOS, and silicon-rich oxide (SRO). PETEOS is an oxide formed using a PECVD process with TEOS as the silicon source.

[0020] A further improvement is that the bottom of the first contact hole extends into the semiconductor substrate and contacts the well region.

[0021] The first contact hole consists of a metal layer filling the opening of the first contact hole.

[0022] A second conductivity type heavily doped contact hole injection region is also formed at the bottom of the first contact hole opening.

[0023] A further improvement is that the second thickness is less than or equal to 1.1 micrometers, and the first thickness is greater than 1.1 micrometers.

[0024] A further improvement is that the first thickness is 2 to 4 micrometers.

[0025] A further improvement is that the power device is an IGBT.

[0026] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a power device comprising: A semiconductor substrate is provided, the semiconductor substrate being divided into an active region and a terminal region surrounding the active region; a device unit structure is formed in the semiconductor substrate in the active region; and a field oxide layer surrounding the active region is formed on the top surface of the semiconductor substrate in the terminal region.

[0027] An interlayer film is formed, the interlayer film having a first thickness and covering the top surface of the semiconductor substrate on which the device unit structure is formed and the top surface of the field oxide layer.

[0028] The interlayer film is patterned and etched to reduce the thickness of the interlayer film in the active region to a second thickness, while the interlayer film in the terminal region remains at a first thickness. The second thickness is less than or equal to the thickness required by the aspect ratio of the first contact hole. The reliability of the power device is ensured by increasing the first thickness.

[0029] The interlayer membrane is annealed and reflowed to allow the top surface of the interlayer membrane to smoothly transition from a high position in the terminal region to a low position in the active region.

[0030] Etching is performed to form a contact hole opening, and metal is filled into the contact hole opening to form a contact hole; the contact hole includes a first contact hole located in the active region, the first contact hole passing through the interlayer film and contacting the doped region of the device unit structure corresponding to the bottom.

[0031] A further improvement is that the device unit structure includes a trench gate, the trench gate including a gate trench formed in the semiconductor substrate, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench.

[0032] A second conductivity type doped well region is also formed in the surface region of the semiconductor substrate, and the trench gate extends longitudinally through the well region.

[0033] A heavily doped source region of a first conductivity type is formed in the surface region of the well region, and the top of the source region is connected to the source electrode composed of the front metal layer through the corresponding first contact hole.

[0034] A further improvement is that the terminal region includes a transition region adjacent to the active region; the field oxide layer has an inner surface with an inclined morphology, and the inner surface of the field oxide layer is located in the transition region.

[0035] A gate-connect polysilicon layer extends from the active region across the inner side of the field oxide layer and to the top surface of the field oxide layer; in the active region, the gate-connect polysilicon layer and the polysilicon gate connection; on the top of the field oxide layer; the contact hole further includes a second contact hole located on top of the gate-connect polysilicon layer, through which the gate-connect polysilicon layer is connected to a gate composed of a front metal layer.

[0036] A further improvement is that the interface of the patterned etching of the interlayer film is located outside the outer side of the gate connection polysilicon layer, and the outer side of the gate connection polysilicon layer is a side extending to the top surface of the field oxide layer.

[0037] A further improvement is that one or more polysilicon field plates are formed on the top surface of the field oxide layer outside the outer side of the gate-connected polysilicon layer.

[0038] The first thickness is the distance between the top surface of the polycrystalline silicon field plate and the top surface of the interlayer film.

[0039] A further improvement is that the interlayer membrane comprises a combination of one or more of USG, BPSG, PSG, PETEOS, and SRO.

[0040] A further improvement is that the bottom of the first contact hole extends into the semiconductor substrate and contacts the well region.

[0041] After the contact hole opening is formed, it also includes: Contact hole injection is performed to form a contact hole injection area at the bottom of the first contact hole.

[0042] A further improvement is that the second thickness is less than or equal to 1.1 micrometers, and the first thickness is greater than 1.1 micrometers.

[0043] A further improvement is that the first thickness is 2 to 4 micrometers.

[0044] A further improvement is that the power device is an IGBT.

[0045] In this invention, patterned etching of the interlayer film reduces the thickness of the interlayer film in the active region to a second thickness, while the thickness of the terminal region remains at the initial first thickness. This allows the first and second thicknesses to be set independently. The second thickness meets the requirement for setting the first contact hole in the active region. Because the second thickness is reduced, the aspect ratio of the first contact hole is reduced, thus lowering the difficulty of the opening etching and filling processes for the first contact hole and ensuring its quality. Simultaneously, the reduction in the second thickness does not affect the first thickness of the terminal region. Since increasing the first thickness increases the reliability of the terminal region, the first thickness can be set according to the requirements for increasing the reliability of the terminal region. Ultimately, this improves the long-term reliability of the device and facilitates its application in automotive-grade fields.

[0046] Meanwhile, in this invention, the increased thickness can better modulate the electric field distribution on the surface of the semiconductor substrate in the terminal region, avoid electric field concentration, and thus significantly improve the breakdown voltage of the device.

[0047] In this invention, the increase in the first thickness can also compensate for the adverse effects caused by fluctuations in the doping process in the terminal region, thereby expanding the process window. In this invention, the increased first thickness can also reduce the vertical electric field strength at the edge of the field plate formed on the interlayer film and thus prevent dielectric breakdown caused by high electric field strength. This provides a better foundation for the field plate structure formed in the terminal region, so that the electric field modulation effect applied by the field plate can take effect in a wider lateral range and form a better synergistic effect with the terminal. Attached Figure Description

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of the existing manufacturing method for IGBT devices; Figure 2 This is a cross-sectional structural schematic diagram of the power device according to the first embodiment of the present invention; Figure 3 This is a cross-sectional structural schematic diagram of the power device according to the second embodiment of the present invention; Figure 4 This is a flowchart of a method for manufacturing a power device according to an embodiment of the present invention. Detailed Implementation

[0049] The manufacturing method of the power device in this invention is an improvement on the existing manufacturing method of IGBT devices. Before describing the embodiments of this invention in detail, the existing manufacturing method of IGBT devices will be explained as follows: like Figure 1 The diagram shows a flowchart of an existing IGBT device manufacturing method; the existing IGBT device manufacturing method includes the following steps: Step S101, IGBT TCH loop, indicates that the trench gate (TCH) process loop of the IGBT has been completed. IGBT TCH loop indicates that the trench gate process has been completed, specifically that the IGBT TCH process has been completed, including the formation of the field oxide layer defining the active region, the etching of the gate trench in the active region, the gate oxide growth, and the polysilicon filling.

[0050] Step S102: Deposition (dep) to form an interlayer film (ILD), i.e., ILD dep. The commonly used deposition process is PECVD.

[0051] Step S103: Anneal and reflow the interlayer membrane (ILD reflow). The annealing and reflow conditions are usually 90°C for 30 minutes.

[0052] Step S104: Photolithography defines the formation area of ​​the contact hole (CT), i.e., CT Photo.

[0053] Step S105: Etching is performed to form contact hole openings, i.e., CT ETCH. This etching step involves etching the interlayer film.

[0054] Step S106: Etch the silicon at the bottom of the contact hole opening, i.e., CT silicon ETCH. Typically, the semiconductor substrate of an IGBT is made of silicon. In the active region, the contact hole opening usually needs to penetrate the source region to contact the bottom well region, therefore, silicon etching is required.

[0055] Step S107: Perform contact hole implantation (CT implant) to form a contact hole injection area at the bottom of the contact hole.

[0056] The subsequent process flow is the standard process flow for IGBTs.

[0057] As can be seen, in conventional IGBTs, the interlayer film (ILD), i.e., the dielectric layer, is formed together in the unit cell region and the termination region, with a thickness typically around 1µm. Because the dielectric layer in the unit cell region needs to be connected to the metal layer via (CT) structures, its thickness cannot be too thick; excessive thickness would result in an excessively large aspect ratio for the CT structure, which is detrimental to filling the CT metal. However, the termination region generally does not have CT structures, and device breakdown typically occurs at the termination location; therefore, increasing the anti-interference capability of the termination region is essential.

[0058] like Figure 2The diagram shown is a cross-sectional structural schematic of a power device according to a first embodiment of the present invention. The power device according to the first embodiment of the present invention includes an interlayer film 106 formed on the top of a semiconductor substrate 101.

[0059] The semiconductor substrate 101 is divided into an active region 101a and a terminal region 101c surrounding the active region 101a.

[0060] A device unit structure is formed in the semiconductor substrate 101 of the active region 101a; a field oxide layer 103 is formed on the top surface of the semiconductor substrate 101 of the terminal region 101c, surrounding the active region 101a.

[0061] In the first embodiment of the present invention, the terminal region 101c includes a transition region 101b adjacent to the active region 101a; the transition region 101b belongs to the terminal region 101c but is marked separately by the label 101b. The field oxide layer 103 has an inner surface with an inclined morphology, and the inner surface of the field oxide layer 103 is located in the transition region 101b.

[0062] In the active region 101a, an interlayer film 106 covers the top surface of the semiconductor substrate 101 on which the device unit structure is formed, and a first contact hole (not shown) is formed at the top of the doped region corresponding to the device unit structure, passing through the interlayer film 106.

[0063] In the terminal region 101c, the interlayer film 106 covers the top surface of the field oxide layer 103.

[0064] The interlayer film 106 is patterned and etched so that the first thickness d1 of the interlayer film 106 in the terminal region 101c and the second thickness d2 of the interlayer film 106 in the active region 101a are set independently. The second thickness d2 is less than or equal to the thickness required by the aspect ratio of the first contact hole. The first thickness d1 is greater than the second thickness d2, and the reliability of the power device is ensured by thickening the first thickness d1.

[0065] Figure 2 The first thickness d1 is marked as the distance between the bottom surface and the top surface of the interlayer film 106, and the bottom surface of the interlayer film 106 is also the top surface of the semiconductor substrate 101.

[0066] In the first embodiment of the present invention, the interlayer membrane 106 includes a combination of one or more of USG, BPSG, PSG, PETEOS, and SRO. For example, the interlayer membrane 106 is USG+BPSG, PSG+BPSG, SRO+PSG, or SRO+PETEOS, etc.

[0067] In the first embodiment of the present invention, when the width (CD) of the first contact hole is determined, the maximum value of the depth-to-width ratio can be determined according to the process level. Thus, multiplying the width of the first contact hole by the corresponding maximum value of the depth-to-width ratio will yield the maximum value of the second thickness (d2).

[0068] In some embodiments, the second thickness d2 is less than or equal to 1.1 micrometers, and the first thickness d1 is greater than 1.1 micrometers. Preferably, the first thickness d1 is 2 to 4 micrometers.

[0069] In the first embodiment of the present invention, the device unit structure includes a trench gate 102, which includes a gate trench formed in a semiconductor substrate 101, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench. Figure 2 The image shows only one trench gate 102 in the device unit structure.

[0070] A second conductivity type doped well region (not shown) is also formed in the surface region of the semiconductor substrate 101, and the trench gate 102 extends longitudinally through the well region.

[0071] A heavily doped source region (not shown) of a first conductivity type is formed on the surface region of the well region. The top of the source region is connected to the source electrode, i.e., the emitter, composed of the front metal layer 108, through a corresponding first contact hole. The doped region corresponding to the bottom of the first contact hole is the emitter region, i.e., the source region. The bottom of the first contact hole also extends into the semiconductor substrate 101 and contacts the well region.

[0072] The first contact hole consists of a metal layer filling the opening of the first contact hole. The metal layer includes a metal barrier layer formed by stacking Ti and TiN layers, and a tungsten (CT) layer.

[0073] A second conductivity type heavily doped contact hole injection region is also formed at the bottom of the first contact hole opening.

[0074] In the first embodiment of the present invention, the gate-connecting polysilicon layer 105 extends from the active region 101a across the inner side of the field oxide layer 103 and extends to the top surface of the field oxide layer 103; in the active region 101a, the gate-connecting polysilicon layer 105 and the polysilicon gate are connected; at the top of the field oxide layer 103, the top of the gate-connecting polysilicon layer 105 is connected to the gate composed of the front metal layer 108 through the second contact hole 107.

[0075] In the terminal region 101c, a metal field plate (not shown) formed by the front metal layer 108 is also provided on the top surface of the interlayer membrane 106.

[0076] An oxide layer 104 is also formed between the gate-connected polysilicon layer 105 and the top surface of the semiconductor substrate 101.

[0077] The interface of the patterned etching of the interlayer film 106 is located outside the outer side of the gate connection polysilicon layer 105, which is the side extending to the top surface of the field oxide layer 103.

[0078] After being patterned and etched, the interlayer film 106 undergoes annealing and reflowing, which allows the top surface of the interlayer film 106 to smoothly transition from the high position of the terminal region 101c to the low position in the active region 101a.

[0079] In the first embodiment of the present invention, the power device is an IGBT.

[0080] The well region serves as the channel region, and the surface of the well region covered by the side of the trench gate 102 is used to form the channel. The semiconductor substrate 101 at the bottom of the well region is doped with a first conductivity type and serves as a drift region. Preferably, an epitaxial layer of the first conductivity type is also formed on the semiconductor substrate 101, and the drift region is composed of the epitaxial layer.

[0081] A heavily doped field stop layer 110 of a first conductivity type is also formed on the back side of the semiconductor substrate 101.

[0082] A heavily doped collector region 111 of a second conductivity type is formed on the back side of the field stop layer 110.

[0083] A collector electrode composed of a back metal layer 112 is formed on the back side of the collector region 111.

[0084] Termination structures are formed in the semiconductor substrate 101 of the transition region 101b and the termination region 101c. These termination structures include, for example, junction termination extension (JTE), lateral variable doping (VLD), and field confinement ring (FLR). The termination structures are used to improve lateral breakdown voltage. Figure 2 The dashed line 109 represents the boundary of the depletion region formed between the terminal structure and the well and drift regions when the device is reverse biased.

[0085] In the first embodiment of the present invention, the interlayer film 106 is patterned and etched to reduce the thickness of the interlayer film 106 in the active region 101a to a second thickness d2, while the thickness of the terminal region 101c remains at the initial first thickness d1. This allows the first thickness d1 and the second thickness d2 to be set independently. The second thickness d2 meets the requirement of setting a first contact hole in the active region 101a. Because the second thickness d2 is reduced, the aspect ratio of the first contact hole is reduced, thus reducing the difficulty of the opening etching and filling processes for the first contact hole and ensuring its quality. Simultaneously, the reduction of the second thickness d2 does not affect the first thickness d1 of the terminal region 101c. Since increasing the first thickness d1 increases the reliability of the terminal region 101c, the first thickness d1 can be set according to the requirements for increasing the reliability of the terminal region 101c. Ultimately, this improves the long-term reliability of the device and facilitates its application in automotive-grade fields.

[0086] Meanwhile, in the first embodiment of the present invention, the increase in the first thickness d1 can better modulate the electric field distribution on the surface of the semiconductor substrate 101 of the terminal region 101c, avoid electric field concentration, and thus significantly improve the breakdown voltage of the device.

[0087] In the first embodiment of the present invention, the increase in the first thickness d1 can also compensate for the adverse effects caused by the doping process fluctuations in the terminal region 101c, thereby expanding the process window.

[0088] In the first embodiment of the present invention, the increase in the first thickness d1 can also reduce the vertical electric field strength at the edge of the field plate formed on the interlayer film 106 and thus prevent dielectric breakdown caused by high electric field strength. This provides a better foundation for the field plate structure formed in the terminal region 101c, so that the electric field modulation effect applied by the field plate can take effect in a wider lateral range and form a better synergistic effect with the terminal.

[0089] like Figure 3 The diagram shown is a cross-sectional view of the power device according to the second embodiment of the present invention. The difference between the power device and the power device according to the first embodiment of the present invention is that, in the power device of the second embodiment of the present invention, one or more polysilicon field plates 105a are formed on the top surface of the field oxide layer 103 on the outer side of the gate-connected polysilicon layer 105.

[0090] The first thickness d1 is the distance between the top surface of the polycrystalline silicon field plate 105a and the top surface of the interlayer film 106.

[0091] In the terminal region 101c, a metal field plate 108a formed by the front metal layer 108 is also provided on the top surface of the interlayer membrane 106.

[0092] like Figure 4The diagram shown is a flowchart of a method for manufacturing a power device according to an embodiment of the present invention. This method is used to manufacture the power device of the first embodiment and the power device of the second embodiment. The structure of the manufactured device is shown in the attached diagram. Figure 2 As shown, the manufacturing method of the power device in this embodiment of the invention includes the following steps: Step S101: Provide a semiconductor substrate 101, which is divided into an active region 101a and a terminal region 101c surrounding the active region 101a; form a device unit structure in the semiconductor substrate 101 of the active region 101a; and form a field oxide layer 103 surrounding the active region 101a on the top surface of the semiconductor substrate 101 of the terminal region 101c.

[0093] In the method of this embodiment, the terminal region 101c includes a transition region 101b adjacent to the active region 101a; the transition region 101b belongs to the terminal region 101c but is marked separately by the label 101b. The field oxide layer 103 has an inner surface with an inclined morphology, and the inner surface of the field oxide layer 103 is located in the transition region 101b.

[0094] In the first embodiment of the present invention, the device unit structure includes a trench gate 102, which includes a gate trench formed in a semiconductor substrate 101, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench. Figure 2 The image shows only one trench gate 102 in the device unit structure.

[0095] A second conductivity type doped well region (not shown) is also formed in the surface region of the semiconductor substrate 101, and the trench gate 102 extends longitudinally through the well region.

[0096] A source region (not shown) heavily doped with the first conductivity type is formed in the surface region of the well region.

[0097] In the method of this embodiment of the invention, the gate-connected polysilicon layer 105 extends from the active region 101a across the inner side of the field oxide layer 103 and extends to the top surface of the field oxide layer 103; in the active region 101a, the gate-connected polysilicon layer 105 and the polysilicon gate connection are connected. An oxide layer 104 is also formed between the gate-connected polysilicon layer 105 and the top surface of the semiconductor substrate 101.

[0098] When forming the power device of the second embodiment of the present invention, one or more polysilicon field plates 105a are formed on the top surface of the field oxide layer 103 on the outer side of the gate-connected polysilicon layer 105.

[0099] In the method of this embodiment, the power device is an IGBT, the well region serves as the channel region, and the surface of the well region covered by the side of the trench gate 102 is used to form the channel. The semiconductor substrate 101 at the bottom of the well region is doped with a first conductivity type and serves as the drift region. Preferably, an epitaxial layer of the first conductivity type is also formed on the semiconductor substrate 101, and the drift region is composed of the epitaxial layer. Termination structures are formed in the semiconductor substrate 101 of the transition region 101b and the termination region 101c. The termination structures are, for example, junction termination extension (JTE), lateral variable doping (VLD), and field limiting ring (FLR). The termination structures are used to improve the lateral breakdown voltage. Figure 2 The dashed line 109 represents the boundary of the depletion region formed between the terminal structure and the well and drift regions when the device is reverse biased.

[0100] In some embodiments, the semiconductor substrate 101 is made of silicon.

[0101] Book Figure 4 In this context, step S101 is also known as the IGBT TCH loop. This indicates the completion of the IGBT trench gate (TCH) process loop. The IGBT TCH loop signifies the completion of the trench gate process, and also the completion of... Figure 2 The device structure before the formation of the interlayer film 106.

[0102] Step S102: Deposit (dep) to form an interlayer film (ILD) 106, i.e., ILD dep, the interlayer film 106 having a first thickness d1 and covering the top surface of the semiconductor substrate 101 on which the device unit structure is formed and the top surface of the field oxide layer 103.

[0103] In the method of this embodiment of the invention, the interlayer membrane 106 includes a combination of one or more of USG, BPSG, PSG, PETEOS, and SRO. For example, the interlayer membrane 106 is USG+BPSG, PSG+BPSG, SRO+PSG, or SRO+PETEOS, etc.

[0104] Patterning etching is performed on the interlayer film 106 to reduce the thickness of the interlayer film 106 in the active region 101a to a second thickness d2, while maintaining the first thickness d1 in the terminal region 101c. The second thickness d2 is less than or equal to the thickness required by the aspect ratio of the first contact hole. The reliability of the power device is ensured by increasing the first thickness d1. The patterning etching of the interlayer film 106 includes two sub-steps located in the dashed box 201, namely: Step S201, ILD photo, i.e., photolithography, defines the area of ​​ILD, i.e., the interlayer film 106, that needs to be etched.

[0105] In the method of this embodiment, the interface position of the patterned etching of the interlayer film 106 is located outside the outer side of the gate connection polysilicon layer 105, and the outer side of the gate connection polysilicon layer 105 is the side extending to the top surface of the field oxide layer 103.

[0106] Step S202, ILD ETCH, involves etching the ILD according to the photolithography definition. ILD etching can be performed using dry etching or wet etching.

[0107] Step S103: Perform annealing and reflow on the interlaminar membrane 106, i.e., ILD reflow. This allows the top surface of the interlaminar membrane 106 to smoothly transition from the high position in the terminal region 101c to the low position in the active region 101a.

[0108] In some implementation methods, the annealing and reflow conditions are typically 900°C for 30 minutes.

[0109] Figure 2 The first thickness d1 is marked as the distance between the bottom surface and the top surface of the interlayer film 106, and the bottom surface of the interlayer film 106 is also the top surface of the semiconductor substrate 101.

[0110] exist Figure 3 In the power device of the corresponding second embodiment of the present invention, the first thickness d1 is the distance between the top surface of the polysilicon field plate 105a and the top surface of the interlayer film 106.

[0111] In the method of this invention, given that the width (CD) of the first contact hole is determined, the maximum aspect ratio can be determined based on the manufacturing process. Therefore, multiplying the width of the first contact hole by the corresponding maximum aspect ratio yields the maximum value of the second thickness d2. In some embodiments, the second thickness d2 is less than or equal to 1.1 micrometers, and the first thickness d1 is greater than 1.1 micrometers. Preferably, the first thickness d1 is 2 to 4 micrometers.

[0112] Step S104: Photolithography defines the formation area of ​​the contact hole (CT), i.e., CT Photo.

[0113] Step S105: Etching is performed to form contact hole openings, i.e., CT ETCH. This etching step involves etching the interlayer film 106.

[0114] Step S106: Etch the silicon at the bottom of the contact hole opening, i.e., CT silicon ETCH. In this embodiment of the invention, the semiconductor substrate 101 is made of silicon. Typically, in the active region 101a, the contact hole opening needs to penetrate the source region to contact the bottom well region of the source region, therefore, silicon etching is required.

[0115] Step S107: Perform contact hole implantation (CT implant) to form a contact hole injection area at the bottom of the first contact hole.

[0116] Following that, it also includes: The contact hole is formed by filling the opening with metal. The filling metal layer includes a metal barrier layer formed by stacking Ti layer and TiN layer and a tungsten layer (CT metal).

[0117] The contact hole includes a first contact hole located in the active region 101a. The first contact hole passes through the interlayer film 106 and is in contact with the doped region of the corresponding device unit structure at the bottom, such as the source region or emitter region.

[0118] The method also includes forming a front metal layer 108 and patterning the front metal layer 108 to form the source, i.e., the emitter and the gate. In some embodiments, the method further includes forming a metal field plate. The top of the source region is connected to the source formed by the front metal layer 108 through a corresponding first contact hole. The contact hole also includes a second contact hole 107 located on top of the gate-connecting polysilicon layer 105, through which the gate-connecting polysilicon layer 105 is connected to the gate formed by the front metal layer 108.

[0119] The following back-side processes will also be included: The semiconductor substrate 101 is back-side thinned, and a field-stop layer 110 of a first conductivity type is formed on the back side of the thinned semiconductor substrate 101. The field-stop layer 110 is formed by back-side implantation or is directly composed of the thinned semiconductor substrate 101 of the first conductivity type.

[0120] A collector region 111 of a second conductivity type is formed on the back side of the field stop layer 110 by back-side implantation.

[0121] A collector electrode composed of a back metal layer 112 is formed on the back side of the collector region 111.

[0122] and Figure 1 Compared with the existing IGBT device manufacturing method shown, the method of the present invention adds steps S201 and S202 shown in dashed box 201. Through steps S201 and S202, the method of the present invention realizes independent adjustment of the first thickness d1 and the second thickness d2, thereby eliminating the problem of conflicting thickness requirements for the interlayer film 106 in the active region 101a and the terminal region 101c, thus enabling the structure in the active region 101a and the terminal region 101c to be optimized simultaneously.

[0123] The method described in this invention improves the film structure of the IGBT and optimizes the surface electric field distribution, which can effectively improve the long-term reliability of the IGBT and facilitate the expansion of IGBT applications in the automotive field.

[0124] In conventional IGBTs, the interlayer dielectric (ILD) of the unit cell region and the termination region is formed together, with a thickness typically around 1µm. Because the dielectric layer in the unit cell region needs to be connected to the metal layer vias (CTs), its thickness cannot be too thick; excessive thickness would result in an excessively large aspect ratio for the CT structure, hindering the filling of the CT metal. However, the termination region generally lacks CT structures, and device breakdown typically occurs at the termination location; therefore, enhancing the interference immunity of the termination region is essential.

[0125] The method of this invention achieves ILDs with different thicknesses in the cell region and terminal region by adding ILD photo and ILD etch process steps after ILD dep. The components of a conventional IGBT ILD are generally USG and BPSG in different thickness combinations, such as 2000A PSG + 9000A BPSG, 3000A PSG + 8000A BPSG, etc., with a total thickness of 1.1µm; or 2000A SRO + 9000A PSG, with a total thickness of 1.1µm; or SRO + PETEOS, etc. If the ILD in the cell region is too thick, it will lead to an excessively large aspect ratio of the CT etch. For example, the CT CD is 0.4µm for a 2.4µm pitch IGBT and 0.2µm for a 1.6µm pitch IGBT. Furthermore, the CT etch not only needs to penetrate the ILD but also into the silicon substrate, typically with an etching depth of 0.4µm. This results in aspect ratios of 4:1 and 8:1, respectively. An excessively large aspect ratio will lead to abnormal CT morphology and hinder the subsequent filling of barrier metal and CT metal. However, the termination region generally lacks a CT structure, or its CT CD is larger than that of the cell region. Additionally, the surface of the termination region is susceptible to impurity ions. Therefore, increasing the ILD thickness in the termination region is essential. The method of this invention achieves an ILD thickness (d1) > 1.1 µm in the terminal region, and can be made 2-4 µm or even thicker. The ILD composition can be USG, BPSG, PSG, PETEOS, SRO, or different combinations thereof. In particular, the method of this invention performs ILD reflow after ILDETCH. This is to make the transition between the terminal and unit cell regions of the ILD smoother, which is beneficial for subsequent field plate structures.

[0126] The method of this invention, by increasing the thickness of the dielectric layer in the terminal region, offers the following advantages: This can significantly improve the breakdown voltage. Taking JTE termination as an example, the mechanism is explained as follows: First, the dielectric / passivation layer on the surface and the charges inside it significantly affect the electric field distribution on the silicon surface. Thickering the dielectric layer is equivalent to adding an additional vertical distance between the semiconductor surface and the external environment (or subsequent metal field plates). According to Gauss's law, the electric field intensity in the dielectric varies with its thickness and dielectric constant. A thicker dielectric layer can better modulate (usually flatten) the electric field distribution on the termination region surface, avoiding excessive concentration of the electric field at a certain point in the JTE region. This promotes a more uniform expansion of the depletion region, making the actual breakdown voltage of the device closer to the theoretical breakdown limit of silicon. Therefore, the breakdown voltage is improved.

[0127] Thicker dielectric layers can enhance long-term reliability by effectively suppressing surface ion migration. Under high temperature and pressure conditions, mobile ions (such as Na⁺ and K⁺) or interface charges in the dielectric layer may migrate and accumulate under the influence of an electric field, as seen on the surface. This charge accumulation distorts the originally designed surface electric field, leading to an increase in the peak electric field and making the device more susceptible to premature failure or performance degradation. Thicker dielectric layers themselves reduce the peak electric field on the surface. A lower electric field directly means less driving force for charge injection and accumulation, mitigating reliability problems at their source. Thicker dielectric layers can significantly improve device performance in reliability tests such as HTRB and H3TRB, making device parameters (such as leakage current) more stable and extending lifespan.

[0128] It can expand the process window; an optimized thick dielectric layer can partially compensate for process fluctuations in the termination region. Even if the doping value of the termination ring is not ideal, the thick dielectric layer can still "smooth" and "stabilize" the electric field, making the device's breakdown voltage less sensitive to changes in the termination injection process and improving production yield.

[0129] This provides a better foundation for the field plate structure. Typically, a very high vertical electric field is introduced at the edge of the field plate, which can cause the dielectric layer itself to break down. Thickening the dielectric layer in the termination region reduces the vertical electric field intensity at the field plate edge, preventing dielectric layer breakdown. This allows the electric field modulation effect applied by the field plate to take effect over a wider lateral range, creating a better synergistic effect with the termination.

[0130] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A power device, characterized by: An interlayer film is formed on top of the semiconductor substrate; The semiconductor substrate is divided into an active region and a terminal region surrounding the active region. A device unit structure is formed in the semiconductor substrate in the active region; a field oxide layer surrounding the periphery of the active region is formed on the top surface of the semiconductor substrate in the terminal region. In the active region, the interlayer film covers the top surface of the semiconductor substrate on which the device unit structure is formed, and a first contact hole through the interlayer film is formed on the top of the doped region corresponding to the device unit structure. In the terminal region, the interlayer film covers the top surface of the field oxide layer; The interlayer film is patterned and etched so that the first thickness of the interlayer film in the terminal region and the second thickness of the interlayer film in the active region are set independently. The second thickness is less than or equal to the thickness required by the aspect ratio of the first contact hole. The first thickness is greater than the second thickness, and the reliability of the power device is ensured by increasing the first thickness.

2. The power device of claim 1, wherein: The device unit structure includes a trench gate, which includes a gate trench formed in the semiconductor substrate, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench. A well region doped with a second conductivity type is also formed in the surface region of the semiconductor substrate, and the trench gate extends longitudinally through the well region; A heavily doped source region of a first conductivity type is formed in the surface region of the well region, and the top of the source region is connected to the source electrode composed of the front metal layer through the corresponding first contact hole.

3. The power device of claim 2, wherein: The terminal region includes a transition region adjacent to the active region; the field oxide layer has an inner surface with an inclined morphology, and the inner surface of the field oxide layer is located in the transition region; A gate-connecting polysilicon layer extends from the active region across the inner side of the field oxide layer and to the top surface of the field oxide layer; in the active region, the gate-connecting polysilicon layer and the polysilicon gate connection are present; at the top of the field oxide layer, the top of the gate-connecting polysilicon layer is connected to a gate composed of a front-side metal layer through a second contact hole.

4. The power device as described in claim 3, characterized in that: The interface of the patterned etching of the interlayer film is located outside the outer side of the gate connection polysilicon layer, and the outer side of the gate connection polysilicon layer is a side extending to the top surface of the field oxide layer. After being patterned and etched, the interlayer film undergoes annealing and reflowing, so that the top surface of the interlayer film smoothly transitions from a high position in the terminal region to a low position in the active region.

5. The power device as described in claim 3, characterized in that: On the top surface of the field oxide layer outside the outer side of the gate-connected polysilicon layer, one or more polysilicon field plates are also formed. The first thickness is the distance between the top surface of the polycrystalline silicon field plate and the top surface of the interlayer film.

6. The power device as described in claim 1, characterized in that: The interlayer membrane includes a combination of one or more of USG, BPSG, PSG, PETEOS, and SRO.

7. The power device of claim 2, wherein: The bottom of the first contact hole also extends into the semiconductor substrate and contacts the well region; The first contact hole is composed of a metal layer filling the opening of the first contact hole; A second conductivity type heavily doped contact hole injection region is also formed at the bottom of the first contact hole opening.

8. The power device of claim 1, wherein: The second thickness is less than or equal to 1.1 micrometers, and the first thickness is greater than 1.1 micrometers.

9. The power device as described in claim 8, characterized in that: The first thickness is 2 micrometers to 4 micrometers.

10. The power device of claim 1, wherein: The power device is an IGBT.

11. A method for manufacturing a power device, characterized in that: A semiconductor substrate is provided, the semiconductor substrate being divided into an active region and a terminal region surrounding the periphery of the active region; a device unit structure is formed in the semiconductor substrate in the active region; and a field oxide layer surrounding the periphery of the active region is formed on the top surface of the semiconductor substrate in the terminal region. An interlayer film is formed, the interlayer film having a first thickness and covering the top surface of the semiconductor substrate on which the device unit structure is formed and the top surface of the field oxide layer; The interlayer film is patterned and etched to reduce the thickness of the interlayer film in the active region to a second thickness, while the interlayer film in the terminal region remains at a first thickness. The second thickness is less than or equal to the thickness required by the aspect ratio of the first contact hole. The reliability of the power device is ensured by increasing the first thickness. The interlayer membrane is annealed and reflowed to allow the top surface of the interlayer membrane to smoothly transition from a high position in the terminal region to a low position in the active region. Etching is performed to form a contact hole opening, and metal is filled into the contact hole opening to form a contact hole; the contact hole includes a first contact hole located in the active region, the first contact hole passing through the interlayer film and contacting the doped region of the device unit structure corresponding to the bottom.

12. The method of manufacturing a power device according to Claim 11, wherein: The device unit structure includes a trench gate, which includes a gate trench formed in the semiconductor substrate, a gate dielectric layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench. A well region doped with a second conductivity type is also formed in the surface region of the semiconductor substrate, and the trench gate extends longitudinally through the well region; A heavily doped source region of a first conductivity type is formed in the surface region of the well region, and the top of the source region is connected to the source electrode composed of the front metal layer through the corresponding first contact hole.

13. The method for manufacturing a power device as described in claim 12, characterized in that: The terminal region includes a transition region adjacent to the active region; the field oxide layer has an inner surface with an inclined morphology, and the inner surface of the field oxide layer is located in the transition region; A gate-connect polysilicon layer extends from the active region across the inner side of the field oxide layer and to the top surface of the field oxide layer; in the active region, the gate-connect polysilicon layer and the polysilicon gate connection; on the top of the field oxide layer; the contact hole further includes a second contact hole located on top of the gate-connect polysilicon layer, through which the gate-connect polysilicon layer is connected to a gate composed of a front metal layer.

14. The method of manufacturing a power device according to Claim 13, wherein: The interface of the patterned etching of the interlayer film is located outside the outer side of the gate-connected polysilicon layer, which is a side extending to the top surface of the field oxide layer.

15. The method of manufacturing a power device according to Claim 13, wherein: On the top surface of the field oxide layer outside the outer side of the gate-connected polysilicon layer, one or more polysilicon field plates are also formed. The first thickness is the distance between the top surface of the polycrystalline silicon field plate and the top surface of the interlayer film.

16. The method of manufacturing a power device according to Claim 11, wherein: The interlayer membrane includes a combination of one or more of USG, BPSG, PSG, PETEOS, and SRO.

17. The method of manufacturing a power device according to Claim 12, wherein: The bottom of the first contact hole also extends into the semiconductor substrate and contacts the well region; After the contact hole opening is formed, it also includes: Contact hole injection is performed to form a contact hole injection area at the bottom of the first contact hole.

18. The method of manufacturing a power device according to Claim 11, wherein: The second thickness is less than or equal to 1.1 micrometers, and the first thickness is greater than 1.1 micrometers.

19. The method of manufacturing a power device according to Claim 18, wherein: The first thickness is 2 micrometers to 4 micrometers.

20. The method of manufacturing a power device of claim 11, wherein: The power device is an IGBT.

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