Fabrication method of fan-out package structure

Abstract

This application discloses a method for fabricating a fan-out package structure, belonging to the field of semiconductor packaging technology. By using a non-photosensitive dielectric material for the first insulating layer in contact with the release layer, and at least one non-bottom insulating layer using a photosensitive polyimide material, a material architecture is achieved. The hygroscopic photosensitive polyimide is used on the upper layer to form high-density fine lines, while a non-photosensitive material with insulating, oxygen- and moisture-proof properties is used as the bottom layer. This achieves complete coverage and atmospheric isolation of the photosensitive polyimide, fundamentally solving the problem of redistribution layer delamination caused by moisture absorption, and significantly improving product reliability. In terms of process flow, the design of "constructing a multi-layer redistribution structure → forming microbumps → chip mounting → molding → debonding → forming external terminals" combined with single-stage panel-level molding, along with a pre-fabricated redistribution layer structure, significantly simplifies the process and reduces costs through a pre-wiring approach.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a fan-out packaging structure. Background Technology

[0002] With the continuous development of semiconductor technology, chip packaging technology is also constantly innovating to meet the demands of miniaturization, high performance, and high reliability in electronic products. Fan-out packaging, as an advanced packaging technology, has attracted widespread attention from the industry because it can overcome the limitations of the number of I / Os on the chip itself, provide higher interconnect density, better heat dissipation performance, and smaller package size.

[0003] Traditional fan-out packaging technologies typically employ wafer-level or panel-level processes. These technologies generally include key steps such as forming a redistribution layer on a temporary carrier, chip mounting, molding, removing the temporary carrier, and forming external interconnect terminals. In this process, the multilayer redistribution structure is crucial for achieving high-density interconnects, and the choice of insulating layer material and its stacking structure have a decisive impact on the electrical performance, mechanical reliability, and manufacturing cost of the package structure. Currently commonly used dielectric materials include photosensitive polyimide, epoxy resin-based Ajinomoto additive layers, and photosensitive insulating resins.

[0004] However, existing fan-out packaging technologies, especially in advanced panel-level packaging that pursues low-cost advantages, still face many serious challenges and shortcomings:

[0005] 1. Interface delamination defects caused by material moisture absorption: Photosensitive polyimide materials, widely used to achieve high-density wiring, have a molecular structure that makes them highly susceptible to absorbing moisture from the atmosphere. If the surface of the insulating layer containing this material is not adequately covered and protected in subsequent processes (such as chip mounting and molding), the absorbed moisture will rapidly vaporize and generate enormous pressure during high-temperature processes (such as reflow soldering). This can easily lead to delamination and blistering between the redistribution layer and the insulating layer, or within the insulating layer itself, severely affecting product yield and long-term reliability.

[0006] 2. Complex six-sided packaging (double-sided molding) process leads to increased costs and defect rates: To achieve comprehensive protection for chips and fine circuitry, traditional packaging methods typically require molding on both sides of the structure. This six-sided packaging process introduces multiple complex steps (such as board transfer, double-sided molding, grinding, board removal, etc.), which not only makes the process cumbersome and the production cycle long, but also significantly increases packaging costs due to the multiple processing of thin and easily warped boards. At the same time, it introduces higher defect risks such as wafer / panel warping, mechanical stress damage, and misalignment.

[0007] 3. Inherent Uniformity and Defect Issues in Panel-Level Processes: Compared to wafer-level processes, achieving process uniformity over a larger area is drastically more difficult in panel-level processes. This directly leads to a series of defects on the IC board (i.e., the packaging structure itself):

[0008] Redistribution layer defects: On large-area panels, the inhomogeneity of photolithography, electroplating and etching processes can easily cause problems such as open circuits, short circuits, uneven line width / spacing, insufficient via filling or electroplating voids in metal circuits.

[0009] Interlayer alignment defects: Warping and expansion of the panel during multiple hot pressing processes can seriously affect the alignment accuracy between layers in a multilayer rewiring structure, leading to poor connection between micro-bumps and lower layer circuits, or even short circuits.

[0010] Molding process defects: Panel-level molding is prone to defects such as incomplete encapsulation, pores, and chip displacement due to problems such as filler distribution and uneven mold flow. At the same time, the internal stress caused by the mismatch of thermal expansion coefficients between the molding compound and the chip and redistribution layer is also a potential risk to induce interface delamination and cracks.

[0011] Therefore, there is an urgent need for a fan-out packaging fabrication method that can balance high reliability, high yield, and low cost to solve the inherent defects in the aforementioned materials, structures, and panel-level processes. Summary of the Invention

[0012] To address the reliability risks posed by the moisture absorption of photosensitive polyimide in existing technologies, as well as the high manufacturing costs and poor panel-level process reliability caused by the cumbersome double-sided molding process, this paper provides a method for preparing a fan-out packaging structure. This method aims to effectively solve the reliability problems caused by the moisture absorption of photosensitive polyimide materials, while significantly simplifying the packaging process, reducing manufacturing costs, improving panel-level process reliability, and ultimately ensuring that the packaging structure has excellent performance and reliability.

[0013] This application provides a method for fabricating a fan-out packaging structure, including:

[0014] A substrate is provided, and a release layer is formed on the substrate;

[0015] At least three patterned insulating layers and a rewiring layer disposed therebetween are sequentially constructed on the release layer to form a multilayer rewiring structure; wherein, the first insulating layer in contact with the release layer is made of a non-photosensitive dielectric material, and at least one insulating layer other than the bottom layer is made of a photosensitive polyimide material.

[0016] Micro-bumps are formed on the top layer of the multi-layer rewiring structure;

[0017] At least one chip is mounted onto the multilayer redistribution structure via a non-conductive thin film, and the pads of the chip are electrically connected to the microbumps.

[0018] The chip and the microbumps around the chip are encapsulated using a panel-level molding process;

[0019] The substrate is debonded, merged, and cleaned to expose the bottommost redistribution layer of the multilayer redistribution structure.

[0020] Solder is printed on the exposed redistribution layer to form external connection terminals.

[0021] Optionally, constructing the multi-layer rerouting structure includes:

[0022] A first redistribution layer is formed on the first insulating layer, wherein the first insulating layer is an additive layer material or an additive film material.

[0023] A second insulating layer is formed on the first redistribution layer, the second insulating layer being made of a photosensitive polyimide material;

[0024] A second rewiring layer is formed on the second insulating layer;

[0025] A third insulating layer is formed on the second redistribution layer. The third insulating layer is made of a layering film material, and the third insulating layer and the first insulating layer cover the second insulating layer.

[0026] Optionally, the process of encapsulating the chip and the microbumps around the chip using a panel-level molding process includes:

[0027] The chip and the upper surface of the third insulating layer are encapsulated using a panel-level molding process.

[0028] Optionally, constructing the multi-layer rerouting structure includes:

[0029] A first redistribution layer is formed on the first insulating layer, wherein the first insulating layer is made of an additive film material;

[0030] A second insulating layer is formed on the first redistribution layer. The second insulating layer is made of photosensitive polyimide material, and the area of ​​the second insulating layer is smaller than the area of ​​the first insulating layer, so that the second insulating layer is confined to the central region of the surface of the first insulating layer.

[0031] A second rewiring layer is formed on the second insulating layer;

[0032] A third insulating layer is formed on the second redistribution layer, the third insulating layer being made of photosensitive polyimide material.

[0033] Optionally, the process of encapsulating the chip and the microbumps around the chip using a panel-level molding process includes:

[0034] The panel-level molding process is adopted, and epoxy molding compound is used to encapsulate the chip, the periphery of the third insulating layer, the periphery of the second insulating layer, and the upper surface of the first insulating layer.

[0035] Optionally, the step of creating passivation openings in the insulating layer using photosensitive polyimide material includes: processing by photolithography through exposure and development, resulting in an opening aperture of less than or equal to 10 μm.

[0036] Optionally, at least three patterned insulating layers and a rewiring layer disposed therebetween are sequentially constructed on the release layer to form a multi-layer rewiring structure, wherein the formation of each rewiring layer includes:

[0037] A seed layer is deposited on the corresponding insulating layer by sputtering or chemical plating, and the target metal wiring pattern is formed by photolithography, electroplating and etching processes. The thickness of the electroplated copper ranges from 2μm to 8μm, and the line width / line spacing is less than or equal to 5μm.

[0038] Optionally, forming microbumps on the uppermost layer of the multilayer redistribution structure includes:

[0039] A passivation opening is made on the uppermost insulating layer of the multilayer rewiring structure, and copper pillars or tin-silver solder balls are formed in the opening using electroplating or ball-planting processes. The height of the bumps ranges from 10μm to 30μm, and the diameter ranges from 30μm to 80μm.

[0040] Optionally, the panel-level molding process includes:

[0041] The epoxy molding compound is injected into the cavity at a temperature of 150℃-180℃ and a pressure of 8MPa-15MPa using the transfer molding method. The molding thickness is controlled to be 1.2-1.5 times the chip thickness. After molding, the compound is cured at 175℃-185℃ for 1-3 hours.

[0042] Optionally, the unbonding of the substrate includes:

[0043] The release layer is separated from the substrate by laser ablation or thermal conduction. The laser wavelength is 248nm-355nm and the energy density is 100mJ / cm²-300mJ / cm². After debonding, residual organic matter is cleaned by oxygen plasma.

[0044] In this technical solution, the fabrication method of the fan-out packaging structure of this application uses a non-photosensitive dielectric material for the first insulating layer in contact with the release layer, and a photosensitive polyimide (PSPI) material structure for at least one non-bottom insulating layer. The hygroscopic photosensitive polyimide is used in the upper layer to form high-density fine lines, while a non-photosensitive material with insulating, oxygen- and moisture-proof properties is used as the bottom layer. This achieves complete coverage of the photosensitive polyimide and isolation from the atmosphere, fundamentally solving the problem of redistribution layers (RDLs) caused by moisture absorption. The layering problem is significantly improved, enhancing product reliability. In terms of process flow, the overall design of "building a multi-layer redistribution structure → forming microbumps → chip mounting → molding → debonding → forming external terminals" combined with single-panel-level molding and pre-fabricated redistribution layer structure eliminates multiple processes such as board transfer, secondary molding and grinding in traditional six-sided packaging by pre-wiring, greatly simplifying the process and reducing costs. This systematically provides a highly reliable, highly manufacturable and more commercially competitive technical implementation path for panel-level fan-out packaging. Attached Figure Description

[0045] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0046] Figure 1 This is a flowchart illustrating one embodiment of the method for fabricating the fan-out packaging structure described in Embodiment 1 of this application.

[0047] Figures 2-1 to 2-8 This is a schematic diagram of the packaging structure fabrication process of one embodiment of the fabrication method of the fan-out packaging structure described in Example 2;

[0048] Figures 3-1 to 3-8 This is a schematic diagram of the packaging structure fabrication process of one embodiment of the method for fabricating the fan-out packaging structure described in Example 3.

[0049] The names of the parts referred to by the numbers in the attached diagram are as follows:

[0050] Substrate 1, release layer 2, multilayer redistribution structure 3, first redistribution layer 31, second redistribution layer 32, opening 4, insulating layer 5, first insulating layer 51, second insulating layer 52, third insulating layer 53, microbump 6, chip 7, epoxy molding compound 8, connection terminal 9. Detailed Implementation

[0051] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0053] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0054] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0055] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0056] The method for fabricating the fan-out packaging structure in this application is mainly applied to IC substrates and PCB materials. By using a non-photosensitive dielectric material for the first insulating layer in contact with the release layer, and a photosensitive polyimide material for at least one non-bottom insulating layer, the hygroscopic photosensitive polyimide is used on the upper layer to form high-density fine lines. Simultaneously, a non-photosensitive material with insulating, oxygen- and moisture-proof properties is used as the bottom layer, achieving complete coverage and atmospheric isolation of the photosensitive polyimide. This fundamentally solves the problem of redistribution layer delamination caused by moisture absorption, significantly improving product reliability. In terms of process flow, the overall design of "constructing a multi-layer redistribution structure → forming microbumps → chip mounting → molding → debonding → forming external terminals" combined with single-stage panel-level molding, along with a pre-fabricated redistribution layer structure, eliminates multiple processes such as board transfer, secondary molding, and grinding in traditional six-sided packaging. This significantly simplifies the process, reduces costs, and systematically provides a highly reliable, highly manufacturable, and more commercially competitive technical implementation path for panel-level fan-out packaging.

[0057] Example 1

[0058] See Figure 1 -Figure 3 ( Figures 3-1 to 3-8 As shown in the figure, this application provides a method for fabricating a fan-out packaging structure, including the following steps:

[0059] S1. Provide a substrate 1, and form a release layer 2 on the substrate 1;

[0060] A temporary substrate 1 (such as glass, silicon, or a metal plate) is provided, and a release layer 2 is formed on the substrate 1. The release layer 2 may be a laser debonding layer, a thermally conductive layer, or a UV-degradable adhesive layer, so as to facilitate the separation of the entire package structure from the substrate 1 after subsequent processes.

[0061] S2. At least three patterned insulating layers 5 and a rewiring layer disposed therebetween are sequentially constructed on the release layer 2 to form a multi-layer rewiring structure 3;

[0062] The first insulating layer 51 in contact with the release layer 2 is made of a non-photosensitive dielectric material, and at least one non-bottom insulating layer 5 is made of a photosensitive polyimide material.

[0063] As an example and not a limitation, Ajinomoto additive materials can be used for non-photosensitive dielectric materials.

[0064] On the release layer 2, at least three patterned insulating layers 5 and a rewiring layer disposed therebetween are sequentially constructed to form a multi-layer rewiring structure 3.

[0065] Specifically, the first insulating layer 51 (bottom layer) is made of a non-photosensitive dielectric material, such as Ajinomoto Build-up Film (ABF). This layer is in direct contact with the release layer 2 and is required to have excellent adhesion, insulation, and low water vapor permeability.

[0066] Upper insulating layer (at least one layer): made of photosensitive polyimide material. Utilizing its excellent photolithography properties, high-precision, small-aperture (e.g., ≤10μm) micropores are formed through exposure and development processes, thereby achieving high-density, fine-linewidth wiring.

[0067] While photosensitive polyimide (PSPI) is suitable for fabricating intricate circuits, its hygroscopic nature is the root cause of redistribution delamination during subsequent high-temperature or reliability testing. This embodiment addresses this by using a non-photosensitive dielectric material (especially ABF) with excellent insulation, oxygen-free, and moisture-free properties as the bottom layer. This effectively provides "comprehensive coverage" and "isolation protection" to all upper photosensitive polyimide layers from the bottom of the structure, isolating them from the atmospheric environment and fundamentally blocking the path of moisture intrusion. This completely avoids redistribution delamination caused by PSPI moisture absorption, significantly improving the long-term reliability of the product.

[0068] S3. Microbumps 6 are formed on the top layer of the multilayer rewiring structure 3;

[0069] On the top layer of the completed multilayer rewiring structure 3, microbumps 6 are formed by electroplating, balling, or printing to serve as electrical interfaces for connection with chip 7.

[0070] S4. At least one chip 7 is mounted onto the multilayer redistribution structure 3 via a non-conductive thin film, and the pads of the chip 7 are electrically connected to the microbumps 6;

[0071] At least one chip 7 is mounted onto the multilayer redistribution structure 3 using a non-conductive thin film. Through processes such as thermosetting bonding, the pads on the chip 7 are electrically connected and mechanically fixed to the microbumps 6 on the redistribution structure.

[0072] S5. The chip 7 and the microbumps 6 around the chip 7 are encapsulated using a panel-level molding process;

[0073] A panel-level molding process is employed, using encapsulating materials such as epoxy molding compound 8 to encapsulate the mounted chip 7 and its surrounding micro-bumps 6 and circuit structure in a single process. This step provides mechanical and environmental protection for the chip 7 and the delicate redistribution structure.

[0074] Compared to traditional six-sided protective fan-out packaging solutions that require two molding processes and two temporary bonding / debonding processes, this embodiment achieves effective protection with only a single panel-level molding process, eliminating multiple complex steps such as board transfer, secondary molding, grinding, and board removal. This greatly simplifies the production process, shortens the cycle time, and significantly reduces manufacturing costs.

[0075] S6. Debond and clean the substrate 1 to expose the bottommost redistribution layer of the multilayer redistribution structure 3;

[0076] The temporary substrate 1 is debonded (e.g., by laser ablation, heating or ultraviolet irradiation), and removed and cleaned together with the release layer 2, thereby exposing the bottommost rewiring layer of the multilayer rewiring structure 3.

[0077] S7. Solder printing is performed on the exposed redistribution layer to form external connection terminals 9.

[0078] Solder printing and reflow soldering are performed on the exposed bottommost redistribution layer to form external connection terminals 9 such as solder ball arrays or solder pillars, which are used to connect the packaged chip 7 to an external circuit board (such as a PCB).

[0079] In a preferred embodiment, the aperture diameter is ≤10μm, the line width / spacing is ≤5μm, the copper plating thickness is 2μm-8μm, the bump height ranges from 10μm to 30μm, and the diameter ranges from 30μm to 80μm. These process parameters, used in large-area panel processing, strictly control critical dimensions such as open / short circuits, insufficient via filling, and alignment accuracy. Uniform plating thickness and bump size are fundamental to ensuring the consistency and reliability of all I / O point connections, directly reducing interconnection defects caused by process fluctuations.

[0080] In this embodiment, the fabrication method of the fan-out packaging structure adopts a material architecture in which the first insulating layer in contact with the release layer is made of a non-photosensitive dielectric material, and at least one non-bottom insulating layer is made of photosensitive polyimide material (PSPI). The hygroscopic photosensitive polyimide is used on the upper layer to form high-density fine lines, while the non-photosensitive material with insulating, oxygen-proof, water-proof and vapor-proof properties is used as the bottom layer to achieve complete coverage of the photosensitive polyimide and atmospheric isolation. This fundamentally solves the problem of redistribution layer (RDL) delamination caused by moisture absorption, and significantly improves product reliability. In terms of process flow, through the overall design of "constructing a multi-layer redistribution structure → forming microbumps → chip mounting → molding → debonding → forming external terminals" and single panel-level molding, combined with the pre-fabricated redistribution layer structure, the method of first-wired packaging eliminates multiple processes such as board transfer, secondary molding and grinding in traditional six-sided packaging, greatly simplifying the process and reducing costs. It systematically provides a highly reliable, highly manufacturable and more commercially competitive technical implementation path for panel-level fan-out packaging.

[0081] Example 2

[0082] This embodiment provides a method for fabricating a fan-out package structure. This method effectively solves the delamination problem caused by the easy moisture absorption of PSPI materials in traditional processes by optimizing the combination of non-photosensitive dielectric materials and the package structure, while also simplifying the process flow. See also... Figure 2-1 As for Figure 2-8 As shown, the method specifically includes the following steps:

[0083] S1. Provide a substrate 1, and form a release layer 2 on the substrate 1 (see...) Figure 2-1 );

[0084] In this embodiment, a temporary substrate 1 (such as glass or silicon wafer) is provided, and a laser debonding release layer 2 is formed on the substrate 1 by spin coating process.

[0085] S2. At least three patterned insulating layers 5 and a rewiring layer disposed therebetween are sequentially constructed on the release layer 2 to form a multi-layer rewiring structure 3;

[0086] The first insulating layer 51 in contact with the release layer 2 is made of a non-photosensitive dielectric material, and at least one non-bottom insulating layer 5 is made of a photosensitive polyimide material.

[0087] In this embodiment, a patterned insulating layer 5 and a rewiring layer are sequentially constructed on the release layer 2 to form a multilayer rewiring structure 3. It should be noted that the bottom and top insulating layers 5 in contact with the release layer 2 are made of non-photosensitive Ajinomoto additive material, while the middle layer is made of photosensitive polyimide material to achieve full coverage of PSPI by ABF.

[0088] In step S2, the formation of each of the redistribution layers may include: depositing a seed layer on the corresponding insulating layer 5 by sputtering or chemical plating, and forming a target metal wiring pattern by photolithography, electroplating and etching processes, wherein the thickness of the electroplated copper is between 2μm and 8μm, and the line width / line spacing is less than or equal to 5μm.

[0089] Specifically, step S2 may include the following steps:

[0090] S211. A first redistribution layer 31 is formed on the first insulating layer 51, wherein the first insulating layer 51 is made of a layering film material (see...). Figure 2-2 );

[0091] Furthermore, a first insulating layer 51 is formed on the release layer 2 by a lamination process. This layer uses a layering film material. The thickness of the first insulating layer 51 can be between 15 μm and 50 μm, and is preferably 25 μm in this example.

[0092] In this embodiment, the step of creating a passivation opening 4 in the insulating layer 5 made of photosensitive polyimide material includes: processing by exposure and development photolithography, and the resulting opening aperture is less than or equal to 10 μm.

[0093] In practical applications, passivation openings 4 can be created in the first insulating layer 51 using laser ablation. The first redistribution layer 31 is formed using a semi-additive process: first, a seed layer is sputtered, then copper is electroplated to fill the openings 4 and form circuits, and finally, the pattern is etched to complete the patterning, so that the first redistribution layer 31 is electrically connected to the release layer 2 through the openings 4.

[0094] In actual manufacturing, the above step S211 process can be repeated multiple times to construct a first interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0095] It should be noted that the layering film material in this embodiment can be Ajinomoto layering material (ABF).

[0096] S212. A second insulating layer 52 is formed on the first redistribution layer 31, the second insulating layer 52 being made of a photosensitive polyimide material (see...). Figure 2-3 );

[0097] Furthermore, a second insulating layer 52 is formed on the first redistribution layer 31 by spin coating. This layer is made of photosensitive polyimide material (PSPI). A second passivation opening 4 is formed in the second insulating layer 52 by photolithography of exposure and development. The aperture of the opening 4 is ≤10μm.

[0098] The thickness of the first insulating layer 51 is between 15μm and 50μm, and can be a specific value such as 15μm, 25μm, 30μm, 35μm or 50μm.

[0099] S213. A second redistribution layer 32 is formed on the second insulating layer 52 (see...) Figure 2-3 );

[0100] The second redistribution layer 32 is also formed using a semi-additive process, which fills the second passivation opening 4 and electrically connects it to the first redistribution layer 31.

[0101] In this embodiment, the thickness of the second insulating layer 52 is between 3 μm and 20 μm. It can be a specific value such as 3 μm, 10 μm, 15 μm, or 20 μm. The thickness of the first insulating layer 51 located below the second insulating layer 52 is 25 μm.

[0102] In actual process, steps S212 and S213 can be repeated multiple times to construct a second interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0103] S214. A third insulating layer 53 is formed on the second redistribution layer 32, the third insulating layer 53 being a layering film material, and the third insulating layer 53 and the first insulating layer 51 covering the second insulating layer 52 (see...). Figure 2-4 ).

[0104] A third insulating layer 53, which uses Ajinomoto additive material (ABF), is formed on the second redistribution layer 32 by a lamination process. A third passivation opening 4 is formed in the third insulating layer 53 by a laser ablation process.

[0105] In actual process, step S214 can be repeated multiple times to construct a third interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0106] In this embodiment, during the process of forming passivation openings 4 in the second insulating layer 52 and the third insulating layer 53, the process is carried out by photolithography process of exposure and development, wherein the aperture of the second passivation opening 4 and the third passivation opening 4 formed is less than or equal to 10 μm.

[0107] In this embodiment, the third insulating layer 53 and the first insulating layer 51 completely cover the second insulating layer 52 of PSPI material from both the top and bottom, isolating it from the atmospheric environment. To ensure the covering effect and structural stability, the distance by which the periphery of the first insulating layer 51 extends beyond the periphery of the second insulating layer 52 must be greater than the thickness of the second insulating layer 52.

[0108] The difference between the periphery of the first insulating layer 51 and the periphery of the second insulating layer 52 must be greater than the thickness of the second insulating layer 52 in order to maintain the stability and reliability of the second insulating layer 52 PSPI, so that the packaging substrate has enough space in the horizontal direction to accommodate more wiring structures, thereby improving wiring density and wiring flexibility.

[0109] In step S2, the second insulating layer 52 is sandwiched between two layers of low-hygroscopic, highly dense reinforcing film material (the first and third insulating layers) by covering the second insulating layer 52 with the third insulating layer 53 and the first insulating layer 51. This fundamentally cuts off the contact path between the photosensitive polyimide and the external humid environment, preventing it from absorbing moisture before subsequent high-temperature processes (such as molding and reflow soldering). This greatly reduces the risk of redistribution layer delamination due to moisture evaporation, improving the long-term reliability of the product.

[0110] S3. Microbumps 6 are formed on the top layer of the multilayer rewiring structure 3 (see reference). Figure 2-5 );

[0111] On the topmost layer of the multilayer redistribution structure 3 (i.e., on the third insulating layer 53), microbumps 6 are formed by electroplating to serve as interfaces for connecting the chip 7.

[0112] Further, step S3 may include:

[0113] A passivation opening 4 is made on the uppermost insulating layer 5 of the multilayer rewiring structure 3. Copper pillars or tin-silver solder balls are formed in the opening using electroplating or ball-planting processes. The height of the bumps ranges from 10μm to 30μm, and the diameter ranges from 30μm to 80μm.

[0114] S4. At least one chip 7 is mounted onto the multilayer redistribution structure 3 via a non-conductive thin film, and the pads of the chip 7 are electrically connected to the microbumps 6 (see...). Figure 2-6 );

[0115] S5. The chip 7 and the microbumps 6 around the chip 7 are encapsulated using a panel-level molding process (see [reference]). Figure 2-6 );

[0116] The chip 7, the micro-bumps 6 around the chip 7, the circuit structure periphery, and the upper surface of the third insulating layer 53 are encapsulated in one step using a panel-level molding process with epoxy molding compound 8.

[0117] In this embodiment, the panel-level molding process includes: using transfer molding, injecting epoxy molding compound into the cavity at a temperature of 150℃-180℃ and a pressure of 8MPa-15MPa, controlling the molding thickness to be 1.2-1.5 times the thickness of chip 7, and then post-curing at 175℃-185℃ for 1-3 hours. These parameters ensure full filling without pores, and the uniform molding thickness effectively controls warpage after encapsulation and reduces stress. Post-curing ensures sufficient EMC cross-linking, improving its mechanical and moisture-proof properties.

[0118] In this embodiment, the panel-level molding process not only encapsulates the chip 7 but also the surface of the insulating layer made of photosensitive polyimide (such as the upper surface of the third insulating layer, or the periphery of the second and third insulating layers). For the photosensitive polyimide layer that is not completely encapsulated by the lower insulating layer, the epoxy molding compound formed by panel-level molding becomes its final protective layer. Epoxy molding compound (EMC) itself has excellent moisture-proof properties and can permanently seal the polyimide material underneath, preventing the intrusion of moisture in subsequent processes and the usage environment.

[0119] S6. The substrate 1 is debonded and cleaned to expose the bottommost redistribution layer of the multilayer redistribution structure 3 (see...). Figures 2-6 to 2-7 );

[0120] The temporary substrate 1 is laser debonded, the substrate 1 and the release layer 2 are removed, and the surface is cleaned to expose the first redistribution layer 31 of the bottom layer of the multilayer redistribution structure 3.

[0121] In this embodiment, the debonding of the substrate 1 may include: separating the release layer 2 from the substrate 1 by laser stripping or thermal conduction. The laser wavelength is 248nm-355nm and the energy density is 100mJ / cm²-300mJ / cm². This combination of parameters can ensure that the release layer is efficiently and thoroughly decomposed, while avoiding damage to the delicate redistribution structure below by the laser energy.

[0122] After debonding, an oxygen plasma cleaning process is used to thoroughly remove organic contaminants remaining on the surface of the redistribution layer. This cleaning step is crucial, as it ensures a high degree of cleanliness on the surface of the bottom redistribution layer pads, laying the foundation for the subsequent formation of external connection terminals and effectively avoiding connection reliability defects such as "cold solder joints" or "ball drop" caused by pad contamination.

[0123] S7. Solder printing is performed on the exposed redistribution layer to form external connection terminals 9 (see...). Figure 2-8 ).

[0124] Solder printing and reflow are performed on the exposed first redistribution layer 31 to form external connection terminals 9 such as solder ball arrays.

[0125] In this embodiment, by utilizing the excellent barrier properties of ABF material, a sandwich-like encapsulation is formed on the top and bottom of the moisture-absorbing PSPI layer, isolating it from the atmosphere and fundamentally avoiding the delamination problem of the redistribution layer caused by PSPI moisture absorption. The photolithographic precision advantage of PSPI material is fully utilized to fabricate microvias with apertures ≤10μm, meeting the requirements of high-density, fine-linewidth wiring. Simultaneously, the laser processing characteristics of ABF can be used to form larger interconnect vias, achieving a collaborative design of fine lines and robust external interconnects. The entire process eliminates the multiple steps required by traditional six-sided packaging, such as board transfer, secondary molding, grinding, and board removal. Through single-panel-level molding and an optimized material system, the process is significantly simplified, manufacturing costs are reduced, and a high-performance, high-reliability, and more commercially competitive technical path is provided for panel-level fan-out packaging.

[0126] Example 3

[0127] This embodiment provides a method for fabricating a fan-out packaging structure. The core of this method lies in constructing a stepped insulating layer 5 structure and optimizing the combination and spatial arrangement of non-photosensitive and photosensitive dielectric materials. This achieves high-density interconnection while maintaining the reliability of the packaging structure and simplifying the manufacturing process. (See also...) Figures 3-1 to 3-8 As shown, the method specifically includes the following steps:

[0128] S1. Provide a substrate 1, and form a release layer 2 on the substrate 1 (see...) Figure 3-1 );

[0129] This embodiment provides a temporary substrate 1 (such as a glass substrate), and a laser debonding release layer 2 is formed on the substrate 1 by spin coating process.

[0130] S2. At least three patterned insulating layers 5 and a rewiring layer disposed therebetween are sequentially constructed on the release layer 2 to form a multi-layer rewiring structure 3;

[0131] The first insulating layer 51 in contact with the release layer 2 is made of a non-photosensitive dielectric material, and at least one non-bottom insulating layer 5 is made of a photosensitive polyimide material.

[0132] In this embodiment, a patterned insulating layer 5 and a rewiring layer are sequentially constructed on the release layer 2 to form a multilayer rewiring structure 3 with a stepped profile. Its key feature is that the bottom layer uses a large-area non-photosensitive dielectric material to provide support and protection, while the upper layer uses a smaller-area photosensitive dielectric material to achieve high-density wiring.

[0133] In step S2, the formation of each of the redistribution layers may include: depositing a seed layer on the corresponding insulating layer 5 by sputtering or chemical plating, and forming a target metal wiring pattern by photolithography, electroplating and etching processes, wherein the thickness of the electroplated copper is between 2μm and 8μm, and the line width / line spacing is less than or equal to 5μm.

[0134] Specifically, step S2 may include the following steps:

[0135] S221. A first redistribution layer 31 is formed on the first insulating layer 51 (see...) Figure 3-2 );

[0136] A first insulating layer 51 is formed on the release layer 2 by a lamination process. This layer uses a layering film material. Its thickness is between 15 μm and 50 μm (e.g., 20 μm, 30 μm or 45 μm).

[0137] In this embodiment, the step of creating a passivation opening 4 in the insulating layer 5 made of photosensitive polyimide material includes: processing by exposure and development photolithography, and the resulting opening aperture is less than or equal to 10 μm.

[0138] In practical applications, a passivation opening 4 can be created in the first insulating layer 51 using a laser ablation process. The aperture of this opening 4 is designed to be relatively large to accommodate a robust connection with external terminals. The first redistribution layer 31 is formed using a semi-additive process: a seed layer is first sputtered, then conductive copper pillars 10 are formed by electroplating to fill the opening 4, and finally, patterning is completed by etching, so that the first redistribution layer 31 is electrically connected to the release layer 2.

[0139] In actual manufacturing, step S221 can be repeated multiple times to construct a first interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0140] In this embodiment, the thickness of the first insulating layer 51 is between 15 μm and 50 μm. For example, the thickness of the first insulating layer 51 can be 20 μm, 30 μm, or 45 μm, etc.

[0141] It should be noted that the layering film material in this embodiment can be Ajinomoto layering material (ABF).

[0142] S222. A second insulating layer 52 is formed on the first redistribution layer 31. The second insulating layer 52 is made of photosensitive polyimide material, and the area of ​​the second insulating layer 52 is smaller than the area of ​​the first insulating layer 51, such that the second insulating layer 52 is confined to the central region of the surface of the first insulating layer 51 (see...). Figure 3-2 );

[0143] The area of ​​the second insulating layer 52 is smaller than the area of ​​the first insulating layer 51 below it. This confines the second insulating layer 52 to the central region of the surface of the first insulating layer 51, thereby forming an edge region surrounding the second insulating layer 52 on the first insulating layer 51. A second passivation opening 4 is formed in the second insulating layer 52 by photolithography processes of exposure and development. The aperture of the formed opening 4 is less than or equal to 10 μm to meet the precision requirements of high-density interconnects.

[0144] S223. A second redistribution layer 32 is formed on the second insulating layer 52 (see...) Figure 3-3 );

[0145] In actual manufacturing, the above process can be repeated multiple times to construct a second interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0146] A second redistribution layer 32 is formed using a semi-additive process, which fills the second passivation opening 4 and is electrically connected to the first redistribution layer 31.

[0147] S224. A third insulating layer 53 is formed on the second redistribution layer 32, the third insulating layer 53 being made of a photosensitive polyimide material (see [reference]). Figure 3-4 ).

[0148] A third insulating layer 53 is formed on the second redistribution layer 32 by spin coating. This layer is made of photosensitive polyimide material (PSPI). A third passivation opening 4 is formed in the third insulating layer 53 by photolithography of exposure and development. The aperture of the opening 4 is ≤10μm.

[0149] In actual process, step S224 can be repeated multiple times to construct a third interconnect structure consisting of alternating layers of insulating layers 5 and rewiring layers.

[0150] In step S2 of this embodiment, an insulating layer structure with decreasing area is constructed (the area of ​​the second insulating layer 52 < the area of ​​the first insulating layer 51). This allows the epoxy molding compound to flow down from the top and fill the periphery and upper surface of the bottom insulating layer during molding. This cleverly utilizes a single panel-level molding process to simultaneously protect the top of the chip and the sidewalls and part of the lower surface of the redistribution structure. It eliminates the complex processes of back-side molding, transfer, and grinding found in traditional six-sided packaging, directly reducing production steps and costs. Furthermore, by reducing the number of board processing steps, it lowers the risk of defects such as warpage, mechanical damage, and misalignment.

[0151] S3. Microbumps 6 are formed on the top layer of the multilayer rewiring structure 3 (see reference). Figure 3-5 );

[0152] Specifically, microbumps 6 are formed on the topmost layer (i.e., the third insulating layer 53) of the multilayer rewiring structure 3 by electroplating.

[0153] Further, step S3 may include:

[0154] A passivation opening 4 is made on the uppermost insulating layer 5 of the multilayer rewiring structure 3. Copper pillars or tin-silver solder balls are formed in the opening using electroplating or ball-planting processes. The height of the bumps ranges from 10μm to 30μm, and the diameter ranges from 30μm to 80μm.

[0155] S4. At least one chip 7 is mounted onto the multilayer redistribution structure 3 via a non-conductive thin film, and the pads of the chip 7 are electrically connected to the microbumps 6 (see...). Figure 3-6 );

[0156] S5. The chip 7 and the microbumps 6 around the chip 7 are encapsulated using a panel-level molding process (see [reference]). Figure 3-6 );

[0157] Specifically, a panel-level molding process is adopted, using epoxy molding compound 8 to encapsulate the chip 7, the micro-bumps 6 around the chip 7, the circuit structure, the third insulating layer 53, the second insulating layer 52, and the upper surface of the first insulating layer 51.

[0158] The epoxy molding compound 8 has a thickness greater than 25 μm (e.g., 30 μm, 40 μm, or 50 μm). To ensure that the epoxy molding compound 8 can be fully filled and firmly bonded, the distance difference (i.e., step width) between the periphery of the first insulating layer 51 and the periphery of the second insulating layer 52 needs to be greater than 25 μm. This design effectively enhances the mechanical integrity of the package.

[0159] In this embodiment, the panel-level molding process includes: using transfer molding, injecting epoxy molding compound into the cavity at a temperature of 150℃-180℃ and a pressure of 8MPa-15MPa, controlling the molding thickness to be 1.2-1.5 times the thickness of chip 7, and then post-curing at 175℃-185℃ for 1-3 hours. These parameters ensure full filling without pores, and the uniform molding thickness effectively controls warpage after encapsulation and reduces stress. Post-curing ensures sufficient EMC cross-linking, improving its mechanical and moisture-proof properties.

[0160] In this embodiment, the panel-level molding process not only encapsulates the chip 7 but also the surface of the insulating layer made of photosensitive polyimide (such as the upper surface of the third insulating layer, or the periphery of the second and third insulating layers). For the photosensitive polyimide layer that is not completely encapsulated by the lower insulating layer, the epoxy molding compound formed by panel-level molding becomes its final protective layer. Epoxy molding compound (EMC) itself has excellent moisture-proof properties and can permanently seal the polyimide material underneath, preventing the intrusion of moisture in subsequent processes and the usage environment.

[0161] S6. The substrate 1 is debonded and cleaned to expose the bottommost redistribution layer of the multilayer redistribution structure 3 (see...). Figures 3-6 to 3-7 );

[0162] The temporary substrate 1 is laser debonded, the substrate 1 and the release layer 2 are removed, and the surface is cleaned to expose the first redistribution layer 31 of the bottom layer of the multilayer redistribution structure 3.

[0163] In this embodiment, the debonding of the substrate 1 may include: separating the release layer 2 from the substrate 1 by laser stripping or thermal conduction. The laser wavelength is 248nm-355nm and the energy density is 100mJ / cm²-300mJ / cm². This combination of parameters can ensure that the release layer is efficiently and thoroughly decomposed, while avoiding damage to the delicate redistribution structure below by the laser energy.

[0164] After debonding, an oxygen plasma cleaning process is used to thoroughly remove organic contaminants remaining on the surface of the redistribution layer. This cleaning step is crucial, as it ensures a high degree of cleanliness on the surface of the bottom redistribution layer pads, laying the foundation for the subsequent formation of external connection terminals and effectively avoiding connection reliability defects such as "cold solder joints" or "ball drop" caused by pad contamination.

[0165] S7. Solder printing is performed on the exposed redistribution layer to form external connection terminals 9 (see...). Figure 3-8 ).

[0166] Solder printing and reflow are performed on the exposed first redistribution layer 31 to form external connection terminals 9 such as solder ball arrays.

[0167] In this embodiment, the upper insulating layer 5 is constructed using PSPI continuously, fully leveraging its excellent photolithography precision to easily achieve microvias ≤10μm, meeting the requirements of high-density wiring. The bottom layer uses ABF material, utilizing its excellent mechanical strength, insulation, and protection capabilities for the underlying structure. The stepped structure design provides ample anchoring space for the epoxy molding compound 8, ensuring a tight bond between the encapsulation and the rewiring structure, effectively preventing delamination risks. Simultaneously, the large-area design of the bottom ABF provides a stable mechanical foundation for the entire packaging structure. The entire process eliminates the need for complex flipping operations; effective protection of the chip 7 and the stepped wiring structure can be achieved through a single panel-level molding process, significantly simplifying production steps, reducing manufacturing costs, and providing a highly commercially competitive technical path for achieving high-performance, high-reliability panel-level fan-out packaging.

[0168] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a fan-out type packaging structure, characterized in that, include: A substrate is provided, and a release layer is formed on the substrate; At least three patterned insulating layers and a redistribution layer disposed therebetween are sequentially constructed on the release layer to form a multilayer redistribution structure; wherein, the first insulating layer in contact with the release layer is made of a non-photosensitive dielectric material, and at least one insulating layer other than the bottom layer is made of a photosensitive polyimide material; the construction of the multilayer redistribution structure includes: forming a first redistribution layer on the first insulating layer, the first insulating layer being made of a layering film material; forming a second insulating layer on the first redistribution layer, the second insulating layer being made of a photosensitive polyimide material, and the area of ​​the second insulating layer being smaller than the area of ​​the first insulating layer, such that the second insulating layer is confined to the central region of the surface of the first insulating layer; forming a second redistribution layer on the second insulating layer; and forming a third insulating layer on the second redistribution layer, the third insulating layer being made of a photosensitive polyimide material; Microbumps are formed on the top layer of the multi-layer rewiring structure; At least one chip is mounted onto the multilayer redistribution structure via a non-conductive thin film, and the pads of the chip are electrically connected to the microbumps. The chip and the microbumps around the chip are encapsulated using a panel-level molding process; wherein, the panel-level molding process uses epoxy molding compound to encapsulate the chip, the microbumps around the chip, the periphery of the third insulating layer, the periphery of the second insulating layer, and the upper surface of the first insulating layer not covered by the second insulating layer, the thickness of the epoxy molding compound is greater than 25 μm, and the step width formed between the periphery of the first insulating layer and the periphery of the second insulating layer is greater than 25 μm; The substrate is debonded, merged, and cleaned to expose the bottommost redistribution layer of the multilayer redistribution structure. Solder is printed on the exposed redistribution layer to form external connection terminals.

2. The method of claim 1, wherein the fan-out package structure is prepared by the steps of: The steps for creating passivation openings in an insulating layer using photosensitive polyimide material include: processing the openings through a photolithography process of exposure and development, resulting in an opening diameter of less than or equal to 10 μm. ​ 3. The method of claim 1, wherein the fan-out package structure is prepared by the steps of: In a multi-layer rewiring structure, at least three patterned insulating layers and rewiring layers disposed therebetween are sequentially constructed on the release layer. The formation of each rewiring layer includes: ​ A seed layer is deposited on the corresponding insulating layer by sputtering or chemical plating, and the target metal wiring pattern is formed by photolithography, electroplating and etching processes. The thickness of the electroplated copper ranges from 2μm to 8μm, and the line width / line spacing is less than or equal to 5μm.

4. The method of claim 1, wherein the fan-out package structure is prepared by the steps of: The process of forming microbumps on the top layer of the multi-layer rewiring structure includes: ​ A passivation opening is made on the uppermost insulating layer of the multilayer rewiring structure, and copper pillars or tin-silver solder balls are formed in the opening using electroplating or ball-planting processes. The height of the bumps ranges from 10μm to 30μm, and the diameter ranges from 30μm to 80μm.

5. The method for preparing the fan-out packaging structure according to claim 1, characterized in that, The panel-level molding process includes: The epoxy molding compound is injected into the cavity at a temperature of 150℃-180℃ and a pressure of 8MPa-15MPa using the transfer molding method. The molding thickness is controlled to be 1.2-1.5 times the chip thickness. After molding, the compound is cured at 175℃-185℃ for 1-3 hours.

6. The method of claim 1, wherein the fan-out package structure is prepared by the steps of: The unbonding of the substrate includes: ​ The release layer is separated from the substrate by laser ablation or thermal conduction. The laser wavelength is 248 nm - 355 nm and the energy density is 100 mJ / cm² - 300 mJ / cm². After debonding, residual organic matter is cleaned by oxygen plasma.

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