A real-time signal processing system integrating reconnaissance, investigation, and communication on a high-speed motion platform

Abstract

This invention provides an integrated real-time signal processing system for reconnaissance, interception, and communication on a high-speed motion platform, comprising four functional boards, one high- and low-speed interconnect backplane, and one power supply backplane. The functional boards employ a combination of rigid and flexible PCB design methods, using a "cage-style" stacking approach to maximize space utilization, miniaturize the system, and facilitate rapid insertion and expansion. The system utilizes a combined design technology of multi-channel, high-bandwidth acquisition chips and high-speed, multi-logic-gate chips to improve data acquisition rates and the types of analog signal transmissions. The combined processing of high-performance digital signal processing (DSP) chips and large-scale gate array (FPGA) chips enhances real-time signal processing capabilities, meets the requirements for simultaneous processing in multiple operating modes, and performs fusion and decision-making on the processing results. The use of SEAF series and S2M series micro-miniature connectors, along with a partitioned design for the high- and low-speed interconnect and power supply backplane, effectively reduces size and improves system stability.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, specifically to an integrated real-time signal processing system for reconnaissance and communication on a high-speed motion platform. Background Technology

[0002] Traditional processing systems have a single working mode and separate design for each mode, resulting in high resource consumption, large size, low data processing capability, and poor information fusion, which cannot meet the current signal processing requirements.

[0003] Therefore, a miniaturized, high-power-density, multifunctional, high-bandwidth, multi-channel, and reconfigurable processing system is needed. Summary of the Invention

[0004] This invention aims to address the problems of traditional radar systems, such as limited operating modes, high resource consumption, large size and space requirements, low data processing capabilities, and poor information fusion. It provides an integrated real-time signal processing system for high-speed mobile platforms, enabling multi-channel, high-bandwidth acquisition and processing, multi-path analog signal transmission, multi-mode large-volume data signal processing, multi-mode information fusion, and multi-interface data transmission at different rates. This reduces size and weight, improves the digital signal processing capabilities of the radar system, and adapts to a wider range of application needs.

[0005] This invention provides an integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform, comprising four functional boards, one high- and low-speed interconnection backplane, and one power supply backplane. The four functional boards are stacked on top of each other: main control and interface adapter card, detection acquisition and preprocessing card, detection signal processing card, and reconnaissance and interference signal acquisition and processing card. The main control and interface adapter card, detection acquisition preprocessing card, detection signal processing card, and reconnaissance interference signal acquisition and processing card all adopt a rigid-flexible design method. Each functional board consists of a main functional module, a high-speed and low-speed data module, and a power supply module, and all of them are rigid boards. The main functional module is connected to the high-speed and low-speed data module through a flexible board, and the main functional module is connected to the power supply module through a flexible board. All high-speed and low-speed data modules are connected to the same high-speed and low-speed interconnect backplane slot, and all power supply modules are connected to the same power supply backplane slot. The main control and interface adapter card generates system reset signals and global reset signals to reset the detection acquisition preprocessing card, detection signal processing card, and reconnaissance interference signal acquisition and processing card; the main control and interface adapter card configures system parameters and sends control commands, and receives the status, self-test results, and signal processing results of the detection acquisition preprocessing card, detection signal processing card, and reconnaissance interference signal acquisition and processing card; The detection and acquisition preprocessing card receives the intermediate frequency signal output from the frequency conversion subsystem, performs down-conversion and filtering, and outputs a digital baseband signal to the detection signal processing card; the detection and acquisition preprocessing card generates an intermediate frequency transmission signal; The detection signal processing card performs algorithmic processing on the digital baseband signal and outputs the processing results. The reconnaissance jamming signal acquisition and processing card acquires at least two broadband intermediate frequency signals, performs digital down-conversion, and then performs corresponding digital signal processing according to different working modes to generate intermediate frequency transmission signals. At the same time, it transmits the signals to the main control and interface adapter card, and then outputs them to the control system. The high- and low-speed interconnect backplane transmits high-speed and low-speed commands and parameters, and performs inter-board signal communication. Power is supplied by the power supply backplane.

[0006] The present invention discloses a real-time signal processing system integrating detection, interception, and communication on a high-speed motion platform. In a preferred embodiment, the main functional module of the main control and interface adapter card receives instructions and parameters from the external control system, performs system power consumption control, generates a system reset signal, transcribes external instructions and sends them to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card, sends detection echo data and reconnaissance echo data to the memory, receives and processes the output results of the detection signal processing card and the reconnaissance interference signal acquisition and processing card using reconnaissance algorithms, receives the results of detection, reconnaissance, and interference processing and sends them to the control system, transcribes external instructions according to the protocol and sends them to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card, and reports the status of the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card to the telemetry system. It has synchronous 422, asynchronous 422, and fiber optic communication interfaces.

[0007] The real-time signal processing system for integrated detection and communication on a high-speed motion platform described in this invention, as a preferred embodiment, includes a first FPGA chip, a first DSP chip, and a first CPLD chip as the main functional modules of the main control and interface adapter card. The first FPGA chip forms different interface drivers to complete the data transmission between the internal boards of the signal processing card assembly and the control system and internal boards. The first DSP chip parses instructions and converts the data sent by the control system into parameters required by each board. The first CPLD chip controls the power-on method of the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition processing card, as well as the data transmission between the boards; The main control and interface adapter card controls the power supply status of the first DSP chip and the first FPGA chip through the first CPLD chip. The first FPGA chip receives the instruction parameters issued by the control system and passes them to the first DSP chip. The first DSP chip parses and converts the instructions and passes the results to the first FPGA chip. The first FPGA chip sends the instruction parsing results to the corresponding board and receives the results and status information reported by other boards through the address lines and data lines of the first CPLD. The first FPGA chip outputs to the control system through the 422 interface chip to realize real-time reporting of results.

[0008] The real-time signal processing system for integrated detection and communication on a high-speed moving platform described in this invention, as a preferred embodiment, involves the main functional module of the detection acquisition preprocessing card acquiring eight intermediate frequency signals, performing digital down-conversion and filtering, and then outputting digital baseband signals to the detection signal processing card; the detection acquisition preprocessing card has the capability to configure a bus interface and can report the operating temperature in real time. The detection and acquisition preprocessing card generates two channels of analog intermediate frequency transmission signals; The detection acquisition preprocessing card can send and store the raw echoes to the main control and interface adapter card.

[0009] The real-time signal processing system for integrated detection and communication on a high-speed motion platform described in this invention, as a preferred embodiment, includes a main functional module of a detection acquisition preprocessing card comprising a first AD chip, a second FPGA chip, a first DA chip, and a second CPLD chip. The first AD chip converts the intermediate frequency signal into a digital intermediate frequency signal and outputs it to the second FPGA chip. The second FPGA chip performs digital down-conversion preprocessing on the digital intermediate frequency signal and generates a digital baseband signal, which is output to the detection signal processing card through the high-low speed interconnect backplane. The second FPGA chip generates a digital intermediate frequency signal according to the instruction parameter information issued by the main controller and interface adapter card, and sends it to the first DA chip to be converted into an analog intermediate frequency transmission signal; The second CPLD controls the power supply of the chip on the detection and acquisition preprocessing card and the data transmission between it and other boards.

[0010] The real-time signal processing system for integrated detection and communication under a high-speed motion platform described in this invention, as a preferred embodiment, includes a second DSP chip, a third DSP chip, a fourth DSP chip, a fifth DSP chip, and a third FPGA chip as the main functional modules of the detection signal processing card. The detection signal processing card has the ability to configure a bus interface and can report the operating temperature in real time. The detection signal processing card receives the digital baseband signal output by the detection acquisition preprocessing card, and performs real-time digital baseband signal processing through the second, third, fourth and fifth DSP chips to obtain the processing result. The processing result is then transmitted to the main control and interface adapter card through the third FPGA chip.

[0011] The present invention discloses an integrated real-time signal processing system for reconnaissance and communication on a high-speed moving platform. In a preferred embodiment, the main functional module of the reconnaissance and interference signal acquisition and processing card acquires 12 channels of broadband intermediate frequency signals, performs digital down-conversion, and performs corresponding digital signal processing according to different working modes. The reconnaissance and interference signal acquisition and processing card generates 2 channels of intermediate frequency transmission signals. The reconnaissance and interference signal acquisition and processing card has the ability to configure a bus interface and can report the working temperature in real time.

[0012] The real-time signal processing system for integrated reconnaissance and communication under a high-speed moving platform described in this invention, as a preferred embodiment, includes a second AD chip, a second DA chip, a fourth FPGA chip, and a fifth FPGA chip as the main functional module of the reconnaissance and interference signal acquisition and processing card. The second AD chip converts the acquired intermediate frequency signal into a digital intermediate frequency signal. The fourth FPGA chip converts the digital intermediate frequency signal into a digital baseband signal through digital down-conversion and performs signal processing to obtain the processing result. The fourth FPGA chip outputs the processing result to the fifth FPGA chip. The fifth FPGA chip transmits the processing result to the main controller and interface adapter card and then outputs it to the control system. The second DA chip upconverts the digital baseband signal into a digital intermediate frequency signal, generating two detection and transmission intermediate frequency signals.

[0013] In the high-speed motion platform integrated real-time signal processing system described in this invention, as a preferred embodiment, the high-speed and low-speed interconnection backplane completes the high-frequency and low-frequency signal transmission and communication between the internal boards of the signal processing system through connectors, and the power supply backplane is connected to each power supply module inside the signal processing card assembly through connectors for power supply. The main control and interface adapter card, the detection acquisition and preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card are stacked in sequence.

[0014] The real-time signal processing system for integrated detection, interception, and communication on a high-speed moving platform, as described in this invention, preferably includes the following steps in its signal processing method: S1. After power-on, the main control and interface adapter card receive the wake-up command issued by the system and send the wake-up command to the second CPLD chip of the detection acquisition preprocessing card, the third FPGA chip of the detection signal processing card, and the fifth FPGA chip of the reconnaissance interference signal acquisition and processing card through the configuration bus. At the same time, the main control and interface adapter card control the power supply backplane to power on the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card. After the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card report the self-test completion status, the main control and interface adapter card sends the work start command to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card, and the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card start working. When the frequency conversion subsystem sends an intermediate frequency signal to the main control and interface adapter card, it proceeds to step S2. When the detection acquisition and preprocessing card outputs an intermediate frequency signal, it proceeds to step S3. When the detection interference signal acquisition and processing card acquires the intermediate frequency signal and parses the prior information, it proceeds to step S4. When the detection interference signal acquisition and processing card parses the detailed waveform parameters and generates an intermediate frequency transmission signal, it proceeds to step S5. S2. The first AD chip of the detection and acquisition preprocessing card converts the intermediate frequency signal sent by the frequency conversion subsystem into a digital intermediate frequency signal and sends it to the second FPGA chip of the detection and acquisition preprocessing card. The second FPGA chip filters the digital intermediate frequency signal to obtain a digital baseband signal, and sends it to the second DSP, third DSP, fourth DSP, and fifth DSP of the detection signal processing card, as well as the first FPGA chip of the main control and interface adapter card, through the high-speed interconnect backplane according to the instruction parameter information sent by the main control and interface adapter card. The second, third, fourth, and fifth DSPs analyze, detect, and probe the digital baseband signal sent by the second FPGA chip, and then send it to the main control and interface adapter card through the third FPGA chip of the detection signal processing card. S3. The second FPGA chip of the detection and acquisition preprocessing card generates a digital intermediate frequency signal according to the instruction parameter information issued by the main control and interface adapter card and sends it to the first DA chip of the detection and acquisition preprocessing card. The first DA chip converts the digital intermediate frequency signal into an analog intermediate frequency signal and outputs it to the frequency conversion subsystem. S4. The second AD chip of the reconnaissance jamming signal acquisition and processing card converts the intermediate frequency signal into a digital intermediate frequency signal and sends it to the fourth FPGA chip of the reconnaissance jamming signal acquisition and processing card. The fourth FPGA chip converts the digital intermediate frequency signal into a baseband signal. After processing by the internal algorithm of the fourth FPGA chip, the waveform frequency, pulse width, and repetition frequency of the intermediate frequency signal are obtained and sent to the main control and interface adapter card, and further sent to the control system and the detection signal processing card as prior information for subsequent algorithms. S5. The second AD chip converts the intermediate frequency signal into a digital intermediate frequency signal and sends it to the fourth FPGA chip. The fourth FPGA chip performs waveform parameter analysis and obtains detailed waveform parameters by referring to the processing result of step S4. Based on the detailed waveform parameters, it forms a transmitted digital signal and sends it to the second DA chip of the reconnaissance and interference signal acquisition and processing card. The second DA chip upconverts the transmitted digital signal into a transmitted intermediate frequency signal.

[0015] This invention proposes an integrated real-time signal processing system for high-speed motion platforms, combining reconnaissance and communication. It employs a design method combining rigid and flexible PCBs, using a "cage-style" stacking approach to maximize space utilization, achieve miniaturization, and facilitate rapid insertion and expansion. The system utilizes a combined design technology of multi-channel, high-bandwidth acquisition chips and high-speed, multi-logic-gate chips to improve data acquisition rates and the variety of analog signal transmissions. The combined processing of high-performance digital signal processing (DSP) chips and large-scale gate array (FPGA) chips enhances real-time signal processing capabilities, meets the requirements for simultaneous processing in multiple operating modes, and performs fusion and decision-making on the processing results. The use of SEAF and S2M series micro-miniature connectors, along with high- and low-speed interconnection and power supply backplane partitioning, effectively reduces size and improves system stability. This product development is based on these principles.

[0016] This invention discloses an integrated real-time signal processing system for reconnaissance, interference, and communication on a high-speed motion platform. It is characterized by comprising: four functional boards, one high- and low-speed interconnection backplane, and one power supply backplane. The four functional boards are: one main control and interface adapter card, one detection acquisition and preprocessing card, one reconnaissance and interference card, and one processing and acquisition card. This invention employs a highly integrated large-scale array chip for control and preprocessing, and a dedicated processing chip for algorithm processing, enabling parallel acquisition and processing of multi-channel, high-volume signals. It utilizes a rigid-flexible combined with a "cage-type" structural design to maximize the number of components per unit area. The integrated reconnaissance, interference, and communication design allows for the simultaneous fusion and processing of signals acquired under reconnaissance, interference, and detection modes. This invention features a large number of transceiver channels, high power integration, strong real-time processing, lightweight design, and strong anti-interference capabilities. It also possesses the ability to coordinate and schedule hardware resources for reconnaissance, interference, and communication, and to fuse software resources.

[0017] The technical solution of this invention is: an integrated real-time signal processing system for reconnaissance, interference and communication under a high-speed motion platform, including high-speed signal transmission and power supply between the main control and interface adapter card, the detection acquisition and preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card.

[0018] Main control and interface adapter card: generates system reset signal to reset each board in the processing system, configures system parameters, sends control commands, receives the status of each board and self-test results, has the function of controlling the workflow and other subsystems, and has the function of transmitting processing results and working status to the control system.

[0019] Detection and Acquisition Preprocessing Card: Acquires 8 channels of intermediate frequency signals and performs preprocessing such as digital down-conversion and filtering; generates 2 channels of intermediate frequency transmission signals; has the ability to configure bus interfaces, receives system parameters, control commands, global reset signals, etc. from the main control and interface adapter cards, and operates under the control of the main control and interface adapter cards; sends results and operating status to the main control and interface adapter cards.

[0020] The detection signal processing card processes digital baseband signals of various modes using corresponding algorithms and outputs the processing results. It has the ability to configure the bus interface, receive system parameters, control commands, global reset signals, etc. from the main control and interface adapter cards, and works under the control of the main control and interface adapter cards. It also sends results and working status to the main control and interface adapter cards.

[0021] Reconnaissance and jamming signal acquisition and processing card: Acquires 12 channels of broadband intermediate frequency signals and performs digital down-conversion; performs corresponding digital signal processing according to different working modes; generates 2 channels of intermediate frequency transmission signals; has the ability to configure bus interface, receives system parameters, control commands, global reset signals, etc. from the main control and interface adapter card, and works under the control of the main control and interface adapter card; sends results and working status to the main control and interface adapter card.

[0022] High-speed and low-speed interconnection backplane: Transmits high-speed and low-speed commands, parameters and other data to realize signal communication between processing system boards.

[0023] Power supply backplane: Provides 12V DC power to supply power to various boards in the processing system.

[0024] The present invention has the following advantages: (1) The present invention realizes a design method that combines rigidity and flexibility, which effectively reduces the size of the processing system. The pluggable design facilitates expansion and upgrading. (2) The present invention employs a multi-channel, high-bandwidth acquisition and processing system to increase multi-domain and multi-dimensional detailed information of the scene or target; (3) The present invention uses multi-mode digital signal collaborative processing of detection, interference and exploration to realize efficient resource utilization, information fusion and collaborative work, thereby improving system performance. Attached Figure Description

[0025] Figure 1 A schematic diagram of the processing system components of a real-time signal processing system integrating reconnaissance and communication on a high-speed motion platform. Figure 2A block diagram of the main control and interface adapter card of a real-time signal processing system integrating reconnaissance and communication under a high-speed motion platform; Figure 3 A block diagram of the detection acquisition and preprocessing card of a real-time signal processing system integrating reconnaissance and communication under a high-speed motion platform; Figure 4 A block diagram of the detection signal processing card of a real-time integrated real-time signal processing system for reconnaissance and communication under a high-speed motion platform; Figure 5 A block diagram of a reconnaissance and interference signal acquisition and processing card for a real-time integrated real-time signal processing system for reconnaissance, interference and communication under a high-speed motion platform. Figure 6 An appearance diagram of the power supply rigid-flexible composite board for a real-time signal processing system integrating reconnaissance and communication under a high-speed motion platform. Figure 7 This is an appearance diagram of a rigid-flexible composite board for high- and low-speed signal interconnection in a real-time signal processing system integrating reconnaissance and communication on a high-speed motion platform. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0027] like Figure 1 As shown, a real-time signal processing system integrating reconnaissance, interference and communication under a high-speed motion platform includes a main control and interface adapter card, a detection acquisition and preprocessing card, a detection signal processing card, and a reconnaissance interference signal acquisition and processing card. High-speed signal transmission and power supply between the cards are achieved through miniaturized connectors.

[0028] Main control and interface adapter card: generates system reset signal to reset each board in the processing system, configures system parameters, sends control commands, receives the status of each board and self-test results, has the function of controlling the workflow and other subsystems, and has the function of transmitting processing results and working status to the control system.

[0029] Detection and Acquisition Preprocessing Card: Acquires 8 channels of intermediate frequency signals and performs preprocessing such as digital down-conversion and filtering; generates 2 channels of intermediate frequency transmission signals; has the ability to configure bus interfaces, receives system parameters, control commands, global reset signals, etc. from the main control and interface adapter cards, and operates under the control of the main control and interface adapter cards; sends results and operating status to the main control and interface adapter cards.

[0030] The detection signal processing card processes digital baseband signals of various modes using corresponding algorithms and outputs the processing results. It has the ability to configure the bus interface, receive system parameters, control commands, global reset signals, etc. from the main control and interface adapter cards, and works under the control of the main control and interface adapter cards. It also sends results and working status to the main control and interface adapter cards.

[0031] Reconnaissance and jamming signal acquisition and processing card: Acquires 12 channels of broadband intermediate frequency signals and performs digital down-conversion; performs corresponding digital signal processing according to different working modes; generates 2 channels of intermediate frequency transmission signals; has the ability to configure bus interface, receives system parameters, control commands, global reset signals, etc. from the main control and interface adapter card, and works under the control of the main control and interface adapter card; sends results and working status to the main control and interface adapter card.

[0032] High-speed and low-speed interconnection backplane: Transmits high-speed and low-speed commands, parameters and other data to realize signal communication between processing system boards.

[0033] Power supply backplane: Provides 12V DC power to supply power to various boards in the processing system.

[0034] The main control and interface adapter card consists of three rigid PCB boards connected by a flexible PCB. The first rigid PCB board is the main functional module, the second rigid PCB board is the high- and low-speed interconnect module, and the third rigid PCB board is the power supply module. The first rigid PCB board includes a first FPGA chip, a first DSP chip, and a first CPLD chip. The first FPGA chip is used to generate different interface drivers to complete data transmission between internal boards and the control system, as well as between internal boards. The first DSP chip is used to parse instructions, converting data issued by the control system into parameters required by each board. The first CPLD chip is used to control the power-on mode of the chips on the board and to transmit data with other boards.

[0035] The main control and interface adapter card controls the power supply status of the first DSP chip and the first FPGA chip through the first CPLD chip. The first FPGA chip receives the instruction parameters issued by the control system and passes them to the first DSP chip. The first DSP chip parses and converts the instructions and passes the results to the first FPGA chip. The first FPGA chip sends the instruction parsing results to the corresponding board through the address lines and data lines of the first CPLD, and also receives the results and status information reported by other boards. The first FPGA chip outputs to the control system through the 422 interface chip to realize real-time reporting of results. The detection and acquisition preprocessing card consists of three rigid PCB boards connected by a flexible PCB board. The fourth rigid PCB board is the main functional module, the fifth rigid PCB board is the high- and low-speed interconnect module, and the sixth rigid PCB board is the power supply module. The fourth rigid PCB board includes a first AD chip, a second FPGA chip, a first DA chip, and a second CPLD chip. The first AD chip converts the intermediate frequency signal into a digital intermediate frequency signal. The second FPGA chip performs digital down-conversion preprocessing on the digital intermediate frequency signal and generates a digital intermediate frequency transmission signal. The first DA chip converts the digital intermediate frequency signal into an analog intermediate frequency signal. The second CPLD is used to control the power supply of the chips on the board and to transmit data with other boards.

[0036] The detection and acquisition preprocessing card controls the power supply status of the first AD and second FPGA chips through the second CPLD chip. The first AD chip converts the analog intermediate frequency signal into a digital intermediate frequency signal. The second FPGA chip converts the digital intermediate frequency signal into a digital baseband signal through digital downconversion and then upconverts the digital baseband signal into a digital intermediate frequency signal.

[0037] The detection signal processing card consists of three rigid PCBs connected by a flexible PCB. The seventh rigid PCB is the main functional module, the eighth rigid PCB is the high- and low-speed interconnect module, and the ninth rigid PCB is the power supply module. The seventh rigid PCB includes a second DSP chip, a third DSP chip, a fourth DSP chip, a fifth DSP chip, and a third FPGA chip. The second to fifth DSP chips are used for real-time processing of digital baseband signals and implementation of algorithms for reconnaissance and detection. The third FPGA chip is used to receive instructions from the bus and control the power supply of the chips on the control board.

[0038] The detection signal processing card performs real-time digital baseband signal processing through the second to fourth DSP chips, and the processing results are transmitted to the interface adapter card through the third FPGA chip.

[0039] The reconnaissance and jamming signal acquisition and processing card consists of three rigid PCB boards connected by a flexible PCB. The tenth rigid PCB board is the main functional module, the eleventh rigid PCB board is the high- and low-speed interconnect module, and the twelfth rigid PCB board is the power supply module. The tenth rigid PCB board includes a second AD chip, a second DA chip, a fourth FPGA chip, and a fifth FPGA chip. The second AD chip converts the intermediate frequency (IF) signal to a digital IF signal, the second DA chip converts the digital IF signal to an analog IF signal, the fourth FPGA chip converts the digital IF signal to a digital baseband signal via digital down-conversion, and up-converts the digital baseband signal back to a digital IF signal, while also implementing signal processing algorithms. The fifth FPGA chip controls the power supply to the chips on the board and facilitates data transfer with other boards.

[0040] The reconnaissance jamming signal acquisition and processing card performs broadband signal acquisition through the second AD chip, converts the analog intermediate frequency (IF) to a digital IF, and outputs it to the fourth FPGA chip for digital down-conversion and digital signal processing. The fourth FPGA chip outputs the processing results to the fifth FPGA chip, which then transmits the results to the interface adapter card, ultimately outputting them to the control system. The second DA chip up-converts the digital baseband signal to a digital IF signal, generating two channels of detection and transmission IF signals.

[0041] The signal processing backplane consists of two parts: a high-speed and low-speed interconnect backplane and a power supply backplane. The high-speed and low-speed interconnect backplane uses high-density miniature connectors to complete the transmission and communication of high-frequency and low-frequency signals between the internal boards of the processing system. The power supply backplane connects to each board through connectors to provide power.

[0042] The first AD chip is a high-bandwidth, high-speed sampling chip with a sampling rate of no less than 3.2 Gsps and an A / D bit depth of 12 bits. The second AD chip is a high-speed sampling chip with a sampling rate of no less than 2.6 Gsps and an A / D bit depth of 14 bits. The first DA chip is a single-channel 14-bit chip, and the second DA chip is a single-channel 12-bit chip. The first FPGA chip is a K7 series chip, the second FPGA chip is a V7 system chip, the third FPGA chip is a V2 series chip, the fourth FPGA chip is a VU9P series chip, and the fifth FPGA chip is an A7 series chip. The first to fifth DSP chips are all from the 6678 series.

[0043] A real-time signal processing system integrating reconnaissance, detection, and communication on a high-speed moving platform has 16 channels for acquisition, 4 channels for transmission, a computing power of 640 GFLOPS, a total number of logic gates of over 100 million, a high-speed signal transmission rate of no less than 5Gbps, good stability, and easy expansion. It can simultaneously meet the requirements of detection signal processing, reconnaissance radar signal processing, and jamming signal processing.

[0044] The example is shown below: like Figure 1 The diagram shown is a block diagram of a real-time signal processing system integrating reconnaissance, detection, and communication on a high-speed motion platform according to this embodiment. Figure 1 The integrated reconnaissance and interference processing system consists of six parts: main control and interface adapter card, detection acquisition and preprocessing card, detection signal processing card, reconnaissance interference signal acquisition and processing card, high and low speed interconnection backplane, and power supply backplane.

[0045] The signal processing system's processing method includes the following steps: S1. After power-on, the main control and interface adapter card receive the "wake-up" command from the system and send the command through the configuration bus to the second CPLD chip of the detection acquisition preprocessing card, the third FPGA chip of the detection signal processing card, and the fifth FPGA chip of the reconnaissance interference signal acquisition processing card to power on each board chip. After each board reports the self-test completion status, the main control and interface adapter card sends the "start work" command to each board, and each board starts working.

[0046] S2. The detection acquisition preprocessing card converts the intermediate frequency signal 1 sent by the frequency conversion subsystem into a digital intermediate frequency signal through the first AD chip and sends it to the second FPGA chip. The second FPGA chip processes the digital intermediate frequency signal through filtering and other processes to obtain a digital baseband signal. According to the issued instruction parameter information, it sends it to the second to fifth DSPs of the detection signal processing card and the first FPGA chip of the main control and interface adapter card through the high-speed interconnect backplane.

[0047] The detection signal processing card processes the digital signals sent from the second FPGA chip of the detection acquisition preprocessing card through the processing algorithms programmed into the second to fifth DSP chips. The processing results are then sent to the main control and interface adapter card through the third FPGA chip of the detection signal processing card.

[0048] S3. The second FPGA chip of the detection and acquisition preprocessing card generates a digital intermediate frequency signal according to the instruction parameter information issued by the main control and interface adapter card and sends it to the first DA chip of the detection and acquisition preprocessing card, which then transmits the signal to the frequency conversion system.

[0049] The reconnaissance and interference signal acquisition and processing card has two working modes. Working mode one is to receive intermediate frequency signal 2, perform detailed data inversion on it, and send the results to the main control and interface adapter card. Working mode two is to receive intermediate frequency signal 3, identify it, and forward it to the frequency conversion system.

[0050] S4, Working Mode 1: The second AD chip converts the intermediate frequency signal 2 sent by the frequency conversion subsystem into a digital intermediate frequency signal and sends it to the fourth FPGA chip. The fourth FPGA chip converts the digital intermediate frequency signal 2 into a baseband signal. After processing by the internal algorithm of the fourth FPGA chip, the waveform frequency, pulse width, repetition frequency and other parameters of the intermediate frequency signal 2 are obtained and sent to the main control and interface adapter card. This information is further sent to the control system and the detection signal processing card as prior information for subsequent algorithms.

[0051] S5, Working Mode 2: The second AD chip converts the intermediate frequency signal 3 sent by the frequency conversion subsystem into a digital intermediate frequency signal and sends it to the fourth FPGA chip. The fourth FPGA chip performs waveform parameter analysis and, with reference to the processing results of working mode 1, obtains detailed waveform parameters. Based on the above information, it forms a transmission signal and sends it to the second DA chip. The second DA chip upconverts it to an intermediate frequency signal and sends it to the frequency conversion subsystem, thereby generating two transmission signals.

[0052] Figure 2 The block diagram shows the main control and interface adapter card. This card generates a system reset signal to reset all cards within the processing system. It is capable of configuring system parameters, sending control commands, receiving the status and self-test results of each card, and controlling the workflow and other subsystems. It also has the function of transmitting processing results and operating status to the control system. The main control and interface adapter card consists of three rigid PCBs connected by a flexible PCB. The first rigid PCB is the main functional module, the second rigid PCB is the high- and low-speed data module, and the third rigid PCB is the power supply module. The first rigid PCB includes a first FPGA chip, a first DSP chip, and a first CPLD chip.

[0053] Its functions and performance are as follows: (1) Receive commands and parameters from the external control system; (2) System power consumption control and generation of system reset signal; (3) Translate external commands into write and send them to each board; (4) Send the detection and reconnaissance echo data to the memory; (5) Receive the reconnaissance interference acquisition and processing results and perform reconnaissance algorithm processing; (6) Receive the results of detection, reconnaissance, and interference processing and send them to the control system; (7) Translate external commands according to the protocol and send them to each board, and report the status of each board to the telemetry system; (8) It has external communication interfaces such as synchronous 422, asynchronous 422, and fiber optic port; (9) Storage capacity: not less than 1GB; (10) Computational power: not less than 128 GFLOPS; (11) SRIO high-speed interface rate: not less than 5Gbps; (12) GbE interface rate; 1000Mb; Figure 3The block diagram of the detection and acquisition preprocessing card is shown. This card acquires 8 channels of intermediate frequency (IF) signals and performs preprocessing such as digital down-conversion and filtering; it generates 2 channels of IF transmission signals; it has the capability to configure a bus interface, receiving system parameters, control commands, global reset signals, etc. from the main control and interface adapter cards, and operates under the control of the main control and interface adapter cards; it sends results and operating status to the main control and interface adapter cards. The detection and acquisition preprocessing card consists of three rigid PCB boards connected by a flexible PCB. The fourth rigid PCB board is the main functional module, the fifth rigid PCB board is the high and low speed data module, and the sixth rigid PCB board is the power supply module. The fourth rigid PCB board includes a first AD chip, a second FPGA chip, a first DA chip, and a second CPLD chip.

[0054] Its functions and performance are as follows: (1) Receive work instructions and parameters (2) Send the working status and self-test results to the main controller and interface adapter card. (3) The board has low power consumption, full area reset and real-time reporting of operating temperature functions. (4) Receive the detection intermediate frequency signal, and after frequency conversion and preprocessing, send it to the detection signal processing card. (5) Generate detection intermediate frequency transmission signal (6) Send the stored raw echo to the main control and interface adapter card, and the real-time echo to the detection signal processing card. (7) The first AD chip is a high-bandwidth, high-speed sampling chip with 12 bits for A / D and a configurable sampling rate of 2.4 / 1.2 GSPS.

[0055] (8) The first DA chip is a high-bandwidth, high-speed digital-to-analog converter chip with a D / A bit width of 14 bits. (9) The first FPGA chip is the K7 series, with an equivalent logic gate count of 420,000; (10) The second FPGA chip is a V7 system. (11) Data transmission rate: 5Gbps; (12) Signal bandwidth: Broadband intermediate frequency ≤ 1000MHz; (13) Clutter suppression: less than -70dBc; (14) Phase noise: not greater than -100dBc / Hz@10kHz; (15) Input interface load impedance: 50Ω.

[0056] Figure 4The block diagram of the detection signal processing card is shown. This card processes digital baseband signals of various modes using corresponding algorithms and outputs the processing results. It has the capability to configure a bus interface, receiving system parameters, control commands, global reset signals, etc., from the main control and interface adapter cards, and operates under the control of the main control and interface adapter cards. It also sends results and operating status to the main control and interface adapter cards. The detection signal processing card consists of three rigid PCB boards connected by a flexible PCB. The seventh rigid PCB board is the main functional module, the eighth rigid PCB board is the high and low speed data module, and the ninth rigid PCB board is the power supply module. The seventh rigid PCB board includes a second DSP chip, a third DSP chip, a fourth DSP chip, a fifth DSP chip, and a third FPGA chip.

[0057] Its functions and performance are as follows: (1) Receive work instructions and parameters; (2) Send the working status and self-test results to the main controller and interface adapter card; (3) The board has low power consumption, full area reset and real-time reporting of operating temperature functions; (4) Receive the echo transmitted by the detection acquisition preprocessing card; (5) Send the processing results of each working mode to the main controller and interface adapter card; (6) The third FPGA is the V2 series; (7) The first to fifth DSP chips are all from the 6678 series; (8) Floating-point operation performance is not less than 512 GFLOPS@1GHz, and fixed-point operation performance is not less than 256 GMAC / s@1GHz; (9) Storage capacity: There is one DSP on the board, using 4 DDRs, with a total storage capacity of 2GB; (10) Transmission rate: The SRIO data interface rate shall not be less than 5Gbps / Lane, and the GbE interface rate shall be 1Gbps; Figure 5 The reconnaissance and jamming signal acquisition and processing card consists of three rigid PCBs connected via flexible PCBs. The tenth rigid PCB is the main functional module, the eleventh rigid PCB is the high- and low-speed data module, and the twelfth rigid PCB is the power supply module. The tenth rigid PCB includes a second AD chip, a second DA chip, a fourth FPGA chip, and a fifth FPGA chip.

[0058] Its functions and performance are as follows: (1) Receive work instructions and parameters; (2) Send the working status and self-test results to the main controller and interface adapter card; (3) The board has low power consumption, full area reset and real-time reporting of operating temperature functions; (4) Receive the echo transmitted by the detection acquisition preprocessing card; (5) Send the processing results of each working mode to the main controller and interface adapter card; (6) The second AD chip is a high-speed sampling chip with a sampling rate of not less than 2.6 Gsps and an A / D bit depth of 14 bits; (7) The second DA chip is a high-speed digital-to-analog converter chip with a maximum sampling rate of 6Gsps and an A / D bit depth of 12 bits; (8) The fourth FPGA is the Xilinx UltraScale+ series XCVU9P-2FLGB2104I of the VU9P series; (9) The fifth FPGA is the Fudan Micro A7 series FMK50.

[0059] The appearance of the power supply rigid-flexible board and the high / low speed signal interconnection rigid-flexible board connected to the rigid board in this embodiment is as follows: Figure 6 , Figure 7 As shown, this embodiment achieves the capabilities of multi-channel high-bandwidth acquisition and processing, multi-channel analog signal transmission, large-volume signal processing, multi-mode information fusion, and multi-interface data transmission at different rates, reducing size and weight, improving the digital signal processing capabilities of the radar processing system, and adapting to more application needs.

[0060] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A real-time signal processing system integrating reconnaissance, detection, and communication on a high-speed motion platform, characterized in that: It includes four types of functional boards, one type of high- and low-speed interconnect backplane, and one type of power supply backplane; The four functional boards are stacked on top of each other: main control and interface adapter card, detection acquisition preprocessing card, detection signal processing card, and reconnaissance and interference signal acquisition and processing card. The main control and interface adapter card, the detection and acquisition preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card are all functional boards using a rigid-flexible design method. Each functional board consists of a main functional module, a high-speed and low-speed data module for data transmission, and a power supply module, and all are rigid boards. One side of the main functional module is connected to the high-speed and low-speed data module through a flexible board, and the other side is connected to the power supply module through another flexible board. All the high-speed and low-speed data modules are pluggably connected to the same high-speed and low-speed interconnect backplane slot, and all the power supply modules are pluggably connected to the same power supply backplane slot. The main control and interface adapter card generates system reset signals and global reset signals to reset the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card. The main control and interface adapter card configures system parameters and sends control commands, and receives the status, self-test results, and signal processing results of the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card. The main functional module of the main control and interface adapter card includes a first FPGA chip, a first DSP chip, and a first CPLD chip. The first CPLD chip controls the power-on mode and inter-board data transmission of the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card. The first FPGA chip sends the instruction parsing results to the corresponding board and receives results and status information reported by other boards through the address and data lines of the first CPLD. The first FPGA chip outputs to the control system through a 422 interface chip to achieve real-time result reporting. The detection and acquisition preprocessing card receives the intermediate frequency signal output by the frequency conversion subsystem, performs down-conversion and filtering, and outputs a digital baseband signal to the detection signal processing card; the detection and acquisition preprocessing card generates an intermediate frequency transmission signal; The detection signal processing card performs algorithmic processing on the digital baseband signal and outputs the processing results. The reconnaissance jamming signal acquisition and processing card acquires at least two broadband intermediate frequency signals, performs digital down-conversion, and then performs corresponding digital signal processing according to different working modes to generate intermediate frequency transmission signals, which are simultaneously transmitted to the main control and interface adapter card and then output to the control system. The plug-in design of the integrated real-time signal processing system for reconnaissance, interception, and communication under the high-speed motion platform facilitates expansion and upgrades, and enables collaborative processing of digital signals in multiple working modes of reconnaissance, interception, and communication.

2. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 1, characterized in that: The main functional module of the main control and interface adapter card receives instructions and parameters from the external control system, performs system power consumption control, generates a system reset signal, transcribes external instructions and sends them to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card, sends detection echo data and reconnaissance echo data to the memory, receives the output results of the detection signal processing card and the reconnaissance and interference signal acquisition and processing card and performs reconnaissance algorithm processing, receives the detection, reconnaissance, and interference processing results and sends them to the control system, transcribes external instructions according to the protocol and sends them to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card, and reports the status of the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card to the telemetry system. It has synchronous 422, asynchronous 422, and fiber optic external communication interfaces.

3. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed motion platform according to claim 2, characterized in that: The first FPGA chip forms different interface drivers to complete the data transmission between the internal boards of the detection signal processing card component and the control system and internal boards. The first DSP chip parses instructions and converts the data sent by the control system into parameters required by each board. The main controller and interface adapter card controls the power supply status of the first DSP chip and the first FPGA chip through the first CPLD chip, receives the instruction parameters issued by the control system through the first FPGA chip, and transmits them to the first DSP chip. The first DSP chip performs instruction parsing and conversion and transmits the results to the first FPGA chip. The controller and interface adapter card has a storage capacity of no less than 1GB, a computing power of no less than 128GFLOPS, an SRIO high-speed interface rate of no less than 5Gbps, and a GbE interface rate of 1000Mb.

4. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 1, characterized in that: The main functional module of the detection acquisition preprocessing card acquires 8 intermediate frequency signals, performs digital down-conversion and filtering, and outputs the digital baseband signal to the detection signal processing card; the detection acquisition preprocessing card has the ability to configure a bus interface and can report the operating temperature in real time. The detection and acquisition preprocessing card generates two channels of analog intermediate frequency transmission signals; The detection and acquisition preprocessing card can send and store the raw echoes to the main control and interface adapter card.

5. The integrated real-time signal processing system for reconnaissance and communication on a high-speed moving platform according to claim 4, characterized in that: The main functional modules of the detection acquisition preprocessing card include a first AD chip, a second FPGA chip, a first DA chip, and a second CPLD chip; The first AD chip converts the intermediate frequency signal into a digital intermediate frequency signal and outputs it to the second FPGA chip. The second FPGA chip performs digital down-conversion preprocessing on the digital intermediate frequency signal and generates the digital baseband signal, which is then output to the detection signal processing card through the high-low speed interconnect backplane. The second FPGA chip generates a digital intermediate frequency signal according to the instruction parameter information issued by the main controller and interface adapter card, and sends it to the first DA chip to be converted into an analog intermediate frequency transmission signal; The second CPLD controls the power supply to the chip on the detection acquisition preprocessing card and the data transmission between it and other boards; The first AD chip is a high-bandwidth, high-speed sampling chip with 12-bit A / D bit depth and a configurable sampling rate of 2.4 / 1.2 GSPS. The first DA chip is a high-bandwidth, high-speed digital-to-analog converter chip with a D / A bit width of 14 bits; The first FPGA chip has an equivalent logic gate count of 420,000. The data transmission rate of the detection and acquisition preprocessing card is 5Gbps, with an intermediate frequency of ≤1000MHz, clutter suppression of less than -70dBc, phase noise of not more than -100dBc / Hz@10kHz, and an input interface load impedance of 50Ω.

6. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 1, characterized in that: The main functional modules of the detection signal processing card include a second DSP chip, a third DSP chip, a fourth DSP chip, a fifth DSP chip, and a third FPGA chip. The detection signal processing card has the ability to configure a bus interface and can report the operating temperature in real time. The detection signal processing card receives the digital baseband signal output by the detection acquisition preprocessing card, performs real-time digital baseband signal processing through the second DSP chip, the third DSP chip, the fourth DSP chip and the fifth DSP chip to obtain the processing result, and transmits the processing result to the main control and interface adapter card through the third FPGA chip. The detection signal processing card has a floating-point performance of no less than 512 GFLOPS@1GHz, a fixed-point performance of no less than 256 GMAC / s@1GHz, a total storage capacity of 2GB, an SRIO data interface rate of no less than 5Gbps / Lane, and a GbE interface rate of 1Gbps.

7. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 1, characterized in that: The main functional module of the reconnaissance and interference signal acquisition and processing card acquires 12 channels of broadband intermediate frequency signals, performs digital down-conversion, and performs corresponding digital signal processing according to different working modes; the reconnaissance and interference signal acquisition and processing card generates 2 channels of intermediate frequency transmission signals, and the reconnaissance and interference signal acquisition and processing card has the ability to configure a bus interface and can report the working temperature in real time.

8. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 7, characterized in that: The main functional modules of the reconnaissance jamming signal acquisition and processing card include a second AD chip, a second DA chip, a fourth FPGA chip, and a fifth FPGA chip; The second AD chip converts the acquired intermediate frequency signal into a digital intermediate frequency signal. The fourth FPGA chip converts the digital intermediate frequency signal into a digital baseband signal through digital down-conversion and performs signal processing to obtain the processing result. The fourth FPGA chip outputs the processing result to the fifth FPGA chip. The fifth FPGA chip transmits the processing result to the main control and interface adapter card and then outputs it to the control system. The second DA chip upconverts the digital baseband signal into a digital intermediate frequency signal, generating two detection and transmission intermediate frequency signals.

9. The integrated real-time signal processing system for reconnaissance, detection, and communication on a high-speed moving platform according to claim 1, characterized in that: The high- and low-speed interconnection backplane completes the high-frequency and low-frequency signal transmission and communication between internal boards of the signal processing system through connectors, and the power supply backplane is connected to each power supply module inside the detection signal processing card assembly through connectors to provide power. The main control and interface adapter card, the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance and interference signal acquisition and processing card are stacked in sequence.

10. A real-time signal processing method integrating reconnaissance and communication under a high-speed moving platform, implemented by the real-time signal processing system integrating reconnaissance and communication under a high-speed moving platform as described in claim 1, characterized in that: Includes the following steps: S1. After power-on, the main control and interface adapter card receives a wake-up command from the system and sends the wake-up command through the configuration bus to the second CPLD chip of the detection acquisition preprocessing card, the third FPGA chip of the detection signal processing card, and the fifth FPGA chip of the reconnaissance interference signal acquisition and processing card. At the same time, it controls the power supply backplane to power on the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card. After the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card report the self-test completion status, the main control and interface adapter card sends a start-up command to the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card, and the detection acquisition preprocessing card, the detection signal processing card, and the reconnaissance interference signal acquisition and processing card begin to work. When the frequency conversion subsystem sends an intermediate frequency signal to the main control and interface adapter card, it proceeds to step S2; when the detection acquisition preprocessing card outputs an intermediate frequency signal, it proceeds to step S3; when the reconnaissance interference signal acquisition and processing card acquires the intermediate frequency signal and parses the prior information, it proceeds to step S4; when the reconnaissance interference signal acquisition and processing card parses the detailed waveform parameters and generates an intermediate frequency transmission signal, it proceeds to step S5. S2. The first AD chip of the detection and acquisition preprocessing card converts the intermediate frequency signal sent by the frequency conversion subsystem into a digital intermediate frequency signal and sends it to the second FPGA chip of the detection and acquisition preprocessing card. The second FPGA chip filters the digital intermediate frequency signal to obtain a digital baseband signal, and sends it to the second DSP, third DSP, fourth DSP, and fifth DSP of the detection signal processing card, as well as the first FPGA chip of the main control and interface adapter card, through the high-low speed interconnect backplane according to the instruction parameter information sent by the main control and interface adapter card. The second DSP, the third DSP, the fourth DSP, and the fifth DSP analyze, detect, and probe the digital baseband signal sent by the second FPGA chip, and then send it to the main control and interface adapter card through the third FPGA chip of the detection signal processing card. S3. The second FPGA chip of the detection and acquisition preprocessing card generates a digital intermediate frequency signal according to the instruction parameter information issued by the main control and interface adapter card and sends it to the first DA chip of the detection and acquisition preprocessing card. The first DA chip converts the digital intermediate frequency signal into an analog intermediate frequency signal and outputs it to the frequency conversion subsystem. S4. The second AD chip of the reconnaissance jamming signal acquisition and processing card converts the intermediate frequency signal into a digital intermediate frequency signal and sends it to the fourth FPGA chip of the reconnaissance jamming signal acquisition and processing card. The fourth FPGA chip converts the digital intermediate frequency signal into a baseband signal. After processing by the internal algorithm of the fourth FPGA chip, the waveform frequency, pulse width, and repetition frequency of the intermediate frequency signal are obtained and sent to the main control and interface adapter card, and further sent to the control system and the detection signal processing card as prior information for subsequent algorithms. S5. The second AD chip converts the intermediate frequency signal into a digital intermediate frequency signal and sends it to the fourth FPGA chip. The fourth FPGA chip performs waveform parameter analysis and obtains detailed waveform parameters by referring to the processing result of step S4. Based on the detailed waveform parameters, it forms a transmit digital signal and sends it to the second DA chip of the reconnaissance and interference signal acquisition and processing card. The second DA chip upconverts the transmit digital signal into a transmit intermediate frequency signal.

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