Manufacturing method of semiconductor chip test board

Abstract

The invention discloses a manufacturing method of a semiconductor chip test board, and belongs to the technical field of printed circuit boards, the position of a rivet hole is determined through a first reference hole so as to ensure the alignment degree of the whole board, the position of an in-board positioning hole and the position of an in-board correction hole are respectively determined through a second reference hole and a third reference hole, and the alignment degree of the whole board is ensured based on the position of the in-board positioning hole. In-board correction holes are drilled on the periphery of the ball grid array package, the alignment degree of the periphery of the ball grid array package is ensured, the positioning complexity and cost are reduced, and the problems that the alignment degree of the periphery of the ball grid array package position is adjusted by adopting the alignment degree of the whole PCB at present, the alignment effect is poor, and the board cutting rate is low are solved.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor chip test board, belonging to the field of printed circuit board technology. Background Technology

[0002] To cope with the increasing trend of high density, high performance and high pin count of chips under test (DUT), semiconductor chip test PCBs use finer pin pitches in chip packages. In order to physically connect and electrically accurately test, the PCB must adopt a matching fine pitch design. However, the small pitch design brings difficulties to PCB manufacturing. The most significant difficulty is the small pitch alignment problem, which will affect the electrical performance and reliability of the product.

[0003] The current processing method involves selecting appropriate inner dimensions before manufacturing and setting a corresponding number and different arrangement positions of rivet holes and pads around the inner substrate. The pad positioning holes are punched using a high-precision 8CCD punching machine. When the prepreg is stacked with the substrate, an automatic rivet opening method is used for fixing. Finally, the pins are fixed on a small-format pressing machine for curing and pressing. However, the current processing method only adjusts the fixing method of the PCB board material and only focuses on the overall board alignment performance. It is not fully applicable to the high-difficulty design of small-pitch local alignment around the ball grid array package position of semiconductor PCBs. It is only applicable to ordinary high-layer alignment control methods. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for manufacturing a semiconductor chip test board. This method improves the local alignment of small-pitch areas around the ball grid array package position on the semiconductor PCB, reduces positioning complexity and cost, and solves the problems of poor alignment effect and low board cutting rate when using the alignment of the entire PCB board to adjust the alignment of the ball grid array package position.

[0005] To solve the above-mentioned technical problems, the present invention is implemented using the following technical solution: This invention provides a method for fabricating a semiconductor chip test board, comprising: Around the PCB test chip socket area, board edge and ball grid array package of the outer substrate, select multiple pre-made positioning through holes, which are respectively used as the first reference hole, the second reference hole and the third reference hole; The positions of rivet holes, in-board positioning holes, and in-board correction holes are determined at the positions corresponding to the first reference hole, the second reference hole, and the third reference hole on multiple inner layer substrates, respectively. Make rivet holes at the rivet hole locations; According to a preset order, the outer substrate and multiple inner substrates are stacked and rivets are inserted into the rivet holes to form a stacked board; The stacked plates are pressed together to obtain the initial material. Based on the positions of the positioning holes and the calibration holes, in-board calibration holes are drilled around the ball grid array package.

[0006] Further, determining the rivet hole position includes: Around the PCB test chip socket area of ​​the outer substrate, select at least four pre-made positioning through holes as the first reference holes; The rivet hole positions are determined at the locations corresponding to the first reference holes on multiple inner layer substrates.

[0007] Furthermore, the process of creating the rivet hole at the rivet hole location includes: Create rivet hole pads at the rivet hole locations; Based on the rivet hole pads, holes are drilled at the rivet hole positions of multiple inner layer substrates to form rivet holes.

[0008] Further, determining the position of the positioning hole within the plate includes: Four pre-made positioning through holes are selected at the four corners of the outer substrate as second reference holes. The positions of the positioning holes in the board are determined at the positions corresponding to the second reference holes in multiple inner substrates.

[0009] Further, determining the position of the calibration hole within the plate includes: Four pre-fabricated positioning through holes are selected at the four corners of the ball grid array package on the outer substrate as the third reference holes. The positions of the correction holes in the board are determined at the locations corresponding to the third reference holes on multiple inner substrates.

[0010] Furthermore, drilling in-board calibration holes around the ball grid array package based on the positions of the in-board positioning holes and the in-board calibration holes includes: Drill the internal positioning holes on the initial board according to the position of the internal positioning holes; Using the positioning holes inside the board as a reference, pre-drill the alignment holes inside the board at the positions of the alignment holes inside the board. If the grade of the pre-drilled correction hole in the plate meets the requirements, then drill the correction hole in the plate.

[0011] Furthermore, if the grade of the pre-drilled correction hole in the plate meets the requirements, then drilling the correction hole in the plate includes: Define a range of pre-drilled in-plate correction hole grades around the center of the in-plate correction hole location to limit the offset of the drilling center. If the center of the correction hole in the pre-drilled plate is within the range of the correction hole grade in the pre-drilled plate, then the correction hole in the plate is drilled directly.

[0012] Furthermore, after determining the positions of the rivet holes, the in-board positioning holes, and the in-board correction holes at the positions corresponding to the first reference hole, the second reference hole, and the third reference hole on the multiple inner layer substrates, it is also necessary to fabricate layer offset test holes for detecting the layer offset performance around the ball grid array package, including: Four pre-made positioning through holes are selected as the fourth reference holes on the four edges of the outer substrate. The locations of the layer offset test holes are determined at positions corresponding to the fourth reference holes on multiple inner layer substrates. Based on the location of the positioning holes inside the board, a layer deviation test hole is drilled at the location of the layer deviation test hole.

[0013] Furthermore, the step of drilling a layer misalignment test hole at the layer misalignment test hole location based on the position of the positioning hole within the board includes: Drill a grounding hole at the center of the positioning hole inside the board; Drill layer offset test holes with equal gradients on one side in a clockwise direction around the circumference of the grounding hole.

[0014] Furthermore, the gradient is 0.25 mil.

[0015] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: 1. This invention determines the rivet hole position through a first reference hole to ensure the alignment of the entire board. Then, it determines the position of the positioning hole and the correction hole in the board through a second reference hole and a third reference hole, respectively. Based on the position of the positioning hole in the board, correction holes are drilled around the ball grid array package to ensure the alignment of the ball grid array package periphery. This reduces the positioning complexity and cost, and solves the problems of poor alignment effect and low board cutting rate when adjusting the alignment of the ball grid array package periphery using the alignment of the entire PCB board.

[0016] 2. Based on the location of the positioning holes inside the board, a grounding hole is drilled at the center of the positioning hole. In a circle with the grounding hole as the center, layer deviation test holes with equal gradients on one side are drilled in a clockwise direction. After the electroplating of each drilled hole is completed, a multimeter can be used to test the layer deviation test holes with equal gradients on one side. Then, by checking the connection status of layer deviation test holes of different sizes, the layer deviation performance of the board can be determined. Finally, the electrical performance of the finished product can be estimated by using the electrical properties of the semi-finished board. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor chip test board according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a semiconductor chip test board provided in an embodiment of the present invention (the fourth reference hole is not shown). Figure 3This is a schematic diagram showing the specific location of the first reference hole provided in an embodiment of the present invention; Figure 4 yes Figure 2 Enlarged view of point A in the middle; Figure 5 This is a schematic diagram of the structure of a semiconductor chip test board provided in an embodiment of the present invention (showing the fourth reference hole); Figure 6 This is a schematic diagram of the position of the in-plate correction hole provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the location of the layer offset test hole provided in an embodiment of the present invention.

[0018] In the diagram: 1. Outer substrate; 2. PCB test chip socket area; 3. Ball grid array package; 4. First reference hole; 5. Second reference hole; 6. Third reference hole; 7. Fourth reference hole; 701. First layer offset test hole; 702. Second layer offset test hole; 703. Third layer offset test hole; 704. Fourth layer offset test hole; 705. Fifth layer offset test hole; 706. Sixth layer offset test hole; 707. Grounding hole. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention. Example 1

[0020] like Figure 1 As shown, a method for fabricating a semiconductor chip test board includes: like Figure 2 and Figure 4 As shown, multiple pre-fabricated positioning vias are selected around the PCB test chip socket area 2, the board edge, and the ball grid array package 3 on the outer substrate 1, respectively serving as the first reference hole 4, the second reference hole 5, and the third reference hole 6. Specifically: like Figure 3 As shown, around the PCB test chip socket area 2 of the outer substrate 1, at least four pre-made positioning through holes with a diameter ≥ 4.4 mm are selected as the first reference holes 4. In this embodiment, there are four first reference holes 4; Four pre-made positioning through holes are selected at the four corners of the outer substrate 1 as the second reference holes 5. At the four corners of the ball grid array package 3 on the outer substrate 1, four pre-made positioning through holes are selected as the third reference holes 6.

[0021] The positions of rivet holes, in-board positioning holes, and in-board alignment holes are determined at the positions corresponding to the first reference hole 4, the second reference hole 5, and the third reference hole 6 on multiple inner layer substrates, respectively. Specifically: The positions of the rivet holes are determined at the positions corresponding to the first reference hole 4 on multiple inner layer substrates; The positions of multiple inner layer substrates corresponding to the second reference hole 5 are used to determine the positions of the positioning holes in the board. The positions of the correction holes in the board are determined at the positions corresponding to the third reference hole 6 on multiple inner substrates.

[0022] Make rivet holes at the rivet hole locations, specifically: Create a 2.0mm rivet hole pad at the rivet hole location; A high-precision CCD punching device is used to capture the rivet hole pads and punch holes at the rivet hole positions of multiple inner layer substrates to form rivet holes.

[0023] According to a preset sequence, the outer substrate 1 and multiple inner substrates are stacked and rivets are inserted into the rivet holes to form a stacked board; The stacked plates are pressed together to obtain the initial material. It should be noted that after the laminated boards are pressed together, rivet removal is also required. Specifically: First, perform blind reaming from the rivet head surface. The blind reaming circle has a diameter of 4.2mm, and the center of the blind reaming circle and the center of the positioning through hole must be in the same position. Blind fishing method: All program tools use 2.4mm retrieval needles. First, use program tools T01 & T02 to retrieve a blind groove of 4.2mm in size. The depth of T01 is set to 0.15mm and the depth of T02 is set to 0.30mm. Then use program tools T03 & T04 to start scooping out a blind groove with a size of 3.8mm, scooping out a depth of 0.4mm each time; where T03 is set to a depth of 0.7mm and T04 to a depth of 1.1mm; until the positioning through hole is scooped out.

[0024] Based on the positions of the in-board positioning holes and in-board alignment holes, in-board alignment holes are drilled around the ball grid array package 3. Specifically: Drill the internal positioning holes on the initial board according to the position of the internal positioning holes; Using the positioning holes inside the board as a reference, pre-drill the alignment holes inside the board at the positions of the alignment holes inside the board. If the pre-drilled alignment holes in the plate meet the requirements, then drill the alignment holes in the plate, including: Define a range of pre-drilled in-plate correction hole grades around the center of the in-plate correction hole location to limit the offset of the drilling center. If the center of the correction hole in the pre-drilled plate is within the range of the correction hole grade in the pre-drilled plate, then the correction hole in the plate is drilled directly. like Figure 6 As shown, for ease of understanding, four holes are used around the center of the correction hole position in the board to represent the range of the pre-drilled correction hole level. As long as the center of the pre-drilled correction hole in the board does not deviate from the rectangular range enclosed by the centers of the four holes, the correction hole in the board can be drilled directly. Example 2

[0025] like Figure 1 As shown, a method for fabricating a semiconductor chip test board includes: like Figure 2 and Figure 4 As shown, multiple pre-fabricated positioning vias are selected around the PCB test chip socket area 2, the board edge, and the ball grid array package 3 on the outer substrate 1, respectively serving as the first reference hole 4, the second reference hole 5, and the third reference hole 6. Specifically: like Figure 3 As shown, around the PCB test chip socket area 2 of the outer substrate 1, at least four pre-made positioning through holes with a diameter ≥ 4.4 mm are selected as the first reference holes 4. In this embodiment, there are four first reference holes 4; Four pre-made positioning through holes are selected at the four corners of the outer substrate 1 as the second reference holes 5. At the four corners of the ball grid array package 3 on the outer substrate 1, four pre-made positioning through holes are selected as the third reference holes 6.

[0026] The positions of rivet holes, in-board positioning holes, and in-board alignment holes are determined at the positions corresponding to the first reference hole 4, the second reference hole 5, and the third reference hole 6 on multiple inner layer substrates, respectively. Specifically: The positions of the rivet holes are determined at the positions corresponding to the first reference hole 4 on multiple inner layer substrates; The positions of multiple inner layer substrates corresponding to the second reference hole 5 are used to determine the positions of the positioning holes in the board. The positions of the correction holes in the board are determined at the positions corresponding to the third reference hole 6 on multiple inner substrates.

[0027] Make rivet holes at the rivet hole locations, specifically: Create a 2.0mm rivet hole pad at the rivet hole location; A high-precision CCD punching device is used to capture the rivet hole pads and punch holes at the rivet hole positions of multiple inner layer substrates to form rivet holes.

[0028] According to a preset sequence, the outer substrate 1 and multiple inner substrates are stacked and rivets are inserted into the rivet holes to form a stacked board; The stacked plates are pressed together to obtain the initial material. It should be noted that after the laminated boards are pressed together, rivet removal is also required. Specifically: First, perform blind reaming from the rivet head surface. The blind reaming circle has a diameter of 4.2mm, and the center of the blind reaming circle and the center of the positioning through hole must be in the same position. Blind fishing method: All program tools use 2.4mm retrieval needles. First, use program tools T01 & T02 to retrieve a blind groove of 4.2mm in size. The depth of T01 is set to 0.15mm and the depth of T02 is set to 0.30mm. Then use program tools T03 & T04 to start scooping out a blind groove with a size of 3.8mm, scooping out a depth of 0.4mm each time; where T03 is set to a depth of 0.7mm and T04 to a depth of 1.1mm; until the positioning through hole is scooped out.

[0029] Based on the positions of the in-board positioning holes and in-board alignment holes, in-board alignment holes are drilled around the ball grid array package 3. Specifically: At the location of the positioning hole on the board, fabricate a positioning hole pad with a size of 2.0mm; The initial board is placed on the milling station, and a new 1.6mm needle is used on the X-ray machine to drill holes on both sides of the positioning hole pad inside the board. First, drill through half of the board from the front side, then flip it over and drill through to obtain the positioning hole inside the board. Using the positioning holes inside the board as a reference, pre-drill the alignment holes inside the board at the positions of the alignment holes inside the board. If the pre-drilled alignment holes in the plate meet the requirements, then drill the alignment holes in the plate, including: Define a range of pre-drilled in-plate correction hole grades around the center of the in-plate correction hole location to limit the offset of the drilling center. If the center of the correction hole in the pre-drilled plate is within the range of the correction hole grade in the pre-drilled plate, then the correction hole in the plate is drilled directly. like Figure 6 As shown, for ease of understanding, four holes are used around the center of the correction hole position in the board to represent the range of the pre-drilled correction hole level. As long as the center of the pre-drilled correction hole in the board does not deviate from the rectangular range enclosed by the centers of the four holes, the correction hole in the board can be drilled directly.

[0030] like Figure 5 As shown, layer offset test holes are fabricated for detecting the layer offset performance around the ball grid array package 3. Specifically: Four pre-made positioning through holes with a diameter > 3mm are selected on the four edges of the outer substrate 1 as the fourth reference holes 7. The positions of the layer offset test holes are determined at the positions corresponding to the fourth reference hole 7 on multiple inner layer substrates; like Figure 7 As shown, based on the position of the positioning hole inside the board, a layer misalignment test hole is drilled at the position of the layer misalignment test hole, including: Drill a grounding hole 707 at the center of the positioning hole inside the board; Around the circumference centered on the grounding hole 707, with a gradient of 0.25 mil, drill off-center test holes 701 with a single side dimension of 1.5 mil, 702 with a single side dimension of 1.75 mil, 703 with a single side dimension of 2 mil, 704 with a single side dimension of 2.25 mil, 705 with a single side dimension of 2.5 mil, and 706 with a single side dimension of 2.75 mil in a clockwise direction.

[0031] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor chip test board, characterized in that, include: Around the PCB test chip socket area, board edge and ball grid array package of the outer substrate, select multiple pre-made positioning through holes, which are respectively used as the first reference hole, the second reference hole and the third reference hole; The positions of rivet holes, in-board positioning holes, and in-board correction holes are determined at the positions corresponding to the first reference hole, the second reference hole, and the third reference hole on multiple inner layer substrates, respectively. Make rivet holes at the rivet hole locations; According to a preset order, the outer substrate and multiple inner substrates are stacked and rivets are inserted into the rivet holes to form a stacked board; The stacked plates are pressed together to obtain the initial material. Based on the positions of the positioning holes and the calibration holes, in-board calibration holes are drilled around the ball grid array package.

2. The method for fabricating a semiconductor chip test board according to claim 1, characterized in that, Determining the rivet hole position includes: Around the PCB test chip socket area of ​​the outer substrate, select at least four pre-made positioning through holes as the first reference holes; The rivet hole positions are determined at the locations corresponding to the first reference holes on multiple inner layer substrates.

3. The method for fabricating a semiconductor chip test board according to claim 2, characterized in that, The process of creating a rivet hole at the rivet hole location includes: Create rivet hole pads at the rivet hole locations; Based on the rivet hole pads, holes are drilled at the rivet hole positions of multiple inner layer substrates to form rivet holes.

4. The method for fabricating a semiconductor chip test board according to claim 1, characterized in that, Determining the position of the positioning hole inside the plate includes: Four pre-made positioning through holes are selected at the four corners of the outer substrate as second reference holes. The positions of the positioning holes in the board are determined at the positions corresponding to the second reference holes in multiple inner substrates.

5. The method for fabricating a semiconductor chip test board according to claim 1, characterized in that, Determining the position of the correction hole within the plate includes: Four pre-fabricated positioning through holes are selected at the four corners of the ball grid array package on the outer substrate as the third reference holes. The positions of the correction holes in the board are determined at the locations corresponding to the third reference holes on multiple inner substrates.

6. The method for fabricating a semiconductor chip test board according to claim 1, characterized in that, The method of drilling in-board calibration holes around the ball grid array package based on the positions of in-board positioning holes and in-board calibration holes includes: Drill the internal positioning holes on the initial board according to the position of the internal positioning holes; Using the positioning holes inside the board as a reference, pre-drill the alignment holes inside the board at the positions of the alignment holes inside the board. If the grade of the pre-drilled correction hole in the plate meets the requirements, then drill the correction hole in the plate.

7. The method for fabricating a semiconductor chip test board according to claim 6, characterized in that, If the grade of the pre-drilled correction hole in the plate meets the requirements, then drilling the correction hole in the plate includes: Define a range of pre-drilled in-plate correction hole grades around the center of the in-plate correction hole location to limit the offset of the drilling center. If the center of the correction hole in the pre-drilled plate is within the range of the correction hole grade in the pre-drilled plate, then the correction hole in the plate is drilled directly.

8. The method for fabricating a semiconductor chip test board according to claim 1, characterized in that, After determining the positions of the rivet holes, in-board positioning holes, and in-board correction holes at the positions corresponding to the first reference hole, second reference hole, and third reference hole on the multiple inner layer substrates, it is also necessary to fabricate layer offset test holes for detecting the layer offset performance around the ball grid array package, including: Four pre-made positioning through holes are selected as the fourth reference holes on the four edges of the outer substrate. The locations of the layer offset test holes are determined at positions corresponding to the fourth reference holes on multiple inner layer substrates. Based on the location of the positioning holes inside the board, a layer deviation test hole is drilled at the location of the layer deviation test hole.

9. The method for fabricating a semiconductor chip test board according to claim 8, characterized in that, The step of drilling a layer offset test hole at the layer offset test hole location based on the position of the positioning hole in the board includes: Drill a grounding hole at the center of the positioning hole inside the board; Drill layer offset test holes with equal gradients on one side in a clockwise direction around the circumference of the grounding hole.

10. The method for fabricating a semiconductor chip test board according to claim 9, characterized in that, The gradient is 0.25 mil.

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