Printed circuit board and method of manufacturing the same
By setting a more reactive metal layer on the printed circuit board and using an acidic solution to etch and form gaps, combined with conductive materials and electroplating, the problem of mechanical drilling being unable to completely remove residual stubs was solved, thus improving signal quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KINWONG ELECTRONIC TECH (ZHUHAI) CO LTD
- Filing Date
- 2026-01-14
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, it is difficult to completely remove residual vias on printed circuit boards by mechanical drilling, which adversely affects signal reflection and timing and voltage tolerance of high-speed serial links.
A metal layer with a higher reactivity than the material of the circuit pads is placed on the substrate of the printed circuit board. An acidic solution is used to erode the metal layer to form gaps, and a conductive material is placed on the inner wall of the via. Electroplating is performed through the conductive part to form an electroplated layer to cover the conductive part, and residual solder is removed.
It effectively removes residual stubs at the via locations, ensuring signal quality, avoiding signal reflection and resonance, and improving the performance of high-speed serial links.
Smart Images
Figure CN121665475B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of printed circuit board manufacturing technology, and in particular to a printed circuit board and a method for manufacturing the same. Background Technology
[0002] In the process of manufacturing printed circuit boards, vias are usually processed on the printed circuit board, and then an electroplating layer is placed inside the via. The electroplating layer is used to connect with signal lines and conduct electricity. Then, the printed circuit board needs to be back-drilled by mechanical drilling to remove the stubs in the vias, so as to avoid the stubs causing signal reflection, resonance at specific frequencies, and adverse effects on the timing and voltage tolerance of high-speed serial links.
[0003] Due to limitations in the physical structure of the drill bit, the precision limits of drilling depth control, and the influence of factors such as the material of the printed circuit board itself and deformation during processing, conventional mechanical drilling methods for back-drilling printed circuit boards to remove residual through holes cannot completely remove the residual through holes. Summary of the Invention
[0004] This application provides a printed circuit board and a method for manufacturing the same, which can more completely remove residual vias.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board, comprising:
[0006] A substrate is provided, the substrate comprising a dielectric layer and a basic circuit layer stacked thereon, the basic circuit layer comprising circuit pads;
[0007] A metal layer is disposed on the surface of the circuit pads away from the dielectric layer, wherein the material of the metal layer is more reactive than the material of the circuit pads.
[0008] A first connection layer and a first sub-board are stacked on one side of the substrate, and a second connection layer and a second sub-board are stacked on the other side of the substrate. The first connection layer is located between the dielectric layer and the first sub-board, and the second connection layer is located between the basic circuit layer and the second sub-board. The first sub-board includes a first circuit layer.
[0009] The first sub-board, the first connecting layer, the substrate, the second connecting layer, and the second sub-board are pressed together to obtain the mother board;
[0010] Vias are machined on the motherboard, and the vias penetrate the first daughterboard, the first connection layer, the dielectric layer, the circuit pads, the second connection layer, and the second daughterboard.
[0011] The metal layer is etched using an acidic solution to remove it and create a first gap between the circuit pads and the second interconnect layer, with the via penetrating the first gap.
[0012] A conductive material is disposed on the inner wall of the via. The conductive material includes a first conductive part and a second conductive part disposed along the axial direction of the via. A second gap is formed between the first conductive part and the second conductive part. The second gap is disposed corresponding to the first gap. The second conductive part is located on the side of the circuit pad away from the first circuit layer. The circuit pad and the first circuit layer are both connected to the first conductive part. The circuit pad and the second conductive part are spaced apart.
[0013] The motherboard is electroplated through the first conductive part to form a first electroplating layer, and the first electroplating layer covers the first conductive part.
[0014] Remove the second conductive part.
[0015] In some embodiments, the acidic solution is a hydrochloric acid solution, a sulfuric acid solution, a nitric acid solution, or an acidic mixture.
[0016] In some embodiments, the circuit pads are made of copper, and the metal layer is made of nickel, tin, zinc, lead-tin alloy, or tin-bismuth alloy.
[0017] In some embodiments, the second conductive portion is removed by chemical etching or reverse electroplating.
[0018] In some embodiments, the provision of a metal layer on the portion of the surface of the line pads facing away from the dielectric layer includes:
[0019] A first film is disposed on the surface of the circuit pads away from the dielectric layer. The first film has a window that exposes a portion of the circuit pads.
[0020] The metal layer is disposed on the surface of the circuit pads exposed by the window;
[0021] Remove the first membrane.
[0022] In some embodiments, after the metal layer is deposited on the surface of the circuit pads opposite to the dielectric layer, and before the first interconnect layer and the first sub-board are sequentially stacked on one side of the substrate, the method of manufacturing the printed circuit board further includes:
[0023] A second film is disposed on the substrate, the second film covering the metal layer;
[0024] The substrate is subjected to a browning treatment;
[0025] Remove the second membrane.
[0026] In some embodiments, after removing the second conductive portion, the method for manufacturing the printed circuit board further includes:
[0027] The motherboard is electroplated using the first electroplating layer to form a second electroplating layer, which covers the first electroplating layer.
[0028] In some embodiments, after electroplating the motherboard through the first electroplating layer to form the second electroplating layer, resin is filled into the through hole and the resin is cured, with a portion of the resin filling the first gap.
[0029] In some embodiments, two copies each of the substrate, the first connecting layer, the first sub-board, and the second connecting layer are provided; the step of stacking the first connecting layer and the first sub-board on one side of the substrate, and sequentially stacking the second connecting layer and the second sub-board on the other side of the substrate includes:
[0030] One of the first connecting layers and one of the first sub-boards are stacked on one side of one of the substrates, and one of the second connecting layers and the second sub-board are stacked on the other side of the current substrate. Another first connecting layer and another first sub-board are stacked on one side of the other substrate, and another second connecting layer is stacked on the other side of the other substrate, with the second sub-board located between the two second connecting layers.
[0031] Secondly, embodiments of this application provide a printed circuit board, which is manufactured by the printed circuit board manufacturing method described in the first aspect.
[0032] The printed circuit board manufacturing method provided in this application has the following advantages: First, a metal layer is deposited on the surface of the circuit pads of the basic circuit layer on the substrate, away from the dielectric layer. The metal layer has a higher reactivity than the circuit pads. Then, a first interconnect layer and a first sub-board are stacked on one side of the substrate, and a second interconnect layer and a second sub-board are stacked on the other side of the substrate. The first interconnect layer is located between the dielectric layer and the first sub-board, and the second interconnect layer is located between the basic circuit layer and the second sub-board. The first sub-board includes the first circuit layer. Then, the first sub-board, the first interconnect layer, the substrate, the second interconnect layer, and the second sub-board are laminated to obtain a motherboard. An acidic solution is used to etch the metal layer to remove it, thus making the circuit pads and the second interconnect layer more reactive. A first gap is formed between the layers, and a via penetrates the first gap. Then, a conductive material can be placed on the inner wall of the via. The conductive material includes a first conductive part and a second conductive part arranged along the axial direction of the via. A second gap is formed between the first conductive part and the second conductive part, and the second gap is arranged corresponding to the first gap. The second conductive part is located on the side of the circuit pad away from the first circuit layer. The circuit pad and the first circuit layer are both connected to the first conductive part. The circuit pad and the second conductive part are spaced apart, and the motherboard continues to be electroplated through the first conductive part to form a first electroplated layer. The first electroplated layer covers the first conductive part, so the residual stubs formed by the second conductive part can be removed later, thereby removing the residual stubs formed by the second conductive part at the via position and ensuring signal quality.
[0033] The advantages of the printed circuit board provided in this application compared to the prior art can be seen in the description of the advantages of the manufacturing method of the printed circuit board provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a flowchart of a PCB manufacturing method in one embodiment of this application;
[0036] Figure 2 This is a schematic diagram of the substrate structure in one embodiment of this application;
[0037] Figure 3 Yes Figure 2 A schematic diagram of circuit fabrication on the substrate shown.
[0038] Figure 4 Yes Figure 3A schematic diagram showing a first film disposed on the first circuit layer of the substrate;
[0039] Figure 5 Is Figure 4 A schematic diagram showing a metal layer disposed on the surface of the substrate where the circuit pads are away from the dielectric layer.
[0040] Figure 6 It is to remove Figure 5 A schematic diagram of the first membrane shown;
[0041] Figure 7 Is Figure 5 A schematic diagram of the structure of a motherboard is obtained by stacking a first connecting layer and a first sub-board on one side of the substrate, and a second connecting layer and a second sub-board on the other side of the substrate, and pressing the first sub-board, the first connecting layer, the substrate, the second connecting layer and the second sub-board together.
[0042] Figure 8 Is Figure 7 The diagram shows a through hole machined on the motherboard.
[0043] Figure 9 It is to remove Figure 8 A schematic diagram of the metal layers of the motherboard shown;
[0044] Figure 10 Is Figure 9 A schematic diagram showing the conductive material disposed on the inner wall of the via in the motherboard.
[0045] Figure 11 yes Figure 10 A magnified view of a section at point A in the middle;
[0046] Figure 12 Through the first conductive part Figure 10 The diagram shows a motherboard undergoing electroplating to form the first electroplating layer.
[0047] Figure 13 It is to remove Figure 12 A schematic diagram of the second conductive part on the motherboard shown;
[0048] Figure 14 Through the first electroplating layer Figure 13 The diagram shows a motherboard undergoing electroplating to form a second electroplated layer.
[0049] Figure 15 This is a schematic diagram of the motherboard in another embodiment of this application;
[0050] Figure 16 Is Figure 15 The diagram shows a through hole machined on the motherboard.
[0051] Figure 17It is to remove Figure 16 A schematic diagram of the metal layers of the motherboard shown;
[0052] Figure 18 Is Figure 17 A schematic diagram showing the conductive material disposed on the inner wall of the via in the motherboard.
[0053] Figure 19 Through the first conductive part Figure 18 The diagram shows a motherboard undergoing electroplating to form the first electroplating layer.
[0054] Figure 20 It is to remove Figure 19 A schematic diagram of the second conductive part on the motherboard shown;
[0055] Figure 21 Through the first electroplating layer Figure 20 The diagram shown illustrates the electroplating process performed on the motherboard to form a second electroplated layer.
[0056] The markings in the diagram mean:
[0057] 100. Motherboard;
[0058] 10. Substrate;
[0059] 101. First gap; 11. Dielectric layer; 12. Base circuit layer; 121. Circuit pad; 122. Metal layer; 13. First film; 131. Window;
[0060] 20. First Connecting Layer;
[0061] 30. First sub-board;
[0062] 31. First circuit layer; 32. Intermediate board; 33. Insulation layer;
[0063] 40. Second connecting layer;
[0064] 50. Second sub-board;
[0065] 60. Via;
[0066] 70. Conductive materials;
[0067] 701, Second gap; 71, First conductive part; 72, Second conductive part;
[0068] 80. First electroplating layer;
[0069] 90. Second electroplating layer. Detailed Implementation
[0070] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0071] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0072] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0073] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.
[0074] In the process of manufacturing printed circuit boards, vias are usually processed on the printed circuit board, and then an electroplating layer is placed inside the via. The electroplating layer is used to connect with signal lines and conduct electricity. Then, the printed circuit board needs to be back-drilled by mechanical drilling to remove the stubs in the vias, so as to avoid the stubs causing signal reflection, resonance at specific frequencies, and adverse effects on the timing and voltage tolerance of high-speed serial links.
[0075] Due to limitations in the physical structure of the drill bit, the precision limits of drilling depth control, and the influence of factors such as the material of the printed circuit board itself and deformation during processing, conventional mechanical drilling methods for back-drilling printed circuit boards to remove residual through holes cannot completely remove the residual through holes.
[0076] In view of this, this application provides a printed circuit board and a method for manufacturing the same. First, a metal layer is deposited on the surface of the circuit pads of the base circuit layer on a substrate, away from the dielectric layer. The metal layer has a higher reactivity than the circuit pads. Then, a first interconnect layer and a first sub-board are stacked on one side of the substrate, and a second interconnect layer and a second sub-board are stacked on the other side of the substrate. The first interconnect layer is located between the dielectric layer and the first sub-board, and the second interconnect layer is located between the base circuit layer and the second sub-board. The first sub-board includes the first circuit layer. Then, the first sub-board, the first interconnect layer, the substrate, the second interconnect layer, and the second sub-board are laminated to obtain a motherboard. An acidic solution is then used to etch the metal layer to remove it, thus exposing the circuit pads and the second interconnect layer. A first gap is formed between the vias, and the via penetrates the first gap. Then, conductive material can be placed on the inner wall of the via. The conductive material includes a first conductive part and a second conductive part arranged along the axial direction of the via. A second gap is formed between the first conductive part and the second conductive part, and the second gap is arranged corresponding to the first gap. The second conductive part is located on the side of the circuit pad away from the first circuit layer. The circuit pad and the first circuit layer are both connected to the first conductive part. The circuit pad and the second conductive part are spaced apart, and the motherboard continues to be electroplated through the first conductive part to form a first electroplated layer. The first electroplated layer covers the first conductive part, so the residual stubs formed by the second conductive part can be removed later, thereby removing the residual stubs formed by the second conductive part at the via location and ensuring signal quality.
[0077] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.
[0078] Please refer to Figures 1 to 3 In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board, comprising:
[0079] S100: A substrate 10 is provided, the substrate 10 including a dielectric layer 11 and a basic circuit layer 12 stacked together, the basic circuit layer 12 including circuit pads 121.
[0080] The dielectric layer 11 may be made of resin or fiberglass. The base circuit layer 12 may be made of copper, aluminum, or silver. The circuit pad 121 is a part of the base circuit layer 12 and may serve as a signal pad (PAD).
[0081] S200: Please refer to this as well. Figures 4 to 6 A metal layer 122 is disposed on the surface of the circuit pad 121 that is away from the dielectric layer 11. The material of the metal layer 122 is more reactive than the material of the circuit pad 121.
[0082] Among them, a metal layer 122 can be formed on the surface of the circuit pad 121 that is away from the dielectric layer 11 using a mask process.
[0083] The material of the circuit pad 121 can be copper, and the material of the metal layer 122 can be nickel, tin, zinc, lead-tin alloy or tin-bismuth alloy, etc.
[0084] It should be noted that the circuitry on the substrate 10 can be fabricated first, that is, the circuitry can be fabricated on the base circuitry layer 12, and then a metal layer 122 can be deposited on the surface of the circuit pads 121 that is away from the dielectric layer 11. Alternatively, the metal layer 122 can be deposited first, and then the circuitry on the substrate 10 can be fabricated, that is, the circuitry can be fabricated on the base circuitry layer 12 to obtain the circuit pads 121.
[0085] During the circuit fabrication process on the substrate 10, the corresponding pads 121 of other circuit layers can be removed at the same time.
[0086] S300: Please refer to this as well. Figure 7 A first connection layer 20 and a first sub-board 30 are stacked on one side of the substrate 10, and a second connection layer 40 and a second sub-board 50 are stacked on the other side of the substrate 10. The first connection layer 20 is located between the dielectric layer 11 and the first sub-board 30, and the second connection layer 40 is located between the basic circuit layer 12 and the second sub-board 50. The first sub-board 30 includes a first circuit layer 31.
[0087] The system may include one or more of the following components: a first connecting layer 20, a first sub-board 30, a second connecting layer 40, and a second sub-board 50. Both the first sub-board 30 and the second sub-board 50 may be core boards, multilayer boards, or copper foil, etc. The materials of the first connecting layer 20 and the second connecting layer 40 may include resin and fiberglass, for example, the first connecting layer 20 and the second connecting layer 40 may be prepregs. The material of the first circuit layer 31 may be copper, aluminum, or silver, etc. An intermediate board 32 and an insulating layer 33 may also be provided between the first connecting layer 20 and the first sub-board 30.
[0088] S400: Press the first sub-board 30, the first connecting layer 20, the substrate 10, the second connecting layer 40, and the second sub-board 50 together to obtain the motherboard 100.
[0089] The first sub-board 30, the first connecting layer 20, the substrate 10, the second connecting layer 40, and the second sub-board 50 can be pressed together by a press to obtain the mother board 100.
[0090] S500: Please refer to this as well. Figure 8 A via 60 is machined on the motherboard 100. The via 60 penetrates the first daughterboard 30, the first connection layer 20, the dielectric layer 11, the circuit pad 121, the second connection layer 40, and the second daughterboard 50.
[0091] Vias 60 can be machined on the motherboard 100 by machining or laser ablation. The size of the circuit pad 121 can be 16mil-32mil larger than the diameter of the via 60, and 8mil-16mil larger on each side than the hole.
[0092] It should be noted that after the through hole 60 is machined on the motherboard 100, a hole-finishing process can be performed to remove the residual adhesive remaining on the hole wall after drilling, thus completing the adhesive removal process.
[0093] S600: Please refer to this as well. Figure 9 An acidic solution is used to etch the metal layer 122 to remove the metal layer 122 and to form a first gap 101 between the circuit pad 121 and the second interconnect layer 40. The via 60 penetrates the first gap 101.
[0094] The acidic solution can be hydrochloric acid, sulfuric acid, nitric acid, or a mixed acidic solution. A suitable acidic solution can be selected based on the material of the metal layer 122 and the material of the circuit pads 121. The entire substrate 10 can be immersed in the acidic solution to etch and dissolve the metal layer 122.
[0095] For example, the circuit pad 121 is made of copper, the metal layer 122 is made of nickel, and the acidic solution is hydrochloric acid. Since nickel is more reactive than copper, and nickel and copper form a galvanic cell in the hydrochloric acid solution, the dissolution of nickel is further accelerated (copper does not react with the hydrochloric acid solution). Ultrasonic waves or vacuum can be used to further promote the dissolution of nickel. After hydrochloric acid etching, the dissolved metal layer 122 forms an annular cavity structure with a size equal to the thickness of the metal layer 122, i.e., the first gap 101.
[0096] Since the metal layer 122 is only provided on the part of the circuit pad 121 that is away from the dielectric layer 11, after removing the metal layer 122, only a part of the circuit pad 121 and the second connection layer 40 form a first gap 101. This part of the circuit pad 121 does not contact the dielectric layer 11, and the first gap 101 is provided around the via 60.
[0097] It is understandable that since the material of metal layer 122 is more reactive than the material of circuit pad 121, a suitable acidic solution can be selected so that metal layer 122 reacts with the acidic solution while circuit pad 121 does not react with the acidic solution. That is, acidic solution is used to erode metal layer 122 to remove metal layer 122 while ensuring that circuit pad 121 is not eroded by acidic solution.
[0098] It is also understandable that, due to the presence of the first gap 101, the inner wall of the through hole 60 is divided into two unconnected parts.
[0099] It should be noted that when a metal layer 122 is set on the part of the circuit pad 121 that is away from the dielectric layer 11 using a mask process, the size of the first gap 101 of the annular cavity structure formed between the circuit pad 121 and the second connection layer 40 can be more controllable and the operability is better.
[0100] S700: Please refer to this as well. Figure 10 and Figure 11 A conductive material 70 is provided on the inner wall of the via 60. The conductive material 70 includes a first conductive part 71 and a second conductive part 72 arranged along the axial direction of the via 60. A second gap 701 is formed between the first conductive part 71 and the second conductive part 72. The second gap 701 is arranged corresponding to the first gap 101. The second conductive part 72 is located on the side of the circuit pad 121 away from the first circuit layer 31. The circuit pad 121 and the first circuit layer 31 are both connected to the first conductive part 71. The circuit pad 121 and the second conductive part 72 are spaced apart.
[0101] Conductive material 70 can be deposited on the inner wall of the via 60 by chemical deposition. The conductive material 70 can be made of copper, aluminum, or silver, etc. The second gap 701 is connected to the first gap 101.
[0102] It should be noted that, due to the influence of the first gap 101, the hole-forming solution and the copper plating solution have difficulty entering the first gap 101. The exchange between the external hole-forming solution and the copper plating solution and the internal hole-forming solution and the copper plating solution of the first gap 101 is difficult, resulting in the formation of a loop without conductive material 70, namely the second gap 701. The conductive material 70 on the inner wall of the via 60 is discontinuous and is divided into the first conductive part 71 and the second conductive part 72.
[0103] S800: Please refer to this as well. Figure 12 The motherboard 100 is electroplated through the first conductive part 71 to form a first electroplated layer 80, which covers the first conductive part 71.
[0104] The first conductive part 71 can conduct electricity to perform electroplating on the motherboard 100.
[0105] Conductivity can be achieved solely through the first conductive portion 71 for electroplating the motherboard 100, in which case the first electroplating layer 80 only covers the first conductive portion 71. Alternatively, conductivity can be achieved through both the first circuit layer 31 and the first conductive portion 71 for electroplating the motherboard 100, in which case the first electroplating layer 80 covers both the first conductive portion 71 and the first circuit layer 31. The material of the first electroplating layer 80 can be copper, aluminum, or silver, etc. The materials of the base circuit layer 12, the first circuit layer 31, the conductive material 70, and the first electroplating layer 80 can be the same.
[0106] Because the conductive material 70 on the inner wall of the via 60 is discontinuous and divided into a first conductive part 71 and a second conductive part 72, when the motherboard 100 is electroplated, the current in the first conductive part 71 is continuously present throughout the electroplating process, and the first electroplated layer 80 is relatively thick. The second conductive part 72 is spaced apart from the first conductive part 71, and since there is no current present, the first electroplated layer 80 will not be electroplated on it.
[0107] It should be noted that during the actual manufacturing process, when conductive material 70 is deposited on the inner wall of the via 60 by chemical deposition, if conductive material is also deposited on the surface of the motherboard 100 that is in contact with the chemical solution, except for special cases such as gaps where the chemical solution does not flow due to the whole board deposition, the conductive material on the surface of the motherboard 100 near the second conductive part 72 will be connected to the second conductive part 72, so that current exists in the second conductive part 72 during electroplating. At this time, before electroplating the motherboard 100 through the first conductive part 71, the connection between the second conductive part 72 and other conductive materials (such as the conductive material on the surface of the motherboard 100 near the second conductive part 72) can be cut off. For example, laser ablation or mask etching can be used to cut off the connection between the second conductive part 72 and other conductive materials to avoid the existence of current in the second conductive part 72 during electroplating.
[0108] It is understandable that even if, as the electroplating process proceeds, part of the first electroplated layer 80 connects with the second conductive part 72, causing the second conductive part 72 to be connected to current, the electroplated layer on the second conductive part 72 is relatively thin due to the short electroplating time.
[0109] S900: Please refer to this as well. Figure 13 Remove the second conductive part 72.
[0110] The second conductive part 72 can be removed by chemical etching or reverse electroplating, which is convenient and quick. Chemical etching can be a conventional micro-etching pretreatment process or a rapid etching (also known as flash etching) process. For example, when the first circuit layer 31, the second circuit layer, the conductive material 70, and the first electroplating layer 80 are all made of copper, the second conductive part 72 can be removed by micro-etching to reduce copper content.
[0111] It should be noted that since the first electroplating layer 80 covers the first conductive part 71, the sum of the thicknesses of the first electroplating layer 80 and the first conductive part 71 can be 3um-5um. The thickness of the second conductive part 72 is significantly less than 3um-5um. Therefore, after removing the second conductive part 72 by chemical etching or reverse electroplating, it is also possible to retain part of the first electroplating layer 80 covering the first conductive part 71, or retain all of the first conductive part 71, or retain part of the first conductive part 71.
[0112] It is understandable that when electroplating the motherboard 100, even if part of the first electroplated layer 80 connects with the second conductive part 72 during the electroplating process, causing the second conductive part 72 to be connected to current, the electroplating time is short and the electroplated layer on the second conductive part 72 is thin (significantly less than 3um-5um). Therefore, it can be ensured that after the second conductive part 72 is removed by chemical etching or reverse electroplating, part of the first electroplated layer 80 covering the first conductive part 71 is retained, or all of the first conductive part 71 is retained, or part of the first conductive part 71 is retained.
[0113] As can be seen from the above, the method for manufacturing a printed circuit board provided in this application involves first depositing a metal layer 122 on the surface of the circuit pads 121 of the basic circuit layer 12 on the substrate 10 that faces away from the dielectric layer 11. The metal layer 122 has a higher reactivity than the circuit pads 121. Then, a first connection layer 20 and a first sub-board 30 are stacked on one side of the substrate 10, and a second connection layer 40 and a second sub-board 50 are stacked on the other side of the substrate 10. The first connection layer 20 is located between the dielectric layer 11 and the first sub-board 30, and the second connection layer 40 is located between the basic circuit layer 12 and the second sub-board 50. The first sub-board 30 includes a first circuit layer 31. Then, the first sub-board 30, the first connection layer 20, the substrate 10, the second connection layer 40, and the second sub-board 50 are laminated to obtain a motherboard 100. An acidic solution is then used to etch the metal layer 122 to remove it, thereby creating a gap between the circuit pads 121 and the second connection layer 40. A first gap 101 is formed, and a via 60 penetrates the first gap 101. Then, a conductive material 70 can be provided on the inner wall of the via 60. The conductive material 70 includes a first conductive part 71 and a second conductive part 72 arranged along the axial direction of the via 60. A second gap 701 is formed between the first conductive part 71 and the second conductive part 72. The second gap 701 is arranged corresponding to the first gap 101. The second conductive part 72 is located on the side of the circuit pad 121 away from the first circuit layer 31. The circuit pad 121 and the first circuit layer 31 are both connected to the first conductive part 71. The circuit pad 121 and the second conductive part 72 are spaced apart. The motherboard 100 continues to be electroplated through the first conductive part 71 to form a first electroplated layer 80. The first electroplated layer 80 covers the first conductive part 71. Therefore, the residual stubs formed by the second conductive part 72 can be removed later, thereby removing the residual stubs formed by the second conductive part 72 at the position of the via 60, achieving the purpose of zero residual stubs and ensuring signal quality.
[0114] The printed circuit board manufacturing method provided in this application embodiment sets a metal layer 122 and processes vias 60 on the motherboard 100 before removing the metal layer 122, forming a first gap 101 of an annular cavity structure inside the motherboard 100. This makes it difficult for conductive material 70 to grow at the position of the first gap 101, and finally achieves the purpose of selective electroplating when electroplating the motherboard 100 through the first conductive part 71. Compared with the traditional mechanical back drilling process, it can produce a zero-residue structure.
[0115] Optionally, the acidic solution may be a hydrochloric acid solution, a sulfuric acid solution, a nitric acid solution, or a mixed acidic solution.
[0116] With this setup, an acidic solution can be used to etch the metal layer 122 to remove it.
[0117] Optionally, the circuit pad 121 is made of copper, and the metal layer 122 is made of nickel, tin, zinc, lead-tin alloy or tin-bismuth alloy.
[0118] This configuration allows the material of the metal layer 122 to be more reactive than the material of the circuit pad 121, making it easier to use an acidic solution to etch the metal layer 122 and remove it.
[0119] Alternatively, the second conductive part 72 may be removed by chemical etching or reverse electroplating.
[0120] This configuration makes it easier to remove the second conductive part 72.
[0121] Please refer to Figures 4 to 6 In some embodiments, a metal layer 122 is formed on a portion of the surface of the circuit pad 121 facing away from the dielectric layer 11, including:
[0122] First, a first film 13 is disposed on the surface of the circuit pad 121 away from the dielectric layer 11. The first film 13 has a window 131 that exposes part of the circuit pad 121.
[0123] The first film 13 can be a dry film or a wet film. The first film 13 can be deposited on the surface of the circuit pad 121 opposite to the dielectric layer 11 by means of film application, exposure, and development. The size of the window 131 is smaller than the size of the circuit pad 121 but larger than the diameter of the via 60. For example, the size of the window 131 is 6mil-20mil larger than the diameter D of the via 60, and 3mil-10mil larger on one side than the diameter D of the via 60.
[0124] Secondly, a metal layer 122 is provided on the surface of the line pad 121 exposed by the window 131.
[0125] A metal layer 122 can be deposited on the surface of the circuit pad 121 exposed by the window 131 by chemical deposition or electroplating.
[0126] Next, remove the first membrane 13.
[0127] The first membrane 13 can be removed using a stripping solution.
[0128] By adopting the above solution, a metal layer 122 can be deposited on the surface of the circuit pad 121 that is away from the dielectric layer 11, while avoiding the metal layer 122 covering other parts of the circuit pad 121.
[0129] Optionally, after the metal layer 122 is formed on the surface of the circuit pad 121 facing away from the dielectric layer 11, and before the first interconnect layer 20 and the first sub-board 30 are sequentially stacked on one side of the substrate 10, the method for manufacturing the printed circuit board further includes:
[0130] First, a second film is formed on the substrate 10, and the second film covers the metal layer 122.
[0131] The second film can be a PET (Polyethylene terephthalate) film or tape, etc.
[0132] Next, the substrate 10 is subjected to a browning treatment.
[0133] The substrate 10 can be browned using a browning solution.
[0134] Next, remove the second membrane.
[0135] The second membrane can be removed by machine or manually.
[0136] By adopting the above solution, the browning solution can be avoided from affecting the metal layer 122 during the browning process of the substrate 10.
[0137] Please refer to Figure 13 and Figure 14 In some embodiments, after removing the second conductive portion 72, the method of manufacturing the printed circuit board further includes:
[0138] The motherboard 100 is electroplated by the first electroplating layer 80 to form the second electroplating layer 90, which covers the first electroplating layer 80.
[0139] By adopting the above scheme, the conductive material 70, the first electroplated layer 80, and the second electroplated layer 90 can meet the conductivity requirements.
[0140] It should be noted that the material of the second electroplating layer 90 can be copper, aluminum, or silver, etc.
[0141] Optionally, after electroplating the motherboard 100 with the first electroplating layer 80 to form the second electroplating layer 90, resin is filled into the through hole 60 and the resin is cured, with part of the resin filling the first gap 101.
[0142] This configuration allows the first gap 101 to be filled with resin, ensuring that the rigidity of the motherboard 100 at the first gap 101 is within the acceptable range of quality standards.
[0143] Please refer to Figures 15 to 21 In some embodiments, two copies each of the substrate 10, the first connecting layer 20, the first sub-board 30, and the second connecting layer 40 are provided; the first connecting layer 20 and the first sub-board 30 are stacked on one side of the substrate 10, and the second connecting layer 40 and the second sub-board 50 are stacked sequentially on the other side of the substrate 10, including:
[0144] A first connecting layer 20 and a first sub-board 30 are stacked on one side of one substrate 10, and a second connecting layer 40 and a second sub-board 50 are stacked on the other side of the same substrate 10. Another first connecting layer 20 and another first sub-board 30 are stacked on one side of another substrate 10, and another second connecting layer 40 is stacked on the other side of another substrate 10. The second sub-board 50 is located between the two second connecting layers 40.
[0145] By adopting the above solution, the residual stub formed by the second conductive part 72 can be removed, thereby removing the residual stub formed by the second conductive part 72 at the middle position of the via 60 and ensuring signal quality.
[0146] Secondly, embodiments of this application provide a printed circuit board, which is manufactured by the printed circuit board manufacturing method of the first aspect.
[0147] The printed circuit board provided in this application embodiment is manufactured by first depositing a metal layer 122 on the surface of the circuit pads 121 of the base circuit layer 12 on the substrate 10 away from the dielectric layer 11. The metal layer 122 has a higher reactivity than the circuit pads 121. Then, a first connection layer 20 and a first sub-board 30 are stacked on one side of the substrate 10, and a second connection layer 40 and a second sub-board 50 are stacked on the other side of the substrate 10. The first connection layer 20 is located between the dielectric layer 11 and the first sub-board 30, and the second connection layer 40 is located between the base circuit layer 12 and the second sub-board 50. The first sub-board 30 includes a first circuit layer 31. Then, the first sub-board 30, the first connection layer 20, the substrate 10, the second connection layer 40, and the second sub-board 50 are laminated to obtain a motherboard 100. An acidic solution is used to etch the metal layer 122 to remove the metal layer 122 and to form a gap between the circuit pads 121 and the second connection layer 40. A first gap 101 is formed, and a via 60 penetrates the first gap 101. Then, a conductive material 70 can be provided on the inner wall of the via 60. The conductive material 70 includes a first conductive part 71 and a second conductive part 72 arranged along the axial direction of the via 60. A second gap 701 is formed between the first conductive part 71 and the second conductive part 72. The second gap 701 is arranged corresponding to the first gap 101. The second conductive part 72 is located on the side of the circuit pad 121 away from the first circuit layer 31. The circuit pad 121 and the first circuit layer 31 are both connected to the first conductive part 71. The circuit pad 121 and the second conductive part 72 are spaced apart. The motherboard 100 continues to be electroplated through the first conductive part 71 to form a first electroplated layer 80. The first electroplated layer 80 covers the first conductive part 71. Therefore, the residual stud formed by the second conductive part 72 can be removed later, thereby removing the residual stud formed by the second conductive part 72 at the position of the via 60 and ensuring signal quality.
[0148] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method of manufacturing a printed circuit board, characterized by, include: A substrate is provided, the substrate comprising a dielectric layer and a basic circuit layer stacked thereon, the basic circuit layer comprising circuit pads; A metal layer is disposed on the surface of the circuit pads away from the dielectric layer, wherein the material of the metal layer is more reactive than the material of the circuit pads. A first connection layer and a first sub-board are stacked on one side of the substrate, and a second connection layer and a second sub-board are stacked on the other side of the substrate. The first connection layer is located between the dielectric layer and the first sub-board, and the second connection layer is located between the basic circuit layer and the second sub-board. The first sub-board includes a first circuit layer. The first sub-board, the first connecting layer, the substrate, the second connecting layer, and the second sub-board are pressed together to obtain the mother board; Vias are machined on the motherboard, and the vias penetrate the first daughterboard, the first connection layer, the dielectric layer, the circuit pads, the second connection layer, and the second daughterboard. The metal layer is etched using an acidic solution to remove it and create a first gap between the circuit pads and the second interconnect layer, with the via penetrating the first gap. A conductive material is disposed on the inner wall of the via. The conductive material includes a first conductive part and a second conductive part disposed along the axial direction of the via. A second gap is formed between the first conductive part and the second conductive part. The second gap is disposed corresponding to the first gap. The second conductive part is located on the side of the circuit pad away from the first circuit layer. The circuit pad and the first circuit layer are both connected to the first conductive part. The circuit pad and the second conductive part are spaced apart. The motherboard is electroplated through the first conductive part to form a first electroplating layer, and the first electroplating layer covers the first conductive part. Remove the second conductive part.
2. The method of manufacturing a printed circuit board according to claim 1, wherein The acidic solution is a hydrochloric acid solution, a sulfuric acid solution, a nitric acid solution, or a mixed acidic solution.
3. The method of manufacturing a printed circuit board according to claim 1, wherein The circuit pads are made of copper, and the metal layer is made of nickel, tin, zinc, lead-tin alloy, or tin-bismuth alloy.
4. The method of manufacturing a printed circuit board according to claim 1, wherein The second conductive part is removed by chemical etching or reverse electroplating.
5. The method of claim 1, wherein The provision of a metal layer on the surface of the circuit pads opposite to the dielectric layer includes: A first film is disposed on the surface of the circuit pads away from the dielectric layer. The first film has a window that exposes a portion of the circuit pads. The metal layer is disposed on the surface of the circuit pads exposed by the window; Remove the first membrane.
6. The method of manufacturing a printed circuit board of claim 1, wherein, After the metal layer is deposited on the surface of the circuit pads opposite to the dielectric layer, and before the first interconnect layer and the first sub-board are sequentially stacked on one side of the substrate, the method for manufacturing the printed circuit board further includes: A second film is disposed on the substrate, the second film covering the metal layer; The substrate is subjected to a browning treatment; Remove the second membrane.
7. The method for manufacturing a printed circuit board according to any one of claims 1 to 6, characterized in that, After removing the second conductive portion, the method for manufacturing the printed circuit board further includes: The motherboard is electroplated using the first electroplating layer to form a second electroplating layer, which covers the first electroplating layer.
8. The method of manufacturing a printed circuit board according to claim 7, wherein After electroplating the motherboard through the first electroplating layer to form the second electroplating layer, resin is filled into the through hole and the resin is cured, with a portion of the resin filling the first gap.
9. The method of manufacturing a printed circuit board according to any one of claims 1 to 6, wherein The substrate, the first connecting layer, the first sub-board, and the second connecting layer are all provided in duplicate; the step of stacking the first connecting layer and the first sub-board on one side of the substrate, and sequentially stacking the second connecting layer and the second sub-board on the other side of the substrate, includes: One of the first connecting layers and one of the first sub-boards are stacked on one side of one of the substrates, and one of the second connecting layers and the second sub-board are stacked on the other side of the current substrate. Another first connecting layer and another first sub-board are stacked on one side of the other substrate, and another second connecting layer is stacked on the other side of the other substrate, with the second sub-board located between the two second connecting layers.
10. A printed circuit board, characterized by The printed circuit board is manufactured by the printed circuit board manufacturing method as described in any one of claims 1 to 9.