IGBT device and method of manufacturing the same

Abstract

This invention discloses an IGBT device with a back-side structure comprising: a first P-type back-injection layer formed over the entire back-side region of the field-stop layer and a second P-type back-injection layer formed over a portion of the back-side region of the field-stop layer. In the region where the second P-type back-injection layer is formed, impurities from the first and second P-type back-injection layers and the field-stop layer overlap to form a collector region with net P-type heavy doping. Outside the second P-type back-injection layer, impurities from the first P-type back-injection layer and the field-stop layer overlap to form a Schottky contact region with net N-type doping. A collector electrode composed of a back-side metal layer is formed on the back side of the collector region and the Schottky contact region. The collector electrode and the collector region form an ohmic contact, and the collector electrode and the Schottky contact region form a Schottky diode. This invention also provides a method for manufacturing the IGBT device. This invention can reduce the positive temperature coefficient of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to an IGBT device. This invention also relates to a method for manufacturing an IGBT device. Background Technology

[0002] Traditional Insulated Gate Bipolar Transistor (IGBT) designs consistently strive to ensure a stable positive temperature coefficient (TTC) for their on-state voltage drop (Vce(on)) to achieve uniform current distribution and thermal stability. However, in specific applications such as parallel current sharing and high-frequency switching, while an excessively strong TTC ensures thermal stability, it can lead to a significant increase in conduction losses at high temperatures and a decrease in system efficiency. Current technology lacks an effective means to actively and precisely control the IGBT TTC to achieve a better balance between thermal stability and high-temperature efficiency.

[0003] like Figure 1 The diagram shown is a cross-sectional view of an existing IGBT device; as shown... Figure 2 The diagram shows a flowchart of an existing IGBT device manufacturing method; the existing IGBT device manufacturing method includes the following back-side processes: Step S101: Complete the front-side process of the IGBT device.

[0004] like Figure 1 As shown, the front structure of the formed IGBT device includes: IGBT devices include an active region and a termination region surrounding the active region.

[0005] The device unit structure is formed in the active region.

[0006] The device unit structure includes: a gate structure 102, a P-type well region 104, and an N+ doped emitter region 105. A carrier storage layer 103 is also formed at the bottom of the P-type well region 104.

[0007] The gate structure 102 is a trench gate, including a gate oxide layer formed on the inner surface of the gate trench and a polysilicon gate filled in the gate trench.

[0008] The top of the emitter region 105 is connected to the emitter, which is composed of the front metal layer 110, through a contact hole 109 passing through the interlayer membrane 108.

[0009] The drift region 101 consists of an epitaxial layer formed on the surface of a semiconductor substrate, such as a silicon substrate. In the termination region, a field oxide layer 106 is also formed on the surface of the epitaxial layer, and the field oxide layer 106 surrounds the periphery of the active region.

[0010] The inner side of the field oxide layer 106 is located in the transition region and has an inclined morphology. The gate-connected polysilicon layer 107 will climb over the inner side of the field oxide layer 106. The polysilicon gate will connect to the gate-connected polysilicon layer 107 and connect to the gate composed of the front metal layer 110 through the contact hole 109 through the interlayer film 108 at the top of the gate-connected polysilicon layer 107.

[0011] A polycrystalline silicon field plate 107a is also formed on top of the field oxide layer 106. A metal field plate composed of a front metal layer 110 is also formed on top of the interlayer film 108.

[0012] Step S102: Thinning the semiconductor substrate, i.e. chip thinning.

[0013] Step S103, field cutoff layer implantation, that is, performing comprehensive N-type heavy doping backside implantation to form a field cutoff layer 111 on the backside of the N-type doped drift region 101.

[0014] Step S104, collector region implantation, that is, to perform full P-type heavy doping backside implantation to form collector region 112 on the backside of field stop layer 111.

[0015] Step S105: Perform annealing activation, that is, activate the impurities in the field stop layer 111 and the collector region 112.

[0016] Step S106: Form a back metal layer 114 and form a collector by the back metal layer 114.

[0017] Figure 1 The positive temperature coefficient of the existing IGBT device shown cannot be adjusted. Summary of the Invention

[0018] The technical problem to be solved by this invention is to provide an IGBT device that can adjust the positive temperature coefficient of the device, particularly reducing the positive temperature coefficient of the device at high temperatures, thereby reducing the conduction loss of the device at high temperatures and improving system efficiency. To this end, this invention also provides a method for manufacturing an IGBT device.

[0019] To solve the above-mentioned technical problems, the IGBT device provided by the present invention has the following back-side structure formed on the back side of the N-type doped drift region: A field cutoff layer consisting of an N-type heavily doped backside implantation layer.

[0020] A first P-type back injection layer is formed over the entire back area of ​​the field stop layer, and a second P-type back injection layer is formed over a portion of the back area of ​​the field stop layer.

[0021] The P-type impurity concentration of the first P-type back-side implantation layer is lower than the N-type impurity concentration of the field stop layer, and the P-type impurity concentration of the second P-type back-side implantation layer is higher than the N-type impurity concentration of the field stop layer.

[0022] In the formation region of the second P-type back implantation layer, the P-type impurities of the first P-type back implantation layer and the second P-type back implantation layer and the N-type impurities of the field stop layer are superimposed to form a collector region with net P-type heavy doping.

[0023] Outside the second P-type back implantation layer, the N-type impurities of the first P-type back implantation layer and the field stop layer overlap to form a Schottky contact region with net N-type doping.

[0024] A collector composed of a back metal layer is formed on the back side of the collector region and the Schottky contact region. The collector and the collector region form an ohmic contact, and the collector and the Schottky contact region form a Schottky diode. The Schottky diode serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT. The larger the area of ​​the Schottky contact region, the lower the positive temperature coefficient of the IGBT.

[0025] A further improvement is that the area of ​​the Schottky contact region is 5% to 50% of the total back surface area of ​​the field stop layer.

[0026] A further improvement is that the Schottky contact regions are arranged in an array on the plane of the current collector region and the Schottky contact region.

[0027] A further improvement is that the array distribution structure of the Schottky contact region includes: A bar array consisting of multiple bars arranged in parallel.

[0028] A square array composed of two-dimensional arrangements in multiple directions.

[0029] A circular array consisting of multiple circles arranged in two dimensions.

[0030] A further improvement is that the implanted ions in the field stop layer include phosphorus or hydrogen.

[0031] When the implanted ion in the field stop layer is phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12cm. -2 ~3e13cm -2 .

[0032] When the injected ion in the field stop layer is hydrogen, the injection includes low-energy injection and high-energy injection with different injection energies, and the number of injections includes multiple times.

[0033] Low-energy injection involves injection energies ranging from 400 keV to 1000 keV and injection doses of 1e13 cm⁻¹. -2 ~5e14cm -2 .

[0034] High-energy injection involves an injection energy of 1 MeV to 2 MeV and an injection dose of 2e12cm. -2 ~5e13cm -2 .

[0035] A further improvement is that the injection energy of the first P-type back-side injection layer is 20keV to 60keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 .

[0036] The second P-type back-side injection layer has an injection energy of 20 keV to 60 keV and an injection dose of 5e12cm. -2 ~3e13cm -2 .

[0037] A further improvement is that the field stop layer, the current collector region, and the Schottky contact region have all undergone annealing activation, including laser annealing or furnace tube annealing.

[0038] A further improvement is that the IGBT device includes an active region and a terminal region surrounding the active region.

[0039] The device unit structure is formed in the active region.

[0040] The device unit structure includes: a gate structure, a P-type well region, and an N+ doped emitter region.

[0041] To solve the above-mentioned technical problems, the manufacturing method of the IGBT device provided by the present invention includes the following back-side process: A comprehensive N-type heavily doped backside implantation is performed to form a field cutoff layer on the back side of the N-type doped drift region.

[0042] A first P-type back-side injection layer is formed by performing a comprehensive first P-type back-side injection on the entire back-side region of the field stop layer, wherein the P-type impurity concentration of the first P-type back-side injection layer is lower than the N-type impurity concentration of the field stop layer.

[0043] Forming a second P-type back-side injection layer includes: Photolithography defines the formation region of the second P-type back implantation layer. Then, second P-type back implantation is performed in the formation region of the second P-type back implantation layer in the back region of the field stop layer to form the second P-type back implantation layer. The P-type impurity concentration of the second P-type back implantation layer is higher than the N-type impurity concentration of the field stop layer. In the formation region of the second P-type back implantation layer, the P-type impurities of the first and second P-type back implantation layers and the N-type impurities of the field stop layer overlap to form a collector region with net P-type heavy doping. Outside the second P-type back implantation layer, the N-type impurities of the first and second P-type back implantation layers overlap to form a Schottky contact region with net N-type doping.

[0044] Perform annealing activation.

[0045] A back metal layer is formed and the back metal layer constitutes a collector; the collector and the collector region form an ohmic contact and the collector and the Schottky contact region form a Schottky diode, the Schottky diode serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT, and the larger the area ratio of the Schottky contact region, the lower the positive temperature coefficient of the IGBT.

[0046] A further improvement is that the steps of forming the first P-type back injection layer and forming the second P-type back injection layer are interchangeable in terms of process.

[0047] A further improvement is that the area of ​​the Schottky contact region is 5% to 50% of the total back surface area of ​​the field stop layer.

[0048] A further improvement is that the Schottky contact regions are arranged in an array on the plane of the current collector region and the Schottky contact region.

[0049] A further improvement is that the array distribution structure of the Schottky contact region includes: A bar array consisting of multiple bars arranged in parallel.

[0050] A square array composed of two-dimensional arrangements in multiple directions.

[0051] A circular array consisting of multiple circles arranged in two dimensions.

[0052] A further improvement is that the implanted ions in the field stop layer include phosphorus or hydrogen.

[0053] When the implanted ion in the field stop layer is phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12cm. -2 ~3e13cm -2 .

[0054] When the injected ion in the field stop layer is hydrogen, the injection includes low-energy injection and high-energy injection with different injection energies, and the number of injections includes multiple times.

[0055] Low-energy injection involves injection energies ranging from 400 keV to 1000 keV and injection doses of 1e13 cm⁻¹. -2 ~5e14cm -2 .

[0056] High-energy injection involves an injection energy of 1 MeV to 2 MeV and an injection dose of 2e12cm. -2 ~5e13cm -2 .

[0057] A further improvement is that the injection energy of the first P-type back-side injection layer is 20keV to 60keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 .

[0058] The second P-type back-side injection layer has an injection energy of 20 keV to 60 keV and an injection dose of 5e12cm. -2 ~3e13cm -2 .

[0059] A further improvement is that the annealing includes laser annealing or furnace tube annealing.

[0060] A further improvement is that the front-side process of the IGBT device is completed before the back-side process is performed.

[0061] The IGBT device includes an active region and a terminal region surrounding the active region.

[0062] The front-side process includes forming the device cell structure of the IGBT device, the device cell structure being formed in the active region; the device cell structure includes: a gate structure, a P-type well region, and an N+ doped emitter region.

[0063] The drift region comprises an epitaxial layer formed on the front side of the semiconductor substrate, and further includes the following before back-side implantation of the field stop layer: The semiconductor substrate is thinned.

[0064] This invention divides the P-type back-side implantation layer into two layers. The first P-type back-side implantation layer is formed over the entire back-side region of the field-stop layer, while the heavily doped second P-type back-side implantation layer is located only in a portion of the back-side region of the field-stop layer. That is, the second P-type back-side implantation layer has a patterned structure. This results in a collector region with net P-type heavy doping only forming in the region containing the second P-type back-side implantation layer. Outside the region containing the second P-type back-side implantation layer, the first P-type back-side implantation layer only partially compensates for the N-type heavy doping impurities in the field-stop layer, thus forming a Schottky contact region with net N-type doping. This Schottky contact region, together with the back metal layer (collector), forms a Schottky diode. By utilizing the characteristic that the potential barrier of a Schottky diode decreases with increasing temperature, the current passing through the Schottky diode is further connected in parallel to the conduction current of the IGBT device at high temperatures. Furthermore, by leveraging the characteristic that the potential barrier of the Schottky diode decreases with increasing temperature, the magnitude of the current provided by the Schottky diode at high temperatures is increased. Since the current provided by the Schottky diode has a negative temperature coefficient, it can reduce the positive temperature coefficient of the IGBT, thereby achieving adjustment of the IGBT's positive temperature coefficient. Therefore, this invention can adjust the positive temperature coefficient of the device, especially reducing it at high temperatures, thereby reducing the device's conduction losses at high temperatures and improving system efficiency. Attached Figure Description

[0065] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the cross-sectional structure of an existing IGBT device; Figure 2 This is a flowchart of the existing manufacturing method for IGBT devices; Figure 3 This is a cross-sectional structural diagram of the IGBT device according to an embodiment of the present invention; Figure 4A This is the first layout of the collector region of the IGBT device according to an embodiment of the present invention; Figure 4B This is a second layout of the collector region of the IGBT device according to an embodiment of the present invention; Figure 4C This is a third layout of the collector region of the IGBT device according to an embodiment of the present invention; Figure 5 This is a flowchart of the manufacturing method of the IGBT device according to the first embodiment of the present invention; Figure 6 This is a flowchart of the manufacturing method of the IGBT device according to the second embodiment of the present invention. Detailed Implementation

[0066] like Figure 3The diagram shown is a cross-sectional view of an IGBT device according to an embodiment of the present invention. In the IGBT device of this embodiment, the following back-side structure is formed on the back side of the N-type doped drift region 201: 211 is a field cutoff layer composed of an N-type heavily doped backside implantation layer.

[0067] A first P-type back injection layer is formed in the entire back region of the field stop layer 211, and a second P-type back injection layer is formed in a portion of the back region of the field stop layer 211.

[0068] The P-type impurity concentration of the first P-type back-side implantation layer is lower than the N-type impurity concentration of the field stop layer 211, and the P-type impurity concentration of the second P-type back-side implantation layer is higher than the N-type impurity concentration of the field stop layer 211.

[0069] In the formation region of the second P-type back implantation layer, the P-type impurities of the first P-type back implantation layer and the second P-type back implantation layer and the N-type impurities of the field stop layer 211 are superimposed to form a collector region 212 with net P-type heavy doping.

[0070] Outside the second P-type back implantation layer, the N-type impurities of the first P-type back implantation layer and the field stop layer 211 are superimposed to form a Schottky contact region 213 with net N-type doping.

[0071] A collector composed of a back metal layer 214 is formed on the back side of the collector region 212 and the Schottky contact region 213. The collector and the collector region 212 form an ohmic contact, and the collector and the Schottky contact region 213 form a Schottky diode 215. The Schottky diode 215 serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT. The larger the area ratio of the Schottky contact region 213, the lower the positive temperature coefficient of the IGBT.

[0072] In this embodiment of the invention, the back metal layer 214 is typically composed of aluminum, titanium, nickel, and silver in different thicknesses.

[0073] In this embodiment of the invention, the area of ​​the Schottky contact region 213 is 5% to 50% of the back surface area of ​​the entire field stop layer 211.

[0074] In this embodiment of the invention, the Schottky contact regions 213 are arranged in an array on the plane of the collector region 212 and the Schottky contact region 213.

[0075] The array distribution structure of the Schottky contact region 213 includes: A bar array consisting of multiple bars arranged in parallel. For example... Figure 4AThe diagram shows a first layout 301a of the collector region of an IGBT device according to an embodiment of the present invention. The first layout 301a has multiple parallel strips 302a, and the area where the strips 302a are formed is the area where the Schottky contact region 213 is formed. The area outside the strips 302a is the area where the collector region 212 is formed.

[0076] A square array composed of two-dimensional arrangements in multiple directions. For example... Figure 4B The diagram shows a second layout 301b of the collector region of the IGBT device according to an embodiment of the present invention. The second layout 301b has multiple squares 302b arranged in two dimensions. The area where the squares 302b are formed is the area where the Schottky contact region 213 is formed.

[0077] A circular array composed of multiple circles arranged in a two-dimensional pattern. For example... Figure 4C The diagram shows a third layout 301c of the collector region of the IGBT device according to an embodiment of the present invention. The third layout 301c has multiple two-dimensionally arranged circles 302c, and the area where the circles 302c are formed is the area where the Schottky contact region 213 is formed.

[0078] In this embodiment of the invention, the implanted ions in the field stop layer 211 include phosphorus or hydrogen.

[0079] In some embodiments, when the implanted ion in the field stop layer 211 is phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12cm. -2 ~3e13cm -2 .

[0080] In some embodiments, when the implanted ion in the field stop layer 211 is hydrogen, the implantation includes low-energy implantation and high-energy implantation with different implantation energies, and the number of implantations includes multiple times.

[0081] Low-energy injection involves injection energies ranging from 400 keV to 1000 keV and injection doses of 1e13 cm⁻¹. -2 ~5e14cm -2 .

[0082] High-energy injection involves an injection energy of 1 MeV to 2 MeV and an injection dose of 2e12cm. -2 ~5e13cm -2 .

[0083] In some embodiments, the injection energy of the first P-type backside injection layer is 20 keV to 60 keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 .

[0084] The injection energy for the second P-type back-side injection layer is 20 keV to 60 keV, and the injection dose is 5e12cm.-2 ~3e13cm -2 .

[0085] In this embodiment of the invention, the field stop layer 211, the collector region 212 and the Schottky contact region 213 have all undergone annealing activation, including laser annealing or furnace tube annealing.

[0086] IGBT devices include an active region and a termination region surrounding the active region.

[0087] The device unit structure is formed in the active region.

[0088] The device unit structure includes: a gate structure 202, a P-type well region 204, and an N+ doped emitter region 205. A carrier storage layer 203 is also formed at the bottom of the P-type well region 204.

[0089] In this embodiment of the invention, the gate structure 202 is a trench gate, including a gate oxide layer formed on the inner surface of the gate trench and a polysilicon gate filled in the gate trench.

[0090] The top of the emitter region 205 is connected to the emitter, which is composed of the front metal layer 210, through a contact hole 209 passing through the interlayer membrane 208.

[0091] The drift region 201 consists of an epitaxial layer formed on the surface of a semiconductor substrate, such as a silicon substrate. In the termination region, a field oxide layer 206 is also formed on the surface of the epitaxial layer, and the field oxide layer 206 surrounds the periphery of the active region.

[0092] The inner side of the field oxide layer 206 is located in the transition region and has an inclined morphology. The gate-connected polysilicon layer 207 will climb over the inner side of the field oxide layer 206. The polysilicon gate will connect to the gate-connected polysilicon layer 207 and connect to the gate composed of the front metal layer 210 through the contact hole 209 through the interlayer film 208 at the top of the gate-connected polysilicon layer 207.

[0093] In some embodiments, a polycrystalline silicon field plate 207a is also formed on top of the field oxide layer 206. A metal field plate composed of a front metal layer 210 is also formed on top of the interlayer film 208.

[0094] In this embodiment of the invention, the P-type back-side implantation layer is divided into two layers. The first P-type back-side implantation layer is formed over the entire back-side region of the field stop layer 211, while the heavily doped second P-type back-side implantation layer is located only in a portion of the back-side region of the field stop layer 211. That is, the second P-type back-side implantation layer has a patterned structure. This results in the formation of a collector region 212 with net P-type heavy doping only in the region containing the second P-type back-side implantation layer. In the region outside the second P-type back-side implantation layer, the first P-type back-side implantation layer only partially compensates for the N-type heavy doping impurities in the field stop layer 211, thus forming a Schottky contact region 213 with net N-type doping. The Schottky contact region 213 will interact with the back metal layer 214, i.e., the collector region... The electrode forms a Schottky diode 215. Utilizing the characteristic that the barrier of the Schottky diode 215 decreases with increasing temperature, the current passing through the Schottky diode 215 is further connected in parallel to the on-current of the IGBT device at high temperatures. Furthermore, by leveraging the characteristic that the barrier of the Schottky diode 215 decreases with increasing temperature, the magnitude of the current provided by the Schottky diode 215 at high temperatures is increased. The current provided by the Schottky diode 215 has a negative temperature coefficient, thus reducing the positive temperature coefficient of the IGBT. Therefore, this embodiment of the invention can reduce the positive temperature coefficient of the device, especially at high temperatures, thereby reducing the conduction loss of the device at high temperatures and improving system efficiency.

[0095] like Figure 5 The diagram shown is a flowchart of a manufacturing method for an IGBT device according to a first embodiment of the present invention; the manufacturing method for an IGBT device according to a first embodiment of the present invention includes the following back-side process: Step S101: Complete the front-side process of the IGBT device.

[0096] like Figure 3 As shown, the front structure of the formed IGBT device includes: IGBT devices include an active region and a termination region surrounding the active region.

[0097] The device unit structure is formed in the active region.

[0098] The device unit structure includes: a gate structure 202, a P-type well region 204, and an N+ doped emitter region 205. A carrier storage layer 203 is also formed at the bottom of the P-type well region 204.

[0099] In the method of this embodiment of the invention, the gate structure 202 is a trench gate, including a gate oxide layer formed on the inner surface of the gate trench and a polysilicon gate filled in the gate trench.

[0100] The top of the emitter region 205 is connected to the emitter, which is composed of the front metal layer 210, through a contact hole 209 passing through the interlayer membrane 208.

[0101] The drift region 201 consists of an epitaxial layer formed on the surface of a semiconductor substrate, such as a silicon substrate. In the termination region, a field oxide layer 206 is also formed on the surface of the epitaxial layer, and the field oxide layer 206 surrounds the periphery of the active region.

[0102] The inner side of the field oxide layer 206 is located in the transition region and has an inclined morphology. The gate-connected polysilicon layer 207 will climb over the inner side of the field oxide layer 206. The polysilicon gate will connect to the gate-connected polysilicon layer 207 and connect to the gate composed of the front metal layer 210 through the contact hole 209 through the interlayer film 208 at the top of the gate-connected polysilicon layer 207.

[0103] In some embodiments, a polycrystalline silicon field plate 207a is also formed on top of the field oxide layer 206. A metal field plate composed of a front metal layer 210 is also formed on top of the interlayer film 208.

[0104] Step S102: Thinning the semiconductor substrate, i.e. chip thinning.

[0105] Step S103: Perform comprehensive N-type heavy doping backside implantation to form a field stop layer 211 on the backside of the N-type doped drift region 201.

[0106] In the method of this embodiment of the invention, the implanted ions of the field stop layer 211 include phosphorus or hydrogen.

[0107] In some embodiments, when the implanted ions in the field stop layer 211 are phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12cm. -2 ~3e13cm -2 .

[0108] In some embodiments, when the implanted ion in the field stop layer 211 is hydrogen, the implantation includes low-energy implantation and high-energy implantation with different implantation energies, and the number of implantations includes multiple times.

[0109] Low-energy injection involves injection energies ranging from 400 keV to 1000 keV and injection doses of 1e13 cm⁻¹. -2 ~5e14cm -2 .

[0110] High-energy injection involves an injection energy of 1 MeV to 2 MeV and an injection dose of 2e12cm. -2 ~5e13cm -2 .

[0111] Next, several steps are performed in dashed box 401, including: Step S201: Perform a comprehensive first P-type back-side injection to form a first P-type back-side injection layer in the entire back-side region of the field stop layer 211. The P-type impurity concentration of the first P-type back-side injection layer is lower than the N-type impurity concentration of the field stop layer 211.

[0112] In some embodiments, the injection energy of the first P-type back-side injection layer is 20 keV to 60 keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 .

[0113] Forming a second P-type back-side injection layer includes: Step S202: Photolithography defines the formation area of ​​the second P-type backside implantation layer, that is, photolithography of the second P-type backside implantation layer is performed. Photolithography will form a photoresist pattern to define the formation area of ​​the second P-type backside implantation layer.

[0114] Step S203: Perform second P-type back implantation. A second P-type back implantation layer is formed in the back region of the field stop layer 211. The P-type impurity concentration of the second P-type back implantation layer is higher than the N-type impurity concentration of the field stop layer 211. In the formation region of the second P-type back implantation layer, the P-type impurities of the first P-type back implantation layer and the second P-type back implantation layer and the N-type impurities of the field stop layer 211 are superimposed to form a collector region 212 with net P-type heavy doping. Outside the second P-type back implantation layer, the N-type impurities of the first P-type back implantation layer and the field stop layer 211 are superimposed to form a Schottky contact region 213 with net N-type doping.

[0115] In some embodiments, the injection energy of the second P-type back-side injection layer is 20 keV to 60 keV, and the injection dose is 5e12cm. -2 ~3e13cm -2 .

[0116] In the method of this embodiment, the area of ​​the Schottky contact region 213 is 5% to 50% of the back surface area of ​​the entire field stop layer 211.

[0117] On the plane of collector region 212 and Schottky contact region 213, the Schottky contact region 213 is arranged in an array.

[0118] The array distribution structure of the Schottky contact region 213 includes: A bar array consisting of multiple bars arranged in parallel. For example... Figure 4AThe diagram shows a first layout 301a of the collector region of an IGBT device according to an embodiment of the present invention. The first layout 301a has multiple parallel strips 302a, and the forming area of ​​the strips 302a is the forming area of ​​the Schottky contact region 213. The area outside the strips 302a is the forming area of ​​the collector region 212. At this time, the photolithography in step S202 uses a... Figure 4A The photomask of the pattern can be defined, and the resulting photoresist pattern will cover the area of ​​strip 302a and open the area outside strip 302a.

[0119] A square array composed of two-dimensional arrangements in multiple directions. For example... Figure 4B The diagram shows a second layout 301b of the collector region of the IGBT device according to an embodiment of the present invention. The second layout 301b has multiple two-dimensionally arranged squares 302b, and the area where the squares 302b are formed is the area where the Schottky contact region 213 is formed. In this case, the photolithography in step S202 uses a... Figure 4B The photomask of the pattern can be defined, and the resulting photoresist pattern will cover the area of ​​strip 302b and open the area outside strip 302b.

[0120] A circular array composed of multiple circles arranged in a two-dimensional pattern. For example... Figure 4C The diagram shows a third layout 301c of the collector region of the IGBT device according to an embodiment of the present invention. The third layout 301c has multiple two-dimensionally arranged circular shapes 302c, and the area where the circular shapes 302c are formed is the area where the Schottky contact region 213 is formed. In this case, the photolithography in step S202 uses a... Figure 4C The photomask of the pattern can be defined, and the resulting photoresist pattern will cover the area of ​​strip 302c and open the area outside strip 302c.

[0121] Step S204: Remove photoresist.

[0122] Then proceed as follows: Step S105: Perform annealing activation.

[0123] In the method of the first embodiment of the present invention, annealing includes laser annealing or furnace tube annealing. That is, in the method of the first embodiment of the present invention, annealing can be either high-efficiency laser annealing or furnace tube annealing with better uniformity. In order to ensure the formation of Schottky contacts, the final effective doping concentration of the silicon surface after annealing must be controlled at a reasonable level, that is, the doping concentration of the silicon surface cannot be increased by an excessively high activation rate.

[0124] Step S106: Form a back metal layer 214 and form a collector by the back metal layer 214; form an ohmic contact between the collector and the collector region 212 and form a Schottky diode 215 between the collector and the Schottky contact region 213. The Schottky diode 215 serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT, and the larger the area ratio of the Schottky contact region 213, the lower the positive temperature coefficient of the IGBT.

[0125] The back metal layer 214 is typically composed of aluminum, titanium, nickel, and silver in different thicknesses.

[0126] and Figure 2 Compared to existing methods and processes, Figure 5 In the corresponding first embodiment of the present invention, only a few steps in the dashed box 401 need to be replaced. Figure 2 Step S104 in the above steps is sufficient.

[0127] like Figure 6 The diagram shown is a flowchart of a manufacturing method for an IGBT device according to a second embodiment of the present invention. The difference between this method and the manufacturing method of an IGBT device according to the first embodiment of the present invention is that the steps of forming the first P-type back-side injection layer and forming the second P-type back-side injection layer are interchangeable in terms of process steps. Specifically, Figure 6 In each step corresponding to the dashed box 402, step S201 is placed after steps S202, S203 and S204.

[0128] Because Schottky junctions possess a unique characteristic of increasing conductivity with rising temperature, this invention utilizes this characteristic by connecting a Schottky junction (i.e., a Schottky diode) in parallel with the IGBT device. This reduces the IGBT's temperature coefficient and effectively adjusts the positive temperature coefficient ratio. Specifically, this invention adjusts the injection area and dose of the IGBT's back-side collector region to achieve different ratios of ohmic and Schottky contacts. By leveraging the increased conductivity of the Schottky junction with rising temperature, the high-temperature coefficient of the IGBT is reduced, thereby lowering conduction losses at high temperatures and improving system efficiency.

[0129] The commonly used field-stop (FS)-IGBT combines the thermal stability of MOSFET structures with the low on-state voltage drop of BJT structures. However, these advantages can only be realized through careful balancing design. The MOSFET portion introduces a positive temperature coefficient of on-state voltage drop, resulting in a uniform current distribution across the power device area, thus achieving thermal stability. If the BJT portion dominates, a negative temperature coefficient of on-state voltage drop occurs, causing current density to increase in the hottest region, forming localized hot spots and potentially damaging the device. One advantage of the FS-IGBT design is the ability to tune the injection efficiency of the vertical PNP emitter via back-side ion implantation. The on-state voltage drop of an IGBT can typically be considered as the sum of three components: 1. Vmosfet; 2. Vdrift; 3. Vpn. Vmosfet refers to the voltage drop of the MOS portion of the IGBT, with a positive temperature coefficient; Vdrift is the voltage drop of the drift region, with a positive temperature coefficient; and Vpn is the voltage drop of the PN junction formed by the back collector / field-stop layer, with a negative temperature coefficient. If the MOS component is significantly reduced due to factors such as an extremely short channel, and the drift region lifetime is very high, then the Vpn component will dominate. This will cause the on-state voltage drop to decrease linearly with temperature, leading to thermal instability and premature failure due to hot spots. Existing conventional IGBTs have a PN junction formed by a heavily doped collector region and a field-stop layer on the back. The injection of holes into the PN junction during conduction is the source of the IGBT's bipolar conductivity and negative temperature coefficient. Its contact with the back metal is an ohmic contact. The embodiments of the present invention are based on the adjustment of the injection dose in the back collector region. By reducing the doping concentration in the collector region, Schottky contacts can be introduced in some back regions, thereby reducing the temperature coefficient of the IGBT while still exhibiting a positive temperature coefficient overall.

[0130] In this invention, by adding photolithography and implantation steps to the collector region after the field stop layer implantation, a design with collector regions of different concentrations in different areas on the back of the IGBT is achieved, thereby achieving the purpose of adjusting the IGBT's high-temperature coefficient. Typically, the implanted ions in the field stop layer can be phosphorus or hydrogen, with phosphorus implantation energy ranging from 200 keV to 1 MeV and an implantation dose of 1e12cm. -2 ~3e13cm -2 The amount varies and is adjusted according to the actual characteristics of the product; the hydrogen injection energy and dosage are generally adjusted according to actual needs, with low-energy injection conditions typically ranging from 400keV to 1000keV, 1e13cm. -2 ~5e14cm -2 High-energy injection conditions are generally 1 MeV to 2 MeV, 5e12cm -2 ~5e13cm -2Depending on actual needs, the depth of the field cutoff layer can be achieved by modifying the number of hydrogen ion implantations, thereby adjusting the characteristics of the IGBT. Collector region implantation is then performed after the field cutoff layer.

[0131] exist Figure 5 In the corresponding first embodiment of the present invention, after the field cutoff layer is implanted, the first implantation of the collector region is performed. At this time, the first implantation of the collector region is a first P-type backside implantation, with an implantation energy of 20-60 keV and a dose of 1e11cm. -2 ~1e13cm -2 Within this range, low-dose implantation needs to be combined with subsequent activation to reduce the surface doping concentration and form a Schottky contact with the back metal. Afterwards, collector region photolithography is performed, followed by a second implantation of the collector region. This second implantation is a second P-type back implantation, using a high concentration of boron ions at an implantation energy of 20–60 keV and a dose of 5e12cm. -2 ~3e13cm -2 High-dose injection is used to form ohmic contacts, after which the photoresist is removed and the back-side process continues.

[0132] exist Figure 6 In the corresponding second embodiment of the present invention, after implantation of the field cutoff layer, photolithography of the collector region is performed. The first implantation of the collector region, i.e., the second P-type backside implantation, is a high-concentration boron ion implantation with an implantation energy of 20keV to 60keV and a dose of 5e12cm. -2 ~3e13cm -2 High-dose implantation is used to form ohmic contacts; then the photoresist is removed; a second implantation is performed on the collector region, which is a first P-type backside implantation, with an implantation energy of 20–60 keV and a dose of 1e11cm. -2 ~1e13cm -2 Within this range, low-dose implantation needs to be combined with subsequent activation to reduce the surface doping concentration and form a Schottky contact with the back metal.

[0133] In this embodiment of the invention, introducing a Schottky contact on the back side of the IGBT has the following advantages: Under normal temperature conditions, when the IGBT is forward biased, the Schottky junction, i.e., the Schottky diode 215, has a certain conduction threshold, and the IGBT's on-state voltage drop is dominated by the conduction of the ohmic contact portion. Under high temperature conditions, when the IGBT is forward biased, the potential barrier of the Schottky junction decreases, the conduction capability increases, and a parallel path is provided for electrons to flow directly from the collector metal into the N-type drift region. This path is a pure majority carrier (electron) current, and its voltage drop has a negative temperature coefficient. As the temperature increases, the shunting effect of this parallel path intensifies, thereby lowering the overall on-state voltage drop of the entire device and making its slope with increasing temperature more gradual, i.e., the positive temperature coefficient is weakened.

[0134] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An IGBT device, characterized by: The following back-side structure is formed on the back side of the N-type doped drift region: A field cutoff layer consisting of an N-type heavily doped backside implantation layer; A first P-type back injection layer formed on the entire back surface region of the field stop layer and a second P-type back injection layer formed on a portion of the back surface region of the field stop layer; The P-type impurity concentration of the first P-type back-side implantation layer is lower than the N-type impurity concentration of the field stop layer, and the P-type impurity concentration of the second P-type back-side implantation layer is higher than the N-type impurity concentration of the field stop layer. In the formation region of the second P-type back implantation layer, the P-type impurities of the first P-type back implantation layer and the second P-type back implantation layer and the N-type impurities of the field stop layer are superimposed to form a collector region with net P-type heavy doping. Outside the second P-type back implantation layer, the N-type impurities of the first P-type back implantation layer and the field stop layer are superimposed to form a Schottky contact region with net N-type doping. A collector composed of a back metal layer is formed on the back side of the collector region and the Schottky contact region. The collector and the collector region form an ohmic contact, and the collector and the Schottky contact region form a Schottky diode. The Schottky diode serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT. The larger the area of ​​the Schottky contact region, the lower the positive temperature coefficient of the IGBT.

2. The IGBT device of claim 1, wherein: The area of ​​the Schottky contact region is 5% to 50% of the total back surface area of ​​the field stop layer.

3. The IGBT device of claim 2, wherein: The Schottky contact regions are arranged in an array on the plane of the current collector region and the Schottky contact region.

4. The IGBT device of claim 3, wherein: The array distribution structure of the Schottky contact region includes: A bar array consisting of multiple bars arranged in parallel; A square array composed of two-dimensional arrangements in multiple directions; A circular array consisting of multiple circles arranged in two dimensions.

5. The IGBT device of claim 1, wherein: The implanted ions in the field stop layer include phosphorus or hydrogen; When the implanted ion in the field stop layer is phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12cm. -2 ~3e13cm -2 ; When the implanted ion in the field stop layer is hydrogen, the implantation includes low-energy implantation and high-energy implantation with different implantation energies, and the number of implantations includes multiple times. The implant energy of the low energy implant is 400 keV to 1000 keV, and the implant dose is 1e13 cm -2 to 5e14 cm -2 ; The injection energy of the high energy injection is 1 MeV ~ 2 MeV, and the injection dose is 2e12cm -2 ~ 5e13cm -2 .

6. The IGBT device of claim 5, wherein: The injection energy of the first P-type back-side injection layer is 20keV to 60keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 ; The second P-type back surface injection layer has an injection energy of 20keV-60keV and an injection dose of 5e12cm -2 -3e13cm -2 .

7. The IGBT device as described in claim 1, characterized in that: The field stop layer, the current collector area, and the Schottky contact area have all undergone annealing activation, including laser annealing or furnace tube annealing.

8. The IGBT device of claim 1, wherein: The IGBT device includes an active region and a terminal region surrounding the active region. The device unit structure is formed in the active region; The device unit structure includes: a gate structure, a P-type well region, and an N+ doped emitter region.

9. A method of manufacturing an IGBT device, characterized by, Including the following back panel finishes: A comprehensive N-type heavily doped backside implantation is performed to form a field cutoff layer on the back side of the N-type doped drift region; A first P-type back-side injection layer is formed by performing a comprehensive first P-type back-side injection on the entire back-side region of the field stop layer, wherein the P-type impurity concentration of the first P-type back-side injection layer is lower than the N-type impurity concentration of the field stop layer. Forming a second P-type back-side injection layer includes: Photolithography defines the formation region of the second P-type back implantation layer. Then, the second P-type back implantation is performed in the formation region of the second P-type back implantation layer in the back region of the field stop layer to form the second P-type back implantation layer. The P-type impurity concentration of the second P-type back implantation layer is higher than the N-type impurity concentration of the field stop layer. In the formation region of the second P-type back implantation layer, the P-type impurities of the first and second P-type back implantation layers and the N-type impurities of the field stop layer overlap to form a collector region with net P-type heavy doping. Outside the second P-type back implantation layer, the N-type impurities of the first and second P-type back implantation layers overlap to form a Schottky contact region with net N-type doping. Perform annealing activation; A back metal layer is formed and the back metal layer constitutes a collector; the collector and the collector region form an ohmic contact and the collector and the Schottky contact region form a Schottky diode, the Schottky diode serves as an adjustment structure to reduce the positive temperature coefficient of the IGBT, and the larger the area ratio of the Schottky contact region, the lower the positive temperature coefficient of the IGBT.

10. The method of manufacturing an IGBT device according to claim 9, wherein: The steps of forming the first P-type back injection layer and forming the second P-type back injection layer are interchangeable in terms of process.

11. The method of manufacturing an IGBT device according to claim 9, wherein: The area of ​​the Schottky contact region is 5% to 50% of the total back surface area of ​​the field stop layer.

12. The method of manufacturing an IGBT device according to claim 11, wherein: The Schottky contact regions are arranged in an array on the plane of the current collector region and the Schottky contact region.

13. The method of manufacturing an IGBT device according to claim 12, wherein: The array distribution structure of the Schottky contact region includes: A bar array consisting of multiple bars arranged in parallel; A square array composed of two-dimensional arrangements in multiple directions; A circular array consisting of multiple circles arranged in two dimensions.

14. The method of manufacturing an IGBT device according to claim 9, wherein: The implanted ions in the field stop layer include phosphorus or hydrogen; When the implanted ions of the field stop layer are phosphorus, the implantation energy is 200 keV to 1 MeV, and the implantation dose is 1e12 cm -2 to 3e13 cm -2 . When the implanted ion in the field stop layer is hydrogen, the implantation includes low-energy implantation and high-energy implantation with different implantation energies, and the number of implantations includes multiple times. Low-energy injection involves injection energies ranging from 400 keV to 1000 keV and injection doses of 1e13 cm⁻¹. -2 ~5e14cm -2 ; High-energy injection involves an injection energy of 1 MeV to 2 MeV and an injection dose of 2e12cm. -2 ~5e13cm -2 .

15. The method of manufacturing an IGBT device according to claim 14, wherein: The injection energy of the first P-type back-side injection layer is 20keV to 60keV, and the injection dose is 1e11cm. -2 ~1e13cm -2 ; The second P-type back surface injection layer has an injection energy of 20keV-60keV and an injection dose of 5e12cm -2 -3e13cm -2 .

16. The method of manufacturing an IGBT device according to claim 9, wherein: The annealing includes laser annealing or furnace tube annealing.

17. The method of manufacturing an IGBT device according to claim 9, wherein: The front-side process of the IGBT device was completed before the back-side process was performed; The IGBT device includes an active region and a terminal region surrounding the active region. The front-side process includes forming the device unit structure of the IGBT device, the device unit structure being formed in the active region; The device unit structure includes: a gate structure, a P-type well region, and an N+ doped emitter region; The drift region comprises an epitaxial layer formed on the front side of the semiconductor substrate, and further includes the following before back-side implantation of the field stop layer: The semiconductor substrate is thinned.

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