一种沟槽型VDMOS器件及其制造方法
By employing a double-step trench structure and a self-aligned body and source region construction process in trench-type VDMOS devices, the problem of reduced gate dielectric layer reliability in medium-voltage VDMOS devices under high-voltage turn-off conditions is solved, achieving synergistic optimization of low on-resistance and high reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG YANHUANG MINXIN TECH CO LTD
- Filing Date
- 2025-12-16
- Publication Date
- 2026-07-17
AI Technical Summary
Existing trench-type VDMOS devices are difficult to optimize for both low on-resistance and high reliability in medium-voltage applications, especially when the gate dielectric layer reliability is prone to deterioration under high-voltage turn-off conditions.
By employing a double-step trench structure and a self-aligned body and source region construction process, the electric field distribution is controlled by constructing a double-step trench that is wider at the top and narrower at the bottom. Combined with a deep P+ body contact wall and self-aligned N+ source region injection, a low-impedance hole discharge channel is formed, which enhances the latch-up suppression capability of the device under avalanche or inductive switching transients.
It achieves synergistic optimization of device conduction performance and reliability without increasing process complexity, improves the long-term reliability of gate oxide, reduces on-resistance, and enhances avalanche tolerance and latch-up suppression capability.
Smart Images
Figure CN121665608B_ABST