Chip, preparation method thereof and electronic equipment

Abstract

The invention provides a chip, a preparation method thereof and electronic equipment. The preparation method of the chip comprises the steps that a low-layer metal layer is formed on the back face of a wafer, the low-layer metal layer comprises a low-layer metal structure, and the low-layer metal structure is electrically connected with a semiconductor device formed on the front face of the wafer; forming a back-end device above the low-layer metal layer; a voltage conversion module is formed at least based on a subsequent device, and the first end of the voltage conversion module is electrically connected with the low-layer metal structure; and a high-layer metal layer is formed above the voltage conversion module, the high-layer metal layer comprises a high-layer metal structure, and the high-layer metal structure is electrically connected with the second end of the voltage conversion module and the low-layer metal structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and more particularly to a chip and its preparation method, and electronic equipment. Background Technology

[0002] With Moore's Law continuously evolving, wafer back-side 3D integration technology has great potential to improve system computing power and integration, as well as enhance the functionality of computing systems, making it an important direction for integrated circuit system integration.

[0003] In related technologies, only the power supply network is implemented on the back side of the wafer, while the voltage conversion module is located at the chip package level or system level. Although this design simplifies the chip structure, the voltage conversion point is far from the internal electrical load of the chip, which causes voltage drop during long-distance transmission of low-voltage power, affecting power supply stability and energy efficiency. Summary of the Invention

[0004] This application provides a chip and its fabrication method, as well as an electronic device, which can effectively reduce the power loss of the chip system's power supply line and improve power supply stability and energy efficiency.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for fabricating a chip, comprising: forming a low-level metal layer on the back side of a wafer, wherein the low-level metal layer includes a low-level metal structure and the low-level metal structure is electrically connected to a semiconductor device formed on the front side of the wafer; forming a back-end device above the low-level metal layer; forming a voltage conversion module based at least on the back-end device, wherein a first terminal of the voltage conversion module is electrically connected to the low-level metal structure; and forming a high-level metal layer above the voltage conversion module, wherein the high-level metal layer includes a high-level metal structure and the high-level metal structure is electrically connected to a second terminal of the voltage conversion module and the low-level metal structure, respectively.

[0007] This application provides a chip fabricated using the method described above, comprising: a low-level metal layer, a voltage conversion module, and a high-level metal layer disposed on the back side of a wafer; wherein the low-level metal layer includes a low-level metal structure, which is electrically connected to a semiconductor device formed on the front side of the wafer; a first terminal of the voltage conversion module is electrically connected to the low-level metal structure; and the high-level metal layer includes a high-level metal structure, which is electrically connected to a second terminal of the voltage conversion module and the low-level metal structure, respectively.

[0008] This application provides an electronic device, including: a circuit board and the aforementioned chip, wherein the chip is disposed on the circuit board.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this application, a low-level metal layer is first formed on the back side of the wafer to connect semiconductor devices on the front side, thereby achieving electrical connection between back-side wiring and front-side logic circuits. Secondly, back-end devices are formed on the low-level metal layer, and a voltage conversion module is constructed in conjunction with these back-end devices. By connecting the first terminal of the voltage conversion module to the low-level metal structure, the voltage conversion module can supply power to the chip's low-voltage operating module. Finally, a high-level metal layer is formed above the voltage conversion module, with part of the high-level metal structure connected to the input terminal of the voltage conversion module and the other part directly connected to the chip's constant-voltage operating module, further realizing power distribution. Thus, on the one hand, by integrating the voltage conversion module on the back side of the wafer, the distance between the voltage conversion module and the electrical load is shortened, reducing voltage drop and energy loss during power transmission and improving power supply stability. On the other hand, by combining the voltage conversion module with the low-level and high-level metal structures, more efficient power management is achieved, thereby improving the overall system efficiency and reliability.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is a schematic flowchart illustrating a chip fabrication method according to an exemplary embodiment;

[0014] Figure 2 This is a circuit diagram of a circuit conversion module in a chip according to an exemplary embodiment;

[0015] Figures 3 to 8 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 1 ;

[0016] Figures 9 to 12 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 2 ;

[0017] Figures 13 to 14 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 3 .

[0018] The reference numerals and names in the figure are as follows:

[0019] 21. First wafer; 22. Semiconductor device; 23. Front metal interconnect layer; 24. Carrier wafer; 25. Lower metal layer; 26. Capacitor; 27. Power switching device; 28. Voltage conversion module; 29. ​​Upper metal layer; 30. Low-voltage operating module; 31. Normal-voltage operating module; 32. Metal structure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] In related technologies, voltage conversion modules are usually set at the package level or system level, resulting in long power supply lines and significant voltage drops and energy losses during power transmission. This phenomenon is particularly noticeable when the chip is operating at low voltage, affecting the power supply efficiency and stability of the system.

[0024] To address the aforementioned problems, this application provides a chip, its fabrication method, and an electronic device. This fabrication method involves forming a back-end device between a lower-layer metal layer and a higher-layer metal layer on the back side of a wafer, and then constructing a voltage conversion module based on this back-end device. This moves the voltage conversion function to a location within the chip closer to the electrical load, significantly reducing power loss and improving power efficiency. Specifically, by embedding the voltage conversion module on the back side of the wafer, with its first end connected to the lower-layer metal structure and its second end connected to the higher-layer metal structure, efficient voltage conversion from the voltage at the higher-layer metal structure (first voltage) to the voltage at the lower-layer metal structure (second voltage) is achieved, simplifying the process flow and improving integration. Here, the first voltage and the second voltage are different; the first voltage can be greater than or less than the second voltage.

[0025] In a first aspect, embodiments of this application provide a method for fabricating a chip. Figure 1This is a schematic flowchart illustrating a chip fabrication method according to an exemplary embodiment, such as... Figure 1 As shown, the chip fabrication method in this application embodiment may include steps 101 to 104.

[0026] Step 101: Form a low-level metal layer on the back side of the wafer.

[0027] In some embodiments, the lower metal layer includes a lower metal structure that is electrically connected to a semiconductor device formed on the front side of a first wafer.

[0028] In some embodiments, the first wafer may refer to a silicon-based wafer used for integrating logic circuits and signal traces. In some embodiments, the front side of the first wafer can be fabricated using FEOL (front-end process) to fabricate semiconductor devices such as transistors.

[0029] In some embodiments, the low-level metal layer may be a film layer formed on the back side of the first wafer using a back-end BEOL (back-end process). In some embodiments, the low-level metal layer may include a low-level metal structure and a dielectric structure. The low-level metal structure may be metal wiring arranged within the low-level metal layer. Electrical connection between the low-level metal structure and semiconductor devices on the front side of the first wafer is achieved through vias or interconnect structures. In one example, the low-level metal structure may include power lines, ground lines, and some local signal lines, which are connected to transistors on the front side of the first wafer via vertical interconnect structures (such as copper pillars), thereby achieving back-end power supply functionality.

[0030] It should be noted that the terms "lower metal layer" and "higher metal layer" used in the embodiments of this application are only relative concepts and do not limit the specific metal layer number or absolute thickness. That is, the "lower metal layer" can also be named "first metal layer," and the "higher metal layer" can also be named "second metal layer." In one embodiment, when the "lower metal layer" and "higher metal layer" are stacked vertically, the layer closer to the device surface is called the lower metal layer, and the layer farther from the device surface and closer to the package surface is called the higher metal layer.

[0031] In one example, the lower metal layer may include metals M0 through M5. The higher metal layers may include metals M6 and above. In another example, the lower metal layer may include metals M0 through M6. The higher metal layers may include metals M7 and above.

[0032] In some embodiments, the dielectric structure may be formed by depositing a dielectric material. The dielectric structure is used to encapsulate the underlying metal structure to electrically isolate the underlying metal structure from other structures.

[0033] In some embodiments, the dielectric material may include: silicon oxide, silicon nitride, silicon carbide, diamond-like carbon, polymer-based low dielectric constant material, porous silica, spin-coated glass, polyimide, benzocyclobutene (BCB), or any combination thereof.

[0034] In some embodiments, the formation of the lower metal layer typically employs processes such as sputtering, chemical vapor deposition (CVD), or electroplating to ensure the uniformity and conductivity of the metal layer. Simultaneously, to achieve reliable connectivity with the front-side devices of the first wafer (i.e., semiconductor devices), via structures need to be designed and fabricated within the lower metal layer, and electrical connections are achieved by filling them with conductive materials (such as copper or aluminum). The lower metal structure effectively reduces the resistance of the power supply path and improves overall power supply efficiency.

[0035] Step 102: Form the back-end device above the lower metal layer.

[0036] In some embodiments, back-end devices can refer to devices fabricated on top of a lower metal layer. Back-end devices may include transistors or other passive / active devices. In some embodiments, back-end devices are primarily used to construct voltage conversion modules and to achieve voltage regulation functions through specific wiring methods.

[0037] In some embodiments, back-end devices may include power switching devices and MIM (metal-insulator-metal) capacitors. In some embodiments, the power switching device can be an electronic component for controlling current switching, typically having low on-resistance and high switching speed. In embodiments of this application, the power switching device is integrated in a BEOL process on the back side of the wafer for constructing a voltage conversion module. In some embodiments, the MIM capacitor is a parallel-plate capacitor with metal electrodes separated by an insulating dielectric layer, exhibiting high capacitance density, stable performance, and low leakage characteristics.

[0038] In some embodiments, the power switching device 27 may include at least one of the following: a metal-oxide-semiconductor field-effect transistor; an insulated-gate bipolar transistor; a silicon carbide metal-oxide-semiconductor field-effect transistor; or a complementary metal-oxide-semiconductor.

[0039] In some embodiments, the fabrication process of back-end devices typically includes steps such as thin-film deposition, photolithography, etching, and doping. These devices can be grown or deposited directly on the underlying metal layer, thereby forming an electrical connection between the devices and the underlying metal structure. Because back-end devices have high integration and are located close to the electrical load, they can achieve more efficient voltage conversion and reduce overall power consumption.

[0040] Step 103: Based at least on downstream devices, form a voltage conversion module.

[0041] In some embodiments, the voltage conversion module may consist of at least back-end devices and is used to implement voltage conversion functions, such as a step-down operation from high voltage to low voltage. In some embodiments, the first terminal (i.e., the output terminal) of the voltage conversion module is typically connected to a lower-layer metal structure in the lower metal layer to provide a stable voltage output to the chip's low-voltage operating module through the lower-layer metal structure. Here, the chip's low-voltage operating module may be a logic circuit composed of semiconductor devices in the chip that operate at low voltage.

[0042] In some embodiments, the voltage conversion module can employ various topologies, such as DC-DC converters, charge pumps, and LDOs (low-dropout linear regulators). The choice of topology depends on application requirements and process conditions. In some embodiments, the construction of the voltage conversion module can be optimized based on the operating voltage range and load characteristics of the chip's low-voltage operating module. For example, in low-voltage operating scenarios, an LDO can be used as the voltage conversion module to achieve high-precision voltage regulation; while in high-frequency or high-current applications, a DC-DC converter may be chosen to improve conversion efficiency and response speed.

[0043] In some embodiments, when the back-end device includes multiple power switching devices, step 101 may include: forming a low-layer metal structure electrically connected to a capacitor in the semiconductor device. Step 103 may include: electrically connecting the low-layer metal structure electrically connected to the capacitor in the semiconductor device to the power switching devices. The capacitor in the semiconductor device and the power switching devices constitute a voltage conversion module.

[0044] Understandably, the lower-layer metal structure is used to connect decoupling capacitors in semiconductor devices (i.e., front-end devices). Simultaneously, the lower-layer metal structure is also electrically connected to power switching devices in back-end devices. This electrical connection allows the power switching devices and capacitors to jointly form a voltage conversion module. In other words, the voltage conversion module consists of multiple power switching devices and decoupling capacitors from the front-end devices, interconnected through the lower-layer metal structure, thereby achieving near-load voltage conversion on the back side of the wafer. Furthermore, this voltage conversion module directly utilizes front-end capacitors, which not only increases chip integration density but also does not increase chip reliability risks.

[0045] In some embodiments, decoupling capacitors are used for local decoupling and voltage regulation, reducing power supply noise and improving power supply stability, and can also be used as intermediate storage nodes for voltage conversion.

[0046] In some embodiments, when the downstream device includes a plurality of power switching devices and at least one capacitor, step 103 may include: electrically connecting the power switching devices and the capacitor to form a voltage conversion module.

[0047] Understandably, there is a logical collaborative relationship between power switching devices and MIM capacitors. Power switching devices control the switching of current paths, while MIM capacitors maintain voltage stability and absorb transient fluctuations. Together, they form the basic unit of the voltage conversion module, significantly reducing power supply path impedance and energy consumption, and improving overall power supply efficiency and system stability.

[0048] In some embodiments, the arrangement of downstream devices includes at least one of the following: multiple power switching devices are located on the same film layer; multiple power switching devices are located on different film layers; power switching devices and capacitors are located on the same film layer; power switching devices and capacitors are located on different film layers.

[0049] In some embodiments, the film layer can refer to a metal or dielectric layer formed on the wafer surface through back-end processes, used to carry circuit elements (such as transistors, capacitors, etc.) and achieve interconnection. Depending on the integration level and process complexity, multiple back-end devices can be laid out on the same film layer to simplify the process flow, or distributed on different film layers to save space, achieving finer functional partitioning and signal isolation. This layout method for power switching devices helps optimize chip layout design and improve the overall integration performance of the chip.

[0050] In some embodiments, placing multiple power switching devices on the same film layer can reduce process costs and is suitable for low-power scenarios; while distributing multiple power switching devices on different film layers helps improve integration efficiency, enables more complex power management functions, and enhances system flexibility and scalability. Similarly, arranging power switching devices and capacitors on the same layer helps reduce parasitic inductance and resistance and improves response speed; while layered arrangement facilitates independent optimization of the performance of power switching devices and capacitors, and is suitable for applications sensitive to electromagnetic interference.

[0051] In some embodiments, by flexibly configuring the layout, higher energy efficiency and lower system latency can be achieved in the voltage conversion module integrated on the back of the chip. This configuration can significantly improve the overall power supply quality of the chip, reduce energy consumption, and simplify subsequent manufacturing processes, thereby improving product yield and reliability.

[0052] In some embodiments, multiple downstream devices located on the same film layer can be arranged arbitrarily.

[0053] In some embodiments, step 103 may include: electrically connecting a first terminal of the voltage conversion module to a lower metal structure, wherein the first terminal of the power switching device may serve as the first terminal of the voltage conversion module.

[0054] In some embodiments, the lower metal structure can be a metal trace within a lower metal layer. The lower metal structure can serve as a bridge between the voltage conversion module and the electrical load. By electrically connecting the first terminal of the voltage conversion module to the lower metal structure, it can be ensured that the converted power can be efficiently transmitted to the low-voltage operating module inside the chip.

[0055] In some embodiments, by using one end of the power switching device as the first end of the voltage conversion module and electrically connecting the first end of the voltage conversion module to the lower metal structure, the parasitic resistance and inductance of the power transmission path can be significantly reduced, thereby achieving efficient power transmission and fast load transient response.

[0056] Step 104: Form a high-layer metal layer above the voltage conversion module.

[0057] In some embodiments, the high-layer metal layer includes a high-layer metal structure. In some embodiments, the high-layer metal layer can also be a film layer formed by a BEOL process. The combined function of the low-layer and high-layer metal layers can be to provide power network support and signal conduction for the semiconductor devices on the front side of the first wafer.

[0058] In some embodiments, the high-layer metal layer may include a high-layer metal structure and a dielectric structure. In some embodiments, the high-layer metal structure is configured similarly to the low-layer metal structure, including power lines, ground lines, and signal lines. In some embodiments, the formation process of the high-layer metal layer may be similar to the formation process of the low-layer metal layer, and this application embodiment does not limit this.

[0059] In some embodiments, a higher metal layer can be formed above the voltage conversion module. This higher metal layer can be used to connect to the second terminal (i.e., the input terminal) of the voltage conversion module, providing power to the module so that after voltage conversion, the module provides a stable voltage to the low-voltage operating module of the chip via the lower metal layer. Simultaneously, the higher metal layer can also be directly connected to the chip's ambient voltage operating module to provide a stable voltage for it. Here, the ambient voltage operating module can be a logic circuit composed of semiconductor devices within the chip that operate at ambient voltage.

[0060] In some embodiments, step 104 may include: electrically connecting the second terminal of the voltage conversion module to the high-layer metal structure, wherein the second terminal of the power switching device may be the second terminal of the voltage conversion module, and the first terminal of the power switching device is different from the second terminal of the power switching device.

[0061] Understandably, the second terminal of a voltage conversion module refers to the port used for input voltage, typically connected to a higher-level metal structure within a higher-level metal layer to receive raw voltage input from that structure or other external power supply networks. Corresponding to the second terminal, the first terminal of the voltage conversion module is the output terminal, connected to a lower-level metal structure within a lower-level metal layer, used to provide a stable, low-loss power supply to that lower-level metal layer.

[0062] In some embodiments, the second terminal of the power switching device can be the second terminal of the voltage conversion module, and the first terminal of the power switching device is different from the second terminal of the power switching device. It is understood that the first and second terminals of the voltage conversion module have different functions; therefore, the first and second terminals of the power switching device are located in different positions, which in turn makes the second terminal of the voltage conversion module located in different positions, allowing it to respectively undertake the input and output functions in the voltage conversion process.

[0063] In some embodiments, by electrically connecting the second terminal of the voltage conversion module to the upper metal structure, the voltage conversion module can be integrated between the upper metal layer and the lower metal layer, thereby achieving near-load power supply.

[0064] In this embodiment, by electrically connecting the second terminal of the voltage conversion module to the high-layer metal structure, the voltage conversion module can be directly connected to the power supply network, thereby optimizing the power supply path, reducing power loss, and thus improving the overall energy efficiency and stability of the chip.

[0065] It should be noted that, Figure 1 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 1 The steps shown can be adjusted in order according to actual needs.

[0066] In this embodiment, a low-level metal layer is first formed on the back side of the wafer to connect semiconductor devices on the front side, thereby achieving electrical connection between back-side wiring and front-side logic circuits. Next, back-end devices are formed on the low-level metal layer, and a voltage conversion module is constructed in conjunction with these back-end devices. By connecting the first terminal of the voltage conversion module to the low-level metal structure, the voltage conversion module can supply power to the chip's low-voltage operating module. Finally, a high-level metal layer is formed above the voltage conversion module, with part of the high-level metal structure connected to the input terminal of the voltage conversion module and the other part directly connected to the chip's constant-voltage operating module, further realizing power distribution. Thus, on the one hand, by integrating the voltage conversion module on the back side of the wafer, the distance between the voltage conversion module and the electrical load is shortened, reducing voltage drop and energy loss during power transmission and improving power supply stability. On the other hand, by combining the voltage conversion module with the low-level and high-level metal structures, more efficient power management is achieved, thereby improving the overall system efficiency and reliability.

[0067] In some embodiments, the chip fabrication method further includes: forming a semiconductor device on the front side of a first wafer; and forming a front-side metal interconnect layer on the semiconductor device.

[0068] In some embodiments, the first wafer front side refers to the original surface of the first wafer that has not been thinned or flipped, and semiconductor devices (such as transistors) and metal interconnect layers (i.e. signal trace networks) can be formed on the first wafer front side.

[0069] In some embodiments, forming a semiconductor device on the front side of a first wafer includes constructing transistors (such as FinFETs, nanosheet field-effect transistors (NSFETs), complementary field-effect transistors (CFETs), and ferroelectric field-effect transistors (FFETs)) and their associated interconnect structures on the first wafer. The transistors and their interconnect structures constitute the logic circuitry of the chip, such as computing units and memory arrays. In some embodiments, the process of forming a semiconductor device on the front side of the first wafer is part of the FEOL process, which typically includes multiple steps such as deposition, etching, ion implantation, and thermal processing.

[0070] In some embodiments, the front-side metal interconnect layer refers to a metal wiring network formed above a manufactured semiconductor device, used to connect electrical signal transmission paths between various transistors and modules. In some embodiments, the front-side metal interconnect layer typically consists of multiple metal layers, each layer being vertically connected through vias and vias, and insulated by a dielectric structure.

[0071] In some embodiments, the formation of the front-side metal interconnect layer is part of the BEOL process, which typically includes steps such as CVD, physical vapor deposition (PVD), photolithography, etching, and chemical mechanical planarization (CMP). The front-side metal interconnect layer not only determines the signal transmission efficiency within the chip but also affects overall power consumption, latency, and reliability.

[0072] In some embodiments, after forming the front metal interconnect layer, the front metal interconnect layer can be bonded to the wafer carrier and flipped, and the semiconductor device on the front side of the wafer can be exposed by thinning the portion on the back side of the wafer. Thus, chip fabrication can be completed through steps 101 to 104.

[0073] The following is a specific example illustrating the chip and its fabrication method in the embodiments of this application.

[0074] Figure 2 This is a circuit diagram illustrating a circuit conversion module in a chip according to an exemplary embodiment. See also... Figure 2 As shown, the circuit structure of the charge pump voltage conversion module may include four switches (referred to as switch SW1, switch SW2, switch SW3 and switch SW4 respectively) and a decoupling capacitor (referred to as C1).

[0075] Figures 3 to 8 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 1 The image shows a cross-sectional view of the chip along the vertical direction (i.e., the three-dimensional stacking direction). See also... Figures 3 to 8 to form Figure 2 Taking the circuit structure shown as an example, the first method of chip fabrication may include the following steps.

[0076] The first step involves fabricating the semiconductor device 22 and the front-side metal interconnect layer 23 on the front side of the first wafer 21, resulting in the following: Figure 3 The structure shown.

[0077] Here, the semiconductor device 22 can form a logic circuit, and the front metal interconnect layer 23 can be the signal trace network of the logic circuit.

[0078] The second step involves bonding the front-side metal interconnect layer 23 to the carrier wafer 24, then flipping the carrier wafer 24. Following this, a thinning process is used to thin the back portion of the first wafer 21 to expose the semiconductor device 22, resulting in the following... Figure 4 The structure shown.

[0079] The third step is to form a low-level metal layer 25 in the power supply network on the back side of the first wafer 21, resulting in the following: Figure 5 The structure shown.

[0080] Here, the lower metal layer 25 can be connected to the capacitor 26 in the semiconductor device 22.

[0081] Step 4: Form back-end devices above the lower metal layer 25 of the first wafer 21, to obtain... Figure 6 The structure shown.

[0082] Here, the downstream devices may include multiple power switching devices 27.

[0083] Step 5: Electrically connect the back-end device to the metal structure 32 in the lower metal layer 25, so that the back-end device is connected to the capacitor 26 in the semiconductor device 22, forming a voltage conversion module 28. Then, connect the metal structures 32 in the lower metal layer 25 at other locations on the first end of the voltage conversion module 28, so that the voltage conversion module 28 supplies power to the low-voltage operating module 30 of the chip through the metal structures 32, obtaining the desired result. Figure 7 The structure shown.

[0084] Here, capacitor 26 in semiconductor device 22 can be used as capacitor 26 in voltage conversion module 28. Metal structure 32 in lower metal layer 25 can be a lower metal structure.

[0085] Step 6: Form a high-layer metal layer 29 above the voltage conversion module 28 to obtain the following... Figure 8 The structure shown.

[0086] Here, the metal structure 32 in the high-layer metal layer 29 is electrically connected to the power switching device 27 at the second terminal of the voltage conversion module 28 and the low-layer metal structure 32 connected to the chip's constant-voltage operating module. It is understood that the constant-voltage operating module 31 can be directly powered by the power supply network, and the low-voltage operating module 30 can be powered by the voltage conversion module 28. The metal structure 32 in the high-layer metal layer 29 can be a high-layer metal structure.

[0087] This completes the chip fabrication process.

[0088] See Figure 7 As shown, capacitor C1 in the circuit structure of the charge pump voltage conversion module is equivalent to Figure 8 Medium capacitor 26. Switches SW1, SW2, SW3, and SW4 are equivalent to Figure 8 Medium-power switching device 27. It can be seen that the chip provided in this embodiment can integrate at least a load-pump voltage conversion module. Of course, other types of voltage conversion modules can also be integrated into the chip provided in this embodiment, and no specific limitation is made. Based on this, the embodiments of this application can be applied to next-generation integrated circuit manufacturing processes and have great application potential.

[0089] In some embodiments, the present application is also applicable to schemes that utilize back-end capacitors to form voltage conversion modules. Figures 9 to 12 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 2 The image shows a cross-sectional view of the chip along the vertical direction (i.e., the three-dimensional stacking direction). See also... Figures 9 to 12 to form Figure 2 Taking the circuit structure shown as an example, the second method for fabricating the chip may include the following steps.

[0090] The first step, similar to steps one through three of the first preparation method, yields the following result: Figure 9 The structure shown.

[0091] The second step involves forming back-end devices above the lower metal layer 25 of the first wafer 21, resulting in... Figure 10 The structure shown.

[0092] Here, the downstream devices may include multiple power switching devices 27 and capacitors 26.

[0093] The third step is to electrically connect the downstream device to the metal structure 32 in the lower metal layer 25, resulting in the following: Figure 11 The structure shown.

[0094] Here, multiple power switching devices 27 and capacitors 26 in the back-end devices can form a voltage conversion module 28. The first end of the voltage conversion module 28 is connected to the metal structure 32 in the lower metal layer 25 to supply power to the low-voltage operating module 30 of the chip.

[0095] Step 4: Form a high-layer metal layer 29 above the voltage conversion module 28 to obtain the following... Figure 12 The structure shown.

[0096] Here, the metal structure 32 in the high-layer metal layer 29 is electrically connected to the power switching device 27 at the second terminal of the voltage conversion module 28 and the metal structure 32 connected to the chip's constant-voltage operating module 31. It is understood that the constant-voltage operating module 31 can be directly powered by the power supply network, and the low-voltage operating module 30 can be powered by the voltage conversion module 28.

[0097] This completes the chip fabrication process.

[0098] In some embodiments, the present application is also applicable to schemes where the capacitor and the power switching device are located on different film layers. Figures 13 to 14 This is a schematic diagram of a chip fabrication process according to an exemplary embodiment. Figure 3 The image shows a cross-sectional view of the chip along the vertical direction (i.e., the three-dimensional stacking direction). See also... Figures 13 to 14 to form Figure 2Taking the circuit structure shown as an example, the third method for fabricating a chip may include the following steps.

[0099] The first step, similar to steps one through four of the second preparation method, yields the following result: Figure 13 The structure shown.

[0100] The second step involves forming a capacitor 26 in a film layer different from that of the power switching device 27, and electrically connecting the power switching device 27 and the capacitor 26 to form a voltage conversion module 28. The first end of the voltage conversion module 28 is then electrically connected to the metal structure 32 in the lower metal layer 25, and a higher metal layer 29 is formed above the voltage conversion module 28, resulting in... Figure 14 The structure shown.

[0101] Here, the metal structure 32 in the high-layer metal layer 29 is electrically connected to the power switching device 27 at the second terminal of the voltage conversion module 28 and the metal structure 32 connected to the chip's constant-voltage operating module 31. It is understood that the constant-voltage operating module 31 can be directly powered by the power supply network, and the low-voltage operating module 30 can be powered by the voltage conversion module 28.

[0102] This completes the chip fabrication process.

[0103] In this embodiment, logic circuits and signal traces are completed on the front side of a silicon wafer. Wafer bonding and flipping operations are then performed, followed by wafer thinning. A low-layer metal structure for the power supply network is formed on the back side of the wafer. Further, a voltage conversion module is constructed in the back-end process. The voltage conversion module is connected to the power rails of the low-voltage operating module via metal traces. Finally, high-layer metal wiring for the power supply network is completed, with a portion connected to the input of the voltage conversion module and another portion directly connected to the chip's constant-voltage operating module. This embodiment reduces the distance between the voltage conversion module and the electrical load to the nanometer scale, effectively reducing power loss in the power supply lines. Simultaneously, by combining with capacitors in semiconductor devices, reliance on back-end capacitors is reduced, simplifying the back-end process and lowering costs.

[0104] Furthermore, this invention can be applied to various variants. For example, it is also applicable when the back side of the wafer contains not only power supply networks but also local signal traces and global clock traces. Additionally, the purpose of this invention can be achieved by using transistor structures suitable for back-side power supply networks, such as FinFET, NSFET, CFET, or FFET.

[0105] Furthermore, the vertical transistors provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM).

[0106] Taking TEM as an example, the embodiments of this application can use TEM slicing to detect the structure of the chip. Figure 8 The TEM slice of the structure shown reveals back-end transistors on the back side of the wafer, which are interconnected to form a charge pump voltage conversion module 28. The charge pump voltage conversion module 28 supplies power to the chip's low-voltage operating module 30 via a back-end power supply network.

[0107] Secondly, embodiments of this application provide a chip. See also... Figures 1 to 14 As shown, the chip can be fabricated using the method described in any of the embodiments of the first aspect. The chip may include: a low-layer metal layer 25, a voltage conversion module 28, and a high-layer metal layer 29 disposed on the back side of the wafer; wherein the low-layer metal layer 25 includes a low-layer metal structure 32 electrically connected to a semiconductor device 22 formed on the front side of the wafer; a first terminal of the voltage conversion module 28 is electrically connected to the low-layer metal structure 32; and the high-layer metal layer 29 includes a high-layer metal structure 32 electrically connected to a second terminal of the voltage conversion module 28 and the low-layer metal structure 32, respectively.

[0108] It is understood that the structure of the chip in the embodiments of this application can be referred to the description in any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0109] In some embodiments, the voltage conversion module 28 includes a plurality of power switching devices 27 and at least one capacitor 26; the capacitor 26 is formed on the front side of the wafer or on the back side of the wafer.

[0110] Understandably, when a capacitor is fabricated on the front side of a wafer, it can be located within the semiconductor device fabricated on the front side. In this case, the capacitor can be a decoupling capacitor. When a capacitor is fabricated on the back side of a wafer, it can be located within the back-end device fabricated on the back side. In this case, the capacitor can be a MIM capacitor.

[0111] In some embodiments, the power switching device 27 includes at least one of the following: a metal-oxide-semiconductor field-effect transistor; an insulated-gate bipolar transistor; a silicon carbide metal-oxide-semiconductor field-effect transistor; or a complementary metal-oxide-semiconductor.

[0112] Thirdly, embodiments of this application provide an electronic device, including: a circuit board and a chip as described in the above embodiments, wherein the chip is disposed on the circuit board.

[0113] In this embodiment of the application, by setting a semiconductor chip with a voltage conversion module 28 integrated on the back of the wafer on the circuit board, the dependence on the voltage conversion module of the circuit board can be reduced, thereby improving the overall system performance and expanding the application scenarios of the chip.

[0114] In summary, through the embodiments of this application, on the one hand, by integrating the voltage conversion module 28 on the back of the wafer, the voltage conversion module 28 is located closer to the electrical load, thereby significantly reducing the energy loss of the power supply line; on the other hand, the implementation of the voltage conversion module is also simpler, which helps to reduce the overall process complexity.

[0115] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a chip, characterized in that, include: A low-level metal layer is formed on the back side of the wafer, wherein the low-level metal layer includes a low-level metal structure, and the low-level metal structure is electrically connected to a semiconductor device formed on the front side of the wafer. Back-end devices are formed above the lower metal layer; A voltage conversion module is formed based at least on the back-end device, wherein a first terminal of the voltage conversion module is electrically connected to the lower metal structure; A high-layer metal layer is formed above the voltage conversion module, wherein the high-layer metal layer includes a high-layer metal structure, and the high-layer metal structure is electrically connected to the second terminal of the voltage conversion module and the low-layer metal structure, respectively.

2. The method according to claim 1, characterized in that, The downstream devices include: multiple power switching devices; The formation of a low-level metal layer on the back side of the wafer includes: A low-layer metal structure is formed that is electrically connected to capacitors in the semiconductor device; The voltage conversion module, formed at least based on the downstream device, includes: A low-level metal structure electrically connected to a capacitor in the semiconductor device is electrically connected to a power switching device, wherein the capacitor and the power switching device constitute the voltage conversion module.

3. The method according to claim 1, characterized in that, The downstream devices include: multiple power switching devices and at least one capacitor; The voltage conversion module, formed at least based on the downstream device, includes: The power switching device is electrically connected to the capacitor to form the voltage conversion module.

4. The method according to claim 3, characterized in that, The positional arrangement of the downstream components includes at least one of the following: Multiple power switches are located in the same membrane layer; The multiple power switches are located in different film layers; The power switching device and the capacitor are located in the same film layer; The power switching device and the capacitor are located in different film layers.

5. The method according to any one of claims 2 to 4, characterized in that, The voltage conversion module, formed at least based on the downstream device, further includes: The first terminal of the voltage conversion module is electrically connected to the lower metal structure, wherein the first terminal of the power switching device is the first terminal of the voltage conversion module.

6. The method according to claim 5, characterized in that, A high-layer metal layer is formed above the voltage conversion module, including: The second terminal of the voltage conversion module is electrically connected to the high-rise metal structure, wherein the second terminal of the power switching device is the second terminal of the voltage conversion module, and the first terminal of the power switching device is different from the second terminal of the power switching device.

7. The method according to claim 1, characterized in that, The method further includes: Semiconductor devices are formed on the front side of the wafer; A front-side metal interconnect layer is formed on the semiconductor device; The front metal interconnect layer is bonded to the carrier wafer and then flipped; The wafer is thinned to expose the semiconductor device.

8. A chip, characterized in that, The wafer is fabricated using the method described in any one of claims 1 to 7, comprising: a low-layer metal layer, a voltage conversion module, and a high-layer metal layer disposed on the back side of the wafer; The lower metal layer includes a lower metal structure, which is electrically connected to a semiconductor device formed on the front side of the wafer. The first terminal of the voltage conversion module is electrically connected to the lower metal structure. The high-level metal layer includes a high-level metal structure, which is electrically connected to the second terminal of the voltage conversion module and the low-level metal structure, respectively.

9. The chip according to claim 8, characterized in that, The voltage conversion module includes: multiple power switching devices and at least one capacitor; The capacitor is formed on the front side of the wafer or on the back side of the wafer.

10. An electronic device, characterized in that, Includes a circuit board and a chip as described in claim 8 or 9.

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