Semiconductor device

Abstract

The present disclosure provides a semiconductor device in which peeling of an insulating film is reduced. The semiconductor device includes: a first metal layer provided on a substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of an upper surface of the first metal layer; a second metal layer provided on the first metal layer, a central portion in a lower surface of the second metal layer being in contact with the first metal layer via the first opening, and a peripheral portion in the lower surface being in contact with the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of an upper surface of the second metal layer; and an organic insulating film covering the second inorganic insulating film, the organic insulating film having a third opening that exposes the central portion in the upper surface of the second metal layer and overlaps the second opening when viewed from the thickness direction of the substrate.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] A technique is known in which an insulating film with an opening that exposes the central portion of the upper surface of the metal layer is provided in a manner that covers a metal layer used as a solder pad, etc. (e.g., Patent Document 1). A silicon nitride film is used as the insulating film.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-56246

[0006] Sometimes, an organic insulating film is disposed on a silicon nitride film having an opening that exposes the central portion of the upper surface of the metal layer, in a manner that does not overlap with the opening. In this case, due to the stress of the organic insulating film, the insulating film will peel off from the metal layer starting from the end of the opening. Summary of the Invention

[0007] The purpose of this disclosure is to provide a semiconductor device that reduces the peeling of the insulating film.

[0008] An embodiment of this disclosure is a semiconductor device comprising: a first metal layer disposed on a substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of an upper surface of the first metal layer; a second metal layer disposed on the first metal layer, wherein a central portion of a lower surface of the second metal layer contacts the first metal layer via the first opening, and a peripheral portion of the lower surface contacts the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of an upper surface of the second metal layer; and an organic insulating film covering the second inorganic insulating film and having a third opening exposing the central portion of the upper surface of the second metal layer and overlapping the second opening when viewed from the thickness direction of the substrate.

[0009] Invention Effects

[0010] According to this disclosure, the peeling of the insulating film can be reduced. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a top view showing the metal layer and openings in the semiconductor device of the first embodiment.

[0013] Figure 3 This is a cross-sectional view of a semiconductor device in a comparative form.

[0014] Figure 4 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0015] Figure 5 This is an enlarged cross-sectional view of the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0019] Figure 9 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0020] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0021] Figure 11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0022] Figure 12 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0023] Figure 13 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0024] Figure 14 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0025] Figure 15 This is a cross-sectional view of a semiconductor device according to a variation of the first embodiment 1.

[0026] Figure 16 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment, Example 1.

[0027] Figure 17 This is a top view of the semiconductor device according to the second embodiment.

[0028] Explanation of reference numerals in the attached figures:

[0029] 10, 10A: substrate;

[0030] 10B: Semiconductor layer;

[0031] 11 (first inorganic insulating film), 12 (second inorganic insulating film), 13 (third inorganic insulating film): Inorganic insulating film;

[0032] 11A (first opening), 12A (second opening), 13A (fourth opening), 14A (third opening), 40A, 42A, 44A, 46A: openings;

[0033] 14: Organic insulating film;

[0034] 15 (third metal layer), 16 (first metal layer), 16A, 16B, 18 (second metal layer), 18A (sealing layer), 18B (low resistance layer): metal layers;

[0035] 15A, 17A, 19A: Top surface;

[0036] 17B, ​​19B: Lower surface;

[0037] 20: Source electrode;

[0038] 21: Drain electrode;

[0039] 22: Gate electrode;

[0040] 23: Source wiring;

[0041] 24S, 24D, 24G: solder pads;

[0042] 25: Via;

[0043] 26: Joint area;

[0044] 40, 42, 44, 46: Mask layers;

[0045] 50: Stress;

[0046] 51, 53: end;

[0047] 52: Wedge;

[0048] 54: Path;

[0049] 100, 102, 104, 110: Semiconductor devices. Detailed Implementation

[0050] [Description of embodiments of this disclosure]

[0051] First, the implementation plan disclosed herein will be listed for illustration.

[0052] (1) An embodiment of this disclosure is a semiconductor device comprising: a first metal layer disposed on a substrate; a first inorganic insulating film covering the first metal layer and having a first opening exposing a central portion of the upper surface of the first metal layer; a second metal layer disposed on the first metal layer, wherein a central portion of the lower surface of the second metal layer contacts the first metal layer via the first opening, and a peripheral portion of the lower surface contacts the first inorganic insulating film outside the first opening; a second inorganic insulating film covering the second metal layer and having a second opening exposing a central portion of the upper surface of the second metal layer; and an organic insulating film covering the second inorganic insulating film and having a third opening exposing the central portion of the upper surface of the second metal layer and overlapping the second opening when viewed from the thickness direction of the substrate. Thus, even if stress from the organic insulating film is applied to the second inorganic insulating film, a portion of the first inorganic insulating film disposed between the first and second metal layers will become a wedge, thereby reducing the peeling of the second inorganic insulating film from the second metal layer.

[0053] (2) In (1) above, the second metal layer may also be thinner than the first metal layer. This reduces the peeling of the second inorganic insulating film from the second metal layer.

[0054] (3) In (1) or (2) above, the width of the lower surface of the second metal layer may be smaller than the width of the upper surface of the first metal layer. This reduces the peeling of the second inorganic insulating film from the second metal layer.

[0055] (4) In any of (1) to (3) above, the outer periphery of the second opening may be defined by the outer periphery of the third opening. This reduces the number of manufacturing steps.

[0056] (5) In any of (1) to (3) above, the outer periphery of the second opening may be located further inside than the outer periphery of the third opening. This reduces the peeling of the second inorganic insulating film from the second metal layer.

[0057] (6) In any of (1) to (5) above, the semiconductor device may also include: a third metal layer disposed on the substrate; and a third inorganic insulating film covering the third metal layer, wherein a fourth opening is provided at the center of the upper surface of the third metal layer, the center of the lower surface of the first metal layer contacts the third metal layer through the fourth opening, and the peripheral portion of the lower surface of the first metal layer contacts the third inorganic insulating film outside the fourth opening. This reduces the ingress of moisture and other contaminants into the substrate 10.

[0058] (7) In any of (1) to (6) above, the organic insulating film may also be a polyimide film or a BCB film. This reduces the peeling of the second inorganic insulating film from the second metal layer.

[0059] (8) In (7) above, the second inorganic insulating film may also be a silicon nitride film, and at least the upper surface of the second metal layer may be a gold layer. This reduces the peeling of the second inorganic insulating film from the second metal layer.

[0060] (9) In any of (1) to (8) above, the second metal layer may also have: an adhesive layer comprising the lower surface of the second metal layer; and a low-resistivity layer disposed on the adhesive layer, having a resistivity lower than that of the adhesive layer. This improves the adhesion between the periphery of the lower surface of the second metal layer and the first inorganic insulating film.

[0061] (10) In any of (1) to (9) above, the area exposed from the second opening and the third opening on the upper surface of the second metal layer may also be a bonding area. Thus, an external connecting member can be bonded to the bonding area.

[0062] [Details of the embodiments of this disclosure]

[0063] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is illustrated by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0064] (First Implementation)

[0065] The first embodiment is an example of a semiconductor device that includes a metal layer that functions as a pad. Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is a top view showing metal layers 15, 16, and 18, openings 13A, 11A, and 12A in the semiconductor device of the first embodiment. Figure 2 The figure shows the upper surface 15A of metal layer 15, the upper surface 17A and lower surface 17B of metal layer 16, and the upper surface 19A and lower surface 19B of metal layer 18. The sizes of the upper surface 17A and lower surface 17B are not necessarily the same, nor are the sizes of the upper surface 19A and lower surface 19B necessarily the same, but... Figure 2 In the illustration, the upper surface 17A and the lower surface 17B are set to the same size, and the upper surface 19A and the lower surface 19B are set to the same size. The thickness direction of the substrate 10 is set as the Z direction, and the directions orthogonal to the Z direction and mutually orthogonal to each other are set as the X direction and the Y direction.

[0066] like Figure 1 and Figure 2 As shown, the semiconductor device 100 of the first embodiment includes a substrate 10, metal layers 15, 16, and 18, an inorganic insulating film 11, an inorganic insulating film 12, an inorganic insulating film 13, and an organic insulating film 14. The substrate 10 has a substrate 10A and a semiconductor layer 10B disposed on the substrate 10A. The metal layer 15 is disposed on the substrate 10. The inorganic insulating film 13 is disposed on the substrate 10 to cover the metal layer 15. The inorganic insulating film 13 has an opening 13A that exposes the central portion of the upper surface 15A of the metal layer 15 but does not expose the peripheral portion of the upper surface 15A of the metal layer 15.

[0067] A metal layer 16 is disposed on the metal layer 15 and the inorganic insulating film 13. The central portion of the lower surface 17B of the metal layer 16 contacts the metal layer 15 via an opening 13A. The peripheral portion of the lower surface 17B of the metal layer 16 contacts the inorganic insulating film 13 outside the opening 13A. The metal layer 16 includes a metal layer 16A that contacts the upper surfaces of the metal layer 15 and the inorganic insulating film 13, and a metal layer 16B disposed on the metal layer 16A. The metal layer 16A is an adhesive layer that improves the adhesion between the metal layer 16B and the metal layer 15 and the inorganic insulating film 13. The metal layer 16B is a low-resistivity layer having a lower resistivity than the metal layer 16A. The inorganic insulating film 11 is disposed on the substrate 10 to cover the metal layer 16 and the inorganic insulating film 13. The inorganic insulating film 11 has an opening 11A that exposes the central portion of the upper surface 17A of the metal layer 16 but does not expose the peripheral portion of the upper surface 17A of the metal layer 16.

[0068] A metal layer 18 is disposed on the metal layer 16 and the inorganic insulating film 11. The central portion of the lower surface 19B of the metal layer 18 contacts the metal layer 16 via an opening 11A. The peripheral portion of the lower surface 19B of the metal layer 18 contacts the inorganic insulating film 11 outside the opening 11A. The metal layer 18 includes a metal layer 18A that contacts the upper surfaces of the metal layer 16 and the inorganic insulating film 11, and a metal layer 18B disposed on the metal layer 18A. The metal layer 18A is an adhesive layer that improves the adhesion between the metal layer 18B and the metal layer 16 and the inorganic insulating film 11. The metal layer 18B is a low-resistivity layer having a lower resistivity than the metal layer 18A. The inorganic insulating film 12 is disposed on the substrate 10 to cover the metal layer 18 and the inorganic insulating film 11. The inorganic insulating film 12 has an opening 12A that exposes the central portion of the upper surface 19A of the metal layer 18 but does not expose the peripheral portion of the upper surface 19A of the metal layer 18.

[0069] The organic insulating film 14 has an opening 14A that exposes the central portion of the upper surface of the metal layer 18 but not the peripheral portion. The outer periphery of the opening 12A is defined by the outer periphery of the opening 14A. The outer peripheries of the opening 12A and the opening 14A are substantially aligned. Alternatively, the outer peripheries of the opening 12A and the opening 14A may not be aligned. Components for external connection, such as bonding lines or bumps, are bonded to the upper surfaces of the metal layer 18 exposed from the openings 12A and 14A. Thus, the upper surfaces of the metal layer 18 exposed from the openings 12A and 14A function as solder pads.

[0070] Semiconductor layer 10B is a nitride semiconductor layer, an arsenide semiconductor layer, or a silicon layer. The nitride semiconductor layer is, for example, gallium nitride, aluminum nitride, indium nitride, or a mixture thereof. The arsenide semiconductor layer is, for example, gallium arsenide, aluminum arsenide, indium arsenide, or a mixture thereof. When semiconductor layer 10B is a nitride semiconductor layer, substrate 10A is, for example, a silicon carbide substrate, a sapphire substrate, or a gallium nitride substrate. When semiconductor layer 10B is an arsenide semiconductor layer, substrate 10A is, for example, a gallium arsenide substrate. When semiconductor layer 10B is a silicon layer, substrate 10A is, for example, a silicon substrate.

[0071] Inorganic insulating films 11 to 13 are, for example, silicon nitride films, silicon oxide films, silicon oxynitride films, or aluminum oxide films; silicon nitride film is an example. The main components of inorganic insulating films 11 to 13 may be the same or different from each other. Organic insulating film 14 is, for example, a polyimide film or a BCB (Benzocyclobutene) film; polyimide film is an example. Metal layers 16A and 18A are, for example, titanium layers, titanium-tungsten layers, titanium nitride layers, or titanium-tungsten nitride layers. The main components of metal layers 16A and 18A may be the same or different from each other. Metal layers 16B and 18B are, for example, gold layers, copper layers, or aluminum layers. The main components of metal layers 16B and 18B may be the same or different from each other. The resistivity of metal layer 16B and metal layer 18B can be, for example, less than 1 / 2 or less than 1 / 5 of the resistivity of metal layer 16A and metal layer 18A.

[0072] (Comparative morphology)

[0073] Figure 3 This is a cross-sectional view of a semiconductor device in a comparative configuration. For example... Figure 3 As shown, in the comparative semiconductor device 110, the inorganic insulating film 11 and the metal layer 18 are not provided. The inorganic insulating film 12 is provided to cover the metal layer 16. The inorganic insulating film 12 has an opening 12A that exposes the central portion of the upper surface of the metal layer 16 but does not expose the peripheral portion of the upper surface of the metal layer 16. Other configurations are the same as in the first embodiment.

[0074] When using inorganic insulating film 12 and organic insulating film 14 as protective films, the coefficient of linear expansion of organic insulating film 14 is generally larger than that of inorganic insulating film and metal layer. Therefore, after heat treatment of organic insulating film 14, shrinkage stress 50 is generated on organic insulating film 14. The stress concentrates at the end of opening 14A of organic insulating film 14 and the end 51 of opening 12A of inorganic insulating film 12. In addition, the adhesion between inorganic insulating film and metal layer is generally low. Therefore, inorganic insulating film 12 may sometimes peel off from metal layer 16 starting from the end 51 of opening 12A of inorganic insulating film 12. Furthermore, moisture and the like can easily enter substrate 10 via path 54 from the end 51 of inorganic insulating film 12 to substrate 10, along the interface between metal layer 15 and metal layer 16 and inorganic insulating film 12 and inorganic insulating film 13. Moisture and the like reaching substrate 10 may reach transistor from the interface between substrate 10 and inorganic insulating film 13.

[0075] Figure 4 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 1 , Figure 2 as well as Figure 4 As shown, in the semiconductor device 100 according to the first embodiment, a metal layer 16 (first metal layer) is disposed on a substrate 10. An inorganic insulating film 11 (first inorganic insulating film) covers the metal layer 16 and has an opening 11A (first opening) that exposes the central portion of the upper surface 17A of the metal layer 16. A metal layer 18 (second metal layer) is disposed on the metal layer 16, with the central portion of the lower surface 19B of the metal layer 18 contacting the metal layer 16 via the opening 11A, and the peripheral portion of the lower surface 19B of the metal layer 18 contacting the inorganic insulating film 11 outside the opening 11A. An inorganic insulating film 12 (second inorganic insulating film) covers the metal layer 18 and has an opening 12A (second opening) that exposes the central portion of the upper surface 19A of the metal layer 18. An organic insulating film 14 covers the inorganic insulating film 12 and has an opening 14A (third opening) that exposes the central portion of the upper surface 19A of the metal layer 18. When viewed from the Z direction, opening 14A overlaps with opening 12A.

[0076] Thus, a portion of the inorganic insulating film 11 is disposed between the metal layers 16 and 18. Therefore, even when the stress 50 of the organic insulating film 14 is applied to the inorganic insulating film 11, the portion of the inorganic insulating film 11 disposed between the metal layers 16 and 18 forms a wedge 52, thereby reducing the peeling of the inorganic insulating film 12 from the metal layer 18. Furthermore, the path 54 from the end 51 of the inorganic insulating film 12 to the substrate 10, along the interfaces of the metal layers 15, 16, and 18, and the inorganic insulating films 11, 12, and 13, is longer than in the comparative configuration. Therefore, the entry of moisture and the like into the substrate 10 via the path 54 along the interfaces is reduced, making it less likely for moisture to reach transistors, etc. The path 54 has more bends than in the comparative configuration, further reducing the entry of moisture and the like into the substrate 10 via the path 54.

[0077] Metal layer 18 is thinner than metal layer 16. Therefore, the distance along the inorganic insulating film 12 from the wedge 52 to the end 51 of the inorganic insulating film 12 is shorter. Thus, even if stress is applied to the end 51 of the inorganic insulating film 12, the inorganic insulating film 12 is not easily peeled off from the metal layer 18. The thickness T2 of metal layer 18 can be set to 0.9 times or less than the thickness T1 of metal layer 16, or it can be set to 0.8 times or less than the thickness T1 of metal layer 16. The thickness T2 of metal layer 18 can also be greater than or equal to the thickness T1 of metal layer 16.

[0078] The width W2 of the lower surface 19B of the metal layer 18 is smaller than the width W1 of the upper surface 17A of the metal layer 16. Therefore, the distance along the inorganic insulating film 12 from the wedge 52 to the end 51 of the inorganic insulating film 12 is shortened. Thus, even if stress is applied to the end 51 of the inorganic insulating film 12, the inorganic insulating film 12 is not easily peeled off from the metal layer 18. The width W2 of the metal layer 18 can be set to 0.95 times or less of the width W1 of the metal layer 16, or it can be set to 0.9 times or less of the width W1 of the metal layer 16.

[0079] A metal layer 15 (third metal layer) is disposed on the substrate 10. An inorganic insulating film 13 (third inorganic insulating film) covers the metal layer 15, and an opening 13A (fourth opening) is provided in the center of the upper surface 15A of the metal layer 15. The center of the lower surface 17B of the metal layer 16 contacts the metal layer 15 through the opening 13A, and the peripheral portion of the lower surface 17B contacts the inorganic insulating film 13 outside the opening 13A. As a result, the entry of moisture and the like into the substrate 10 via path 54 is reduced, and moisture is less likely to reach transistors and the like.

[0080] When the organic insulating film 14 is a polyimide film or a BCB film, stress 50 will be generated in the organic insulating film 14. Therefore, the peeling of the inorganic insulating film 12 from the metal layer 18 can be reduced by providing the wedge 52.

[0081] The inorganic insulating film 12 is a silicon nitride film. When at least the upper surface of the metal layer 18 is a gold layer, the adhesion between the inorganic insulating film 12 and the metal layer 18 is relatively weak. Therefore, the peeling of the inorganic insulating film 12 from the metal layer 18 can be reduced by providing the wedge 52.

[0082] Figure 5 This is an enlarged cross-sectional view of the semiconductor device according to the first embodiment. Figure 5 In this context, the distance between the inorganic insulating film 12 covering the upper surface 19A of the metal layer 18, i.e., the distance between the side surface of the metal layer 18 and the end face of the inorganic insulating film 12, is denoted as D1. If the distance D1 is short, moisture and other substances can easily penetrate between the metal layer 18 and the inorganic insulating film 12, thereby deteriorating the moisture resistance. From the viewpoint of moisture resistance, the distance D1 is, for example, 1 μm or more. From the viewpoint of miniaturization, the distance D1 is, for example, 10 μm or less. Furthermore, the distance D1 can be, for example, set to be 0.2 times or more and 10 times or less than the thickness T2 of the metal layer 18, or it can be set to be 1 times or more and 5 times or less than the thickness T2 of the metal layer 18.

[0083] The distance covered by the inorganic insulating film 11 on the lower surface 19B of the metal layer 18, i.e., the distance between the side surface of the metal layer 18 and the end face of the inorganic insulating film 11, is D2. From the viewpoint of the alignment accuracy between the metal layer 18 and the inorganic insulating film 12, the distance D2 is, for example, 0.5 μm or more. From the viewpoint of increasing the contact area between the metal layer 16 and the metal layer 18, the distance D2 is, for example, 10 μm or less. Furthermore, the distance D2 can be set to be, for example, 0.1 times or more and 20 times or less of the thickness T2 of the metal layer 18, or it can be set to be 0.5 times or more and 10 times or less of the thickness T2 of the metal layer 18.

[0084] The distance between the side surface of metal layer 16 and the side surface of metal layer 18 is D3. From the viewpoint of alignment accuracy between metal layer 16 and metal layer 18, the distance D3 is, for example, 0.5 μm or more. From the viewpoint of miniaturization, the distance D3 is, for example, 5 μm or less. Furthermore, the distance D3 can be set to be, for example, 0.1 times or more and 10 times or less than the thickness T2 of metal layer 18, or it can be set to be 0.5 times or more and 5 times or less than the thickness T2 of metal layer 18.

[0085] From the viewpoint of reducing current density, the thickness T1 of metal layer 16 is, for example, 1 μm or more; from the viewpoint of reducing manufacturing processes, the thickness T1 of metal layer 16 is, for example, 5 μm or less. From the viewpoint of reducing current density, the thickness T2 of metal layer 18 is, for example, 1 μm or more; from the viewpoint of reducing manufacturing processes, the thickness T2 of metal layer 18 is, for example, 5 μm or less.

[0086] From the viewpoint of reducing pinholes, the thickness T3 of the inorganic insulating film 11 is, for example, 0.1 μm or more; from the viewpoint of reducing parasitic capacitance, the thickness T3 of the inorganic insulating film 11 is, for example, 0.4 μm or less. From the viewpoint of reducing pinholes, the thickness T4 of the inorganic insulating film 12 is, for example, 0.2 μm or more; from the viewpoint of reducing parasitic capacitance, the thickness T4 of the inorganic insulating film 12 is, for example, 0.8 μm or less.

[0087] From the viewpoint of functioning as a protective film, the thickness T5 near the opening 14A of the organic insulating film 14 is, for example, 1 μm or more; from the viewpoint of manufacturing time, the thickness T5 near the opening 14A of the organic insulating film 14 is 10 μm or less. It should be noted that in order to use the organic insulating film 14 as a protective film, the thickness T5 is increased. However, when the thickness T5 increases, the stress applied to the end 51 increases. Therefore, when the organic insulating film 14 is thicker, the peeling of the inorganic insulating film 12 can be reduced by providing the metal layer 16 and the metal layer 18.

[0088] (Manufacturing method of the first embodiment)

[0089] Figures 6 to 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. (e.g.) Figure 6 As shown, a metal layer 15 is formed on a substrate 10. The metal layer 15 is formed, for example, using vacuum evaporation and a lift-off method. An inorganic insulating film 13 is formed on the substrate 10 to cover the metal layer 15. An opening 13A is formed in the inorganic insulating film 13, exposing the central portion of the upper surface 15A of the metal layer 15 but not the peripheral portion of the upper surface 15A. The inorganic insulating film 11 is formed, for example, using CVD (Chemical Vapor Deposition). The opening 13A is formed, for example, using photolithography and dry etching.

[0090] like Figure 7 As shown, metal layers 16A and 16C are formed within opening 13A and on inorganic insulating film 13. Metal layer 16A is a sealing layer. Metal layer 16C is a seed layer for forming metal layer 16B, and the main components of metal layer 16C are, for example, the same as the main components of metal layer 16B. Metal layers 16A and 16C are formed, for example, using sputtering. A mask layer 40 is formed on metal layer 16A. Mask layer 40 has an opening 40A that overlaps with opening 13A when viewed from the Z direction and is larger than opening 13A. Mask layer 40 is, for example, a photoresist and is formed by photolithography.

[0091] like Figure 8As shown, a metal layer 16B is formed within the opening 40A of the mask layer 40. The metal layer 16B is formed, for example, by electroplating, by supplying current to metal layers 16A and 16C. The metal layer 16C is omitted from the following figures. The metal layer 16 is formed from metal layers 16A and 16B. The mask layer 40 is peeled off. The metal layer 16A is etched using the metal layer 16B as a mask. Thus, the metal layer 16A outside the area where the metal layer 16B is formed is removed.

[0092] like Figure 9 As shown, an inorganic insulating film 11 is formed on an inorganic insulating film 13 by means of a covering metal layer 16. The inorganic insulating film 11 is formed, for example, using a CVD method. An opening 11A is formed in the inorganic insulating film 11, with the central portion of the upper surface 17A of the metal layer 16 exposed and the peripheral portion of the upper surface 17A not exposed. The opening 11A is formed, for example, using a photolithography method and a dry etching method.

[0093] like Figure 10 As shown, a mask layer 42 is formed on an inorganic insulating film 11. The mask layer 42 has an opening 42A. The opening 42A exposes the metal layer 16 and the inorganic insulating film 11 formed on the side of the metal layer 16. The upper surface of the mask layer 42 near the opening 42A is a curved surface in which the thickness of the mask layer 42 gradually decreases toward the opening 42A. The mask layer 42 is, for example, a photoresist, formed by photolithography. After the opening 42A is formed in the mask layer 42, a heat treatment is performed, thereby making the upper surface of the mask layer 42 curved. Metal layers 18A and 18C are formed on the mask layer 42, on the metal layer 16 within the opening 42A, and on the inorganic insulating film 11 within the opening 42A. Metal layer 18A is a sealing layer. Metal layer 18C is a seed layer for forming metal layer 18B, and the main components of metal layer 18C are, for example, the same as the main components of metal layer 18B. Metal layers 18A and 18C are formed, for example, by sputtering.

[0094] like Figure 11 As shown, a mask layer 44 is formed on the metal layer 18A. The mask layer 44 has an opening 44A. The opening 44A is larger than the opening 11A but smaller than the upper surface 17A of the metal layer 16. The mask layer 44 is, for example, a photoresist and is formed by photolithography.

[0095] like Figure 12 As shown, a metal layer 18B is formed within the opening 44A of the mask layer 44. The metal layer 18B is formed, for example, by supplying current to the metal layer 18A using an electroplating method. The illustration of the metal layer 18C is omitted in the following figures. A metal layer 18 is formed from the metal layers 18A and 18B. The mask layer 44 is peeled off. The metal layer 18A is etched using the metal layer 18B as a mask. Thus, the metal layer 18A outside the area where the metal layer 18B is formed is removed. The mask layer 42 is peeled off.

[0096] like Figure 13 As shown, an inorganic insulating film 12 is formed on the inorganic insulating film 11 by means of a metal layer 18. The inorganic insulating film 12 is formed, for example, using a CVD method.

[0097] like Figure 14 As shown, an organic insulating film 14 is formed on the inorganic insulating film 12. The organic insulating film 14 has an opening 14A. The opening 14A is smaller than the upper surface 19A of the metal layer 18. The organic insulating film 14 is, for example, a photosensitive polyimide film, formed by photolithography.

[0098] Next, the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask. This forms an opening 12A in the inorganic insulating film 12. This process is then used to manufacture... Figure 1 The semiconductor device 100 of the first embodiment.

[0099] In the first embodiment, the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask. Therefore, a mask layer is not required for forming the opening 12A of the inorganic insulating film 12, thereby reducing manufacturing steps. Since the inorganic insulating film 12 is removed using the organic insulating film 14 as a mask, the outer periphery of the opening 12A is defined by the outer periphery of the opening 14A.

[0100] In addition, such as Figures 10-12 The metal layer 18 is thus formed. In this case, the metal layer 18 has: a metal layer 18A (adhesive layer) including the lower surface 19B of the metal layer 18; and a metal layer 18B (low-resistance layer) disposed on the metal layer 18A, having a resistivity lower than that of the metal layer 18A. Therefore, the adhesion between the periphery of the lower surface 19B of the metal layer 18 and the inorganic insulating film 11 is improved. Thus, the metal layer 18 can be formed on the inorganic insulating film 11.

[0101] (Modification 1 of the first embodiment)

[0102] Figure 15 This is a cross-sectional view of a semiconductor device according to a variation of the first embodiment, Example 1. Figure 15 As shown, in the semiconductor device 102 of the first embodiment's modified example 1, the opening 14A of the organic insulating film 14 is formed to be larger than the opening 12A of the inorganic insulating film 12. The end 51 of the inorganic insulating film 12 is located more inward than the end 53 of the organic insulating film 14. That is, the outer periphery of the opening 12A is located more inward than the outer periphery of the opening 14A.

[0103] In a variation of the first embodiment, when stress 50 is generated on the organic insulating film 14, although stress is applied to the end 53 of the organic insulating film 14, the stress applied to the end 51 of the inorganic insulating film 12 is smaller. Therefore, the peeling of the inorganic insulating film 12 from the metal layer 16 can be reduced.

[0104] (Manufacturing method of variation 1 of the first embodiment)

[0105] Figure 16 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment, Example 1. Figure 16 As shown, in the first embodiment Figure 14 Next, a mask layer 46 is formed on the organic insulating film 14. The mask layer 46 has an opening 46A smaller than the opening 14A. The mask layer 46 is, for example, a photoresist, formed by photolithography.

[0106] exist Figure 16 Next, the inorganic insulating film 12 is removed using the mask layer 46 as a mask. For example, dry etching is used in the removal of the inorganic insulating film 12. Then, the mask layer 46 is peeled off. Thus, the semiconductor device 102 is manufactured.

[0107] (Second Implementation)

[0108] The second embodiment is an example of using the structure of metal layer 16 and metal layer 18 of the first embodiment and its variation 1 for the bonding pads of a transistor. Figure 17 This is a top view of the semiconductor device according to the second embodiment.

[0109] like Figure 17 As shown, the semiconductor device 104 of the second embodiment includes a substrate 10, a source electrode 20, a drain electrode 21, a gate electrode 22, pads 24S, pads 24D, and pads 24G. Multiple source electrodes 20 and multiple drain electrodes 21 are alternately arranged in the X direction. A gate electrode 22 is provided between the source electrodes 20 and drain electrodes 21 in the X direction. The source electrodes 20, drain electrodes 21, and gate electrodes 22 are finger-shaped and extend in the Y direction.

[0110] In the X-direction, the width of the source electrode 20 increases every two source electrodes 20. A via 25 penetrating the substrate 10 is connected to the thicker source electrode 20. The thicker source electrode 20 is electrically connected to a metal layer on the lower surface of the substrate 10 via the via 25. The thinner source electrode 20 is electrically connected to the thicker source electrode 20 via source wiring 23. The source wiring 23 intersects the gate electrode 22 without contact. The outermost source electrode 20 in the X-direction is electrically connected to pad 24S.

[0111] Multiple drain electrodes 21 are electrically connected to pad 24D. Multiple gate electrodes 22 are electrically connected to pad 24G. Pads 24S, 24D, and 24G each have a metal layer 16, a metal layer 18, an opening 12A, and an opening 14A, respectively. The structures of pads 24S, 24D, and 24G are the same as in the first embodiment and its variation 1. The area exposed from the openings 12A and 14A on the upper surface of the metal layer 18 (details omitted) is the bonding area 26. Therefore, external connection members, such as bonding wires or bumps, can be bonded to the bonding area 26. Furthermore, probes for electrical testing can contact the bonding area 26. It should be noted that voltage is supplied to the source electrode 20 from the metal layer on the lower surface of the substrate 10 via vias 25; therefore, external connection members may not be bonded to pad 24S. Probes for electrical testing contact pad 24S.

[0112] In the source electrode 20 and drain electrode 21, metal layers 15 and 16 are stacked from the substrate 10 side. In the case that the semiconductor device 104 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the metal layer 15 from the substrate 10 side is, for example, a titanium layer and an aluminum layer. The gate electrode 22 from the substrate 10 side is, for example, a nickel layer and a gold layer.

[0113] In the second embodiment, a FET is used as an example of a transistor, but the transistor can also be a bipolar transistor other than a FET.

[0114] The embodiments disclosed herein are exemplary in all respects and should not be considered limiting. The scope of this disclosure is not indicated by the foregoing meaning but by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A first metal layer is disposed on the substrate; A first inorganic insulating film covers the first metal layer and has a first opening that exposes the central portion of the upper surface of the first metal layer. A second metal layer is disposed on the first metal layer. The central portion of the lower surface of the second metal layer contacts the first metal layer through the first opening, and the peripheral portion of the lower surface contacts the first inorganic insulating film outside the first opening. A second inorganic insulating film covers the second metal layer and has a second opening that exposes the central portion of the upper surface of the second metal layer. as well as An organic insulating film covering the second inorganic insulating film has a third opening that exposes the central portion of the upper surface of the second metal layer and overlaps with the second opening when viewed from the thickness direction of the substrate.

2. The semiconductor device according to claim 1, wherein, The second metal layer is thinner than the first metal layer.

3. The semiconductor device according to claim 1 or 2, wherein, The width of the lower surface of the second metal layer is smaller than the width of the upper surface of the first metal layer.

4. The semiconductor device according to claim 1 or 2, wherein, The outer periphery of the second opening is defined by the outer periphery of the third opening.

5. The semiconductor device according to claim 1 or 2, wherein, The outer periphery of the second opening is located inside the outer periphery of the third opening.

6. The semiconductor device according to claim 1 or 2, comprising: A third metal layer is disposed on the substrate; and A third inorganic insulating film covers the third metal layer, and a fourth opening is provided in the center of the upper surface of the third metal layer. The central portion of the lower surface of the first metal layer contacts the third metal layer via the fourth opening, and the peripheral portion of the lower surface of the first metal layer contacts the third inorganic insulating film outside the fourth opening.

7. The semiconductor device according to claim 1 or 2, wherein, The organic insulating film is a polyimide film or a benzocyclobutene (BCB) film.

8. The semiconductor device according to claim 7, wherein, The second inorganic insulating film is a silicon nitride film. At least the upper surface of the second metal layer is a gold layer.

9. The semiconductor device according to claim 1 or 2, wherein, The second metal layer has: an adhesive layer including a lower surface of the second metal layer; and a low-resistivity layer disposed on the adhesive layer, having a resistivity lower than that of the adhesive layer.

10. The semiconductor device according to claim 1 or 2, wherein, The area exposed from the second opening and the third opening on the upper surface of the second metal layer is the bonding area.

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