Dynamic DDR frequency scaling based on bandwidth and latency use cases, refresh rate, and memory size.

Abstract

Various implementations include methods and apparatus for scaling memory frequency configurations by a computing device. Each implementation includes: comparing at least a memory refresh rate, memory size, at least one use case bandwidth for transmission between the memory and a system-on-a-chip (SoC), and at least one use case latency for transmission between the memory and the SoC, respectively, with the memory refresh rate, memory size, at least one use case bandwidth, and at least one use case latency for transmission between the memory and the SoC; selecting a memory frequency based on all the results of these comparisons; and configuring the memory for that memory frequency. Some implementations may include issuing an alert instructing a change in usage to enable the memory to fulfill use case parameters.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. nonprovisional application No. 18 / 447,159, filed August 9, 2023, the entire contents of which are incorporated herein by reference. Background Technology

[0003] The memory usage requirements of a use case may be stringent. The use case may need to meet certain parameters to achieve its proper functionality. For example, a use case might require bandwidth and latency levels using Double Data Rate (DDR) random access memory (RAM). The ability of the memory to meet these parameters may be affected by memory temperature. For instance, as the temperature at DDR memory increases, the DDR memory refresh rate must increase to maintain the integrity of the data stored there. Increasing the memory refresh rate reduces bandwidth and increases the latency of the DDR memory. The increase in memory refresh rate, and its impact on bandwidth and latency, may result in the use case requirements not being met. Summary of the Invention

[0004] Various aspects provide methods for scaling the memory frequency configuration of a computing device's memory and apparatus for implementing such methods. These aspects may include: comparing at least a memory refresh rate, memory size, at least one use case bandwidth for transmission between the memory and a system-on-a-chip (SoC), and use case latency for transmission between the memory and the SoC with at least one storage's memory refresh rate, at least one storage's memory size, at least one storage's use case bandwidth for transmission between the memory and the SoC, and at least one storage's use case latency for transmission between the memory and the SoC; selecting a memory frequency based on the comparison results; and configuring the memory for the memory frequency.

[0005] In some respects, at least one use case bandwidth may include the current bandwidth of the use case and the average bandwidth of the use case, and at least one stored use case bandwidth may include the stored current bandwidth of the use case and the stored average bandwidth of the use case.

[0006] Some aspects may also include: identifying the memory refresh rate of the storage that matches the memory refresh rate; identifying the memory size of the storage that matches the memory size; identifying the use case bandwidth of at least one storage that matches the use case bandwidth of at least one storage; identifying the use case latency of at least one storage that matches the use case latency, wherein the result of the comparison may include the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of at least one storage, and the use case latency of at least one storage; and identifying the memory frequency of the storage associated with the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of at least one storage, and the use case latency of at least one storage.

[0007] Some aspects may also include identifying a maximum memory frequency as a memory frequency in response to failure to identify at least one of the use case bandwidth of at least one storage that matches at least one use case bandwidth or the use case latency of at least one storage that matches at least one use case latency, wherein the result of the comparison may include less than all of the use case bandwidth of at least one storage that matches at least one use case bandwidth or the use case latency of at least one storage that matches at least one use case latency.

[0008] Some aspects may also include issuing an alarm signal configured to indicate a change in the use case so that the memory can achieve the use case parameters.

[0009] Some aspects may also include receiving the memory refresh rate from the memory subsystem.

[0010] Some aspects may also include sending a memory frequency modification signal to the memory subsystem.

[0011] Another aspect includes a computing device comprising a memory and a processor and / or a memory frequency device configured to perform operations of any of the methods outlined above. Another aspect includes a non-transitory processor-readable storage medium having processor-executable software instructions stored thereon, these instructions being configured to cause the processor and / or memory frequency device to perform operations of any of the methods outlined above. Another aspect includes a computing device having components for implementing the functionality of any of the methods outlined above. Attached Figure Description

[0012] The accompanying drawings, incorporated herein and forming part of this specification, illustrate exemplary embodiments of various implementations and, together with the general description given above and the detailed description given below, serve to interpret the features of the claims.

[0013] Figure 1 This is a component block diagram illustrating an example computing device suitable for implementing various implementation schemes.

[0014] Figure 2 This is a component block diagram illustrating a computing device suitable for implementing various implementation schemes.

[0015] Figure 3 These are component block diagrams and signaling diagrams illustrating examples of systems that implement dynamic DDR scaling and use case management based on DDR refresh rate and size, suitable for implementing various implementation schemes.

[0016] Figure 4 This is an example information structure diagram illustrating an implementation scheme for dynamic DDR scaling and use case management based on DDR refresh rate and size.

[0017] Figure 5 This is a flowchart illustrating an example method for implementing dynamic DDR scaling and use case management based on DDR refresh rate and size, according to the implementation scheme.

[0018] Figure 6A and Figure 6B This is a flowchart illustrating an example method for implementing dynamic DDR scaling and use case management based on DDR refresh rate and size, according to the implementation scheme.

[0019] Figure 7 This is a component block diagram illustrating an example mobile computing device suitable for implementing various implementation schemes.

[0020] Figure 8 This is a component block diagram illustrating an example mobile computing device suitable for implementing various implementation schemes.

[0021] Figure 9 This is a component block diagram illustrating an example server suitable for implementing various implementation schemes.

[0022] Figures 10A to 10C This is a component block diagram illustrating an example embedded vehicle computing system suitable for implementing various implementation schemes. Detailed Implementation

[0023] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the claims.

[0024] Various implementations include methods for achieving dynamic DDR scaling and use case management based on DDR refresh rate and size, and computing devices implementing such methods. Various implementations may include comparing memory characteristics and use case parameters with stored data, selecting a memory frequency based on the comparison results, and configuring memory for the memory frequency. Some implementations may include identifying the memory frequency based on whether the memory characteristics enable the use case parameters. Some implementations may include identifying the maximum memory frequency as the memory frequency based on whether the memory characteristics cannot enable the use case parameters. Some implementations may include issuing an alarm signal based on whether the memory characteristics cannot enable the use case parameters, the alarm signal being configured to indicate changes to the use case to enable the memory to enable the use case parameters.

[0025] The term "computing device" as used herein refers to a resident computing device, including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers (such as those embedded in vehicles and other larger systems), computer systems within or configured for use in vehicles, servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any or all of the following: cellular phones, smartphones, personal or mobile multimedia players, personal data assistants (PDAs), laptop computers, tablet computers, convertible laptops / tablets (2-in-1 computers), smartbooks, ultrabooks, netbooks, handheld computers, wireless email receivers, internet-enabled multimedia cellular phones, mobile game consoles, wireless game controllers, and similar personal electronic devices including memory and programmable processors.

[0026] For ease of explanation and clarity, while various embodiments are described in terms of code (e.g., processor-executable instructions), the same principle applies to any data, such as code, program data, or other information stored in memory. The terms “code,” “data,” and “information” are used interchangeably herein and are not intended to limit the scope of the claims and specification to the types of code, data, or information used as examples in describing the various embodiments.

[0027] The memory usage requirements of a use case may be stringent. The use case may need to meet certain parameters to achieve its proper functionality. For example, a use case might require bandwidth and latency levels using Double Data Rate (DDR) random access memory (RAM). The ability of the memory to meet these parameters may be affected by memory temperature. For instance, when the temperature of DDR memory increases to a certain level, the DDR memory refresh rate must be increased to maintain the integrity of the data stored in the DDR memory. Increasing the memory refresh rate reduces read / write bandwidth and increases the latency of the DDR memory. Increasing the memory refresh rate, and the impact of doing so on bandwidth and latency, may result in the use case requirements not being met.

[0028] Various implementations address and overcome the aforementioned problems related to memory performance under adverse temperature conditions. These implementations may include using memory characteristics and use case parameters compared to the stored data to select a memory frequency to achieve appropriate functionality for the memory, thereby supporting use cases under temperature conditions. Memory characteristics may include the memory refresh rate, which can be used as a proxy for the memory's temperature conditions. At various temperature levels, the memory can vary the memory refresh rate required to maintain the integrity of the data stored in it. Based in part on the memory refresh rate, memory frequency can be selected to achieve appropriate functionality for use cases under temperature conditions. Another memory characteristic may include memory size, as the effect of temperature conditions on memory refresh rate may differ between memory sizes. Based in part on memory size, memory frequency can be selected to achieve appropriate functionality for use cases under temperature conditions. If the use case parameters cannot be achieved under the memory's temperature conditions, an alert configured to indicate the need to change the use case can be generated.

[0029] In some implementations, memory characteristics may include at least a memory refresh rate and a memory size, and use case parameters may include at least one use case bandwidth for transmission between the memory and the system-on-chip (SoC) and a use case latency for transmission between the memory and the SoC. Stored data may include at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth for transmission between the memory and the SoC, and at least one stored use case latency for transmission between the memory and the SoC. Comparison of memory characteristics and use case parameters with stored data may include comparing similar types of data of the memory characteristics and use case parameters with similar types of data of the stored data. For example, comparing the memory refresh rate with the memory refresh rate of at least one stored memory; comparing the memory size with the memory size of at least one stored memory; comparing at least one use case bandwidth with the use case bandwidth of at least one stored memory; and / or comparing the use case latency with the use case latency of at least one stored memory. Memory frequency may be stored in association with stored data that meets comparison criteria. Memory frequency can be selected for configuring the memory for the memory frequency to implement use case parameters for appropriate functionality of the use case under the temperature conditions of the memory.

[0030] If the stored data does not meet the comparison criteria, the maximum memory frequency can be selected. Alarm signals configured to indicate changes to the use case can be generated under the same conditions. In a given situation, selecting the maximum frequency allows the memory to provide the maximum possible performance in terms of bandwidth and latency, and the alarm signals ensure that changes to the use case can avoid potential problems caused by the memory failing to meet the use case parameters.

[0031] Non-limiting example applications of various implementations include concurrent memory usage by multiple clients, where at least one use case requires support for use case parameters to achieve appropriate functionality. For example, concurrent memory usage can be implemented by modem functionality and Global Navigation Satellite System (GNSS) receiver functionality. At the basic memory refresh rate (which may correspond to cryogenic conditions), concurrent traffic from the GNSS receiver functionality can be used to implement the use case parameters for the modem functionality. Depending on factors such as increases in memory refresh rate and memory size, increased temperature conditions in the memory may affect memory latency and / or bandwidth. The severity of this effect may vary between larger and smaller memories. However, temperature conditions that increase the memory refresh rate relative to the memory refresh rate at which appropriate modem functionality can be achieved may affect memory latency and / or bandwidth to some extent, making it possible that appropriate modem functionality may no longer be achieved. In such cases, various implementations can be implemented to select a memory frequency associated with the memory refresh rate and memory size at which appropriate modem functionality can be achieved.

[0032] Figure 1 An example is illustrated by a system including a computing device 10 suitable for use with various implementation schemes. Reference Figure 1 The computing device 10 may include a system-on-a-chip (SoC) 12 having a processor 14, memory 16, a communication interface 18, a storage memory interface 20, a memory interface 34, a power manager 28, a clock controller 30, a peripheral device interface 38, and interconnects 32. The computing device 10 may also include communication components 22 (such as a wired or wireless modem), storage memory 24, an antenna 26 for establishing wireless communication links, memory 36, and peripheral devices 40. The processor 14 may include any of a variety of processing devices, such as multiple processor cores.

[0033] The term "System-on-a-Chip" (SoC) is used herein to refer to a collection of interconnected electronic circuits, typically but not exclusively including processing devices, memory, and communication interfaces. Processing devices can include a wide variety of different types of processors¹⁴ and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), subsystem processors for specific components of a computing device (such as image processors in a camera subsystem or display processors in a display), auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. Processing devices can also embody other hardware and hardware combinations, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic components, transistor logic components, performance monitoring hardware, watchdog hardware, and time references. Integrated circuits can be configured such that components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0034] SoC 12 may include one or more processors 14. Computing device 10 may include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. Computing device 10 may also include processors 14 not associated with SoC 12. Processors 14 may each be configured for a specific purpose that may be the same as or different from other processors 14 of computing device 10. One or more of processors 14 and processor cores with the same or different configurations may be grouped together. A group of processors 14 or processor cores may be referred to as a multiprocessor cluster.

[0035] The memories 16, 36 of SoC 12 may be volatile or non-volatile memories configured to store data and processor-executable code accessible to processor 14. Computing device 10 and / or SoC 12 may include one or more memories 16, 36 configured for various purposes. One or more memories 16, 36 may include volatile memories such as random access memory (RAM) or main memory, including static RAM (SRAM) and / or dynamic RAM (DRAM) or cache memory. These memories 16, 36 may be configured to temporarily hold a limited amount of data received from data sensors or subsystems, data and / or processor-executable code instructions requested from non-volatile memories 16, 24 and loaded into memory 16 from non-volatile memories 16, 24 based on various factors upon anticipated future access, and / or intermediate processing data and / or processor-executable code instructions generated by processor 14 and temporarily stored for future fast access without being stored in non-volatile memories 16, 24. The memory interface 34 and the memory 36 can work together to allow the computing device 10 to load and retrieve data and processor executable code on the memory 36.

[0036] Storage interface 20 and storage memory 24 can operate in concert to allow computing device 10 to store data and processor-executable code on a non-volatile storage medium. Storage memory 24 can be configured very similarly to an embodiment of memory 16, wherein storage memory 24 can store data or processor-executable code for access by one or more processors in processor 14. The non-volatile storage memory 24 can retain information after computing device 10 has been powered off. When power is restored and computing device 10 restarts, the information stored in storage memory 24 becomes available to computing device 10. Storage interface 20 can control access to storage memory 24 and allow processor 14 to read data from and write data to storage memory 24.

[0037] Power manager 28 can be configured to control the power state of one or more power rails (not shown) for power delivery to components of SoC 12. In some implementations, power manager 28 can be configured to control the amount of power supplied to components of SoC 12. For example, power manager 28 can be configured to control the connection between components of SoC 12 and power rails. As another example, power manager 28 can be configured to control the amount of power on power rails connected to components of SoC 12. Power manager 28 can be configured as a power management integrated circuit (power management IC or PMIC).

[0038] Clock controller 30 can be configured to control clock signals sent to components of SoC 12. For example, clock controller 30 can gate components of SoC 12 by disconnecting them from clock signals, and can degated components of SoC 12 by connecting them to clock signals.

[0039] Peripheral device interface 38 enables components of SoC 12 (such as processor 14 and / or memory 16) to communicate with peripheral device 40. Peripheral device interface 38 provides and manages the physical and logical connections between components of SoC 12 and peripheral device 40. Peripheral device interface 38 also manages communication between components of SoC 12 and peripheral device 40, such as by directing and / or allowing communication between transmitter and receiver pairs of components of SoC 12 and peripheral device 40. Communication may include the transmission of memory access commands, addresses, data, interrupt signals, status signals, etc. Peripheral device 40 may be any component of computing device 10 that is separate from SoC 12, such as a processor, memory, subsystem, etc. In some embodiments, peripheral device interface 38 may include a PCIe root complex and enable PCIe protocol communication between components of SoC 12 and peripheral device 40.

[0040] Interconnect 32 may be a communication structure, such as a communication bus, configured to communicatively connect components of SoC 12. Interconnect 32 may transmit signals between components of SoC 12. In some embodiments, interconnect 32 may be configured to control signals between components of SoC 12 by controlling the timing and / or transmission paths of control signals.

[0041] Some or all of the components of computing device 10 and / or SoC 12 may be arranged differently and / or combined, while still providing the functionality of various implementations. Computing device 10 may not be limited to one component of each component, and multiple instances of each component may be included in various configurations of the computing device.

[0042] Figure 2 Examples of computing devices suitable for implementing various implementation schemes are shown (e.g., Figure 1 Example system 200 (computing device 10 in the example). Reference Figure 1 and Figure 2 System 200 may include use case module 202 (e.g., Figure 1 The processor 14, communication component 22, peripheral device 40), memory frequency selector 204, and memory subsystem 206 (e.g., Figure 1 The memory interface 34 and memory 36 are included. Various components of the system 200 can be variably arranged and can be integrated with a SoC (e.g., ...). Figure 1 (SoC 12) integration and / or separation.

[0043] Use case module 202 may include any combination of hardware, software, and / or firmware configured to implement use cases and provide use case parameters for the proper operation of the use cases. Non-limiting examples of use cases include telecommunications functions, audio / video functions, electromagnetic radiation signal processing functions, artificial intelligence (AI) functions, autonomous navigation functions, mechanical safety system functions, etc. Use case module 202 may send use case parameters required for the proper operation of the use cases to memory frequency selector 204. Such use case parameters may include information about the use case bandwidth (such as the current bandwidth of the use case at a certain time and the average bandwidth of the use case over a period of time) and the use case latency of the transmission between memory 36 and SoC.

[0044] Memory 36 may include any memory configured to store data that enables use case module 202 to implement the use case. In a non-limiting example, memory 36 may be DDR memory. In some examples, memory 36 may be DDR synchronous dynamic RAM (SDRAM) separate from SoC 12.

[0045] The memory 36 may be configured with various temperature thresholds at which the memory 36 may be configured to change its refresh rate in response to temperature conditions in the memory 36 reaching and / or exceeding the temperature threshold. For example, a temperature condition reaching and / or exceeding the temperature threshold may prompt the memory 36 to increase the memory refresh rate, and a temperature condition reaching and / or falling below the temperature threshold may prompt the memory 36 to decrease the memory refresh rate. In a non-limiting example, the basic memory refresh rate may be a minimum memory refresh rate and may be referred to as 1x. Higher memory refresh rates may be referred to as multiples of the basic memory refresh rate, such as 2x, 4x, etc. Higher memory refresh rates allow the memory 36 to refresh more frequently compared to lower memory refresh rates. For example, a 1x memory refresh rate may refresh every 4 ms, a 2x memory refresh rate may refresh every 2 ms, a 4x memory refresh rate may refresh every 1 ms, and so on.

[0046] The memory subsystem 206 may include any combination of hardware, software, and / or firmware, such as a memory controller 208 and a physical layer 210, configured to provide and manage physical and logical connectivity and to manage communication between the use case module 202 and the memory 36. Such communication may include data access commands and data sent between the use case module 202 and the memory 36. In some examples, various components of the memory subsystem 206 may be integrated with and / or decoupled from the SoC and / or the memory 36. The memory subsystem 206 may be configured to periodically, continuously, or intermittently poll the memory 36 to obtain its memory refresh rate. The memory subsystem 206 may send the memory refresh rate to the memory frequency selector 204.

[0047] The memory frequency selector 204 may include any combination of hardware, software, and / or firmware configured to select a memory frequency for configuring the memory 36 to operate at that memory frequency. The memory frequency selector 204 may receive use case parameters from the use case module 202 and a memory refresh rate from the memory subsystem 206. The memory frequency selector 204 may be programmed with respect to the memory size of the memory 36. In some examples, the memory frequency selector 204 may store an information structure, as further described herein, in a memory (e.g., a lookup table not shown), configured to store memory characteristics and use case parameters in association with the memory frequency. The memory frequency associated with the memory characteristics and use case parameters may be configured to implement the appropriate use case functionality of the memory 36 configured with the memory frequency while simultaneously displaying the memory characteristics and use case parameters.

[0048] The memory frequency selector 204 can compare use case parameters and memory characteristics with stored data to select a memory frequency. For example, it can compare memory characteristics (at least memory refresh rate and memory size) and use case parameters (at least one use case bandwidth and use case delay for transmission between memory 36 and the SoC) with stored data (at least one storage's memory refresh rate, at least one storage's memory size, at least one storage's use case bandwidth and use case delay for transmission between memory and the SoC). In some examples, the memory frequency selector 204 can compare data stored in an information structure with memory characteristics and use case parameters.

[0049] By comparing memory characteristics and use case parameters with the stored data, memory frequency selector 204 can identify the memory refresh rate of storage that matches the memory refresh rate; identify the memory size of storage that matches the memory size; identify the use case bandwidth of at least one storage that matches the bandwidth of at least one use case; identify the use case latency of storage that matches the latency of use cases; and identify the memory frequency of storage associated with the memory refresh rate, memory size, bandwidth of at least one storage, and latency of storage. Memory frequency selector 204 can send the memory frequency to memory subsystem 206, which can use the memory frequency to configure memory 36.

[0050] In some cases, the memory frequency selector 204 may fail to identify at least one of the following: the use case bandwidth of at least one memory matching at least one use case bandwidth, or the use case latency of a memory matching at least one use case latency. In response to this failure, the memory frequency selector 204 may select the maximum memory refresh rate for the memory 36. The memory frequency selector 204 may send the memory frequency to the memory subsystem 206, which can use the memory frequency to configure the memory 36. In some embodiments, the memory frequency selector 204 may generate an alarm signal based on the memory characteristics preventing the fulfillment of use case parameters. This alarm signal is configured to indicate that the use case needs to be modified to enable the fulfillment of the use case parameters. The memory frequency selector 204 may transmit the alarm signal to a client of the computing device, such as the use case module 202.

[0051] Figure 3 Examples of systems (e.g., system 200) based on DDR refresh rate and size for dynamic DDR scaling and use case management, suitable for implementing various implementation schemes, are illustrated. References Figures 1 to 3 The system may include use case module 202, memory frequency selector 204, memory subsystem 206, and memory 36. The components of the system may be configured to transmit signals between components via a communication bus (not shown), and / or process computer code instructions and / or data.

[0052] The use case module 202 can transmit use case parameters to the memory frequency selector 204 via signal 302. The use case parameters may include at least one use case bandwidth (such as the current bandwidth and average bandwidth of the use case) and a use case delay for the use case module 202 to properly implement the use case functionality. The memory frequency selector 204 can receive the use case parameters from the use case module 202 via signal 302.

[0053] Memory subsystem 206 may request a memory refresh rate from memory 36. Memory 36 receives the request and may return the memory refresh rate to memory subsystem 206. Memory subsystem 206 may also receive the memory refresh rate via signal 304. Memory subsystem 206 may continuously, periodically, and / or intermittently request a memory refresh rate from memory 36. Memory 36 may continuously, periodically, and / or intermittently respond to the requests. For example, memory 36 may respond to each request received from memory system 208. As another example, memory 36 may respond to a request from memory subsystem 206 in response to a change in the memory refresh rate of memory 36 since the last response was transmitted to memory subsystem 206.

[0054] The memory subsystem 206 can forward the memory refresh rate of the memory 36 to the memory frequency selector 204, and the memory frequency selector 204 can receive the memory refresh rate via signal 306. The memory frequency selector 204 can use the received memory refresh rate to select a memory frequency for which it configures the memory 36 via process 308. The memory frequency selector 204 can compare the received at least one use case bandwidth, the received use case latency, the received memory refresh rate, and / or the programmed memory size of the memory 36 with data stored in the information structure to select a memory frequency. In response to finding a memory frequency stored in association with the received at least one use case bandwidth, the received use case latency, the received memory refresh rate, and the programmed memory size, the memory frequency selector 204 can select a memory frequency. In response to not finding a memory frequency stored in association with the received at least one use case bandwidth, the received use case latency, the received memory refresh rate, and the programmed memory size, the memory frequency selector 204 can select the maximum memory frequency for the memory 36.

[0055] Whether selecting a memory frequency stored in association with a memory frequency (which is stored in association with at least one received use case bandwidth, received use case latency, received memory refresh rate, and programmed memory size) or selecting the maximum memory frequency, the memory frequency selector 204 can transmit the selected memory frequency to the memory subsystem 206 via signal 310. The memory subsystem 206 can receive the selected memory frequency via signal 310 and use the selected memory frequency to configure the memory for the selected memory frequency via signal 312.

[0056] In response to selecting the maximum memory frequency, the memory frequency selector 204 may transmit an alarm to the use case module 202 via signal 314. The alarm may be configured to indicate a change in the use case so that the memory 36 can perform the appropriate use case function. After receiving the alarm via signal 314, the use case module 202 may change the use case and transmit the use case parameters and / or representations of the use case parameters, such as the use case identifier, to the memory frequency selector 204 via signal 302.

[0057] Figure 4 An example information structure 400 is illustrated according to the implementation scheme for implementing dynamic DDR scaling and use case management based on DDR refresh rate and size. Reference Figures 1 to 4 The information structure 400 can be stored in a memory frequency selector (e.g., Figure 2 and Figure 3 The memory frequency selector 204 in the memory and / or the memory accessible by the memory frequency selector (e.g., memory frequency selector 204) and / or the memory (e.g., memory frequency selector 204) is located at the memory frequency selector 204 in the memory and / or the memory accessible by the memory frequency selector. Figure 1Memory 16 in Figures 1 to 3 The information structure 400 can be pre-programmed and / or populated for use by use case modules (e.g., memory 36). Figure 2 and Figure 3 The use case module 202 in the information structure 400 is implemented with at least one use case and at least one memory (e.g., Figures 1 to 3 The data in the memory (36) of the device.

[0058] The information structure 400 stored in memory may include data associated with each of one or more use cases, which may be referred to herein as "stored data". Figure 4 In the illustrated example, each row may represent data related to a use case. For example, information structure 400 may include data related to at least one use case, such as at least one type of use case bandwidth (including the current bandwidth of the stored use case and / or the average bandwidth of the stored use case) and the latency of the stored use case. Information structure 400 may include data related to at least one memory, including the size of the stored memory, the refresh rate of the stored memory, and the memory frequency. The association between the data related to at least one use case in information structure 400 and at least one memory may be data for the at least one memory to implement the appropriate functionality of at least one use case. Furthermore, information structure 400 may include only a subset of possible use cases.

[0059] In some implementations, the information structure 400 stored in memory may include data for more than one use case (such as up to M number of use cases, where M is a number greater than 1), which may be referred to herein as "stored" data. Figure 4 In the illustrated non-limiting example, information structure 400 includes data for more than one use case (including "use case 1", "use case MN" (where N is a number between M and 1), and "use case M"). For example, each row in information structure 400 may be an association of data related to the use cases in more than one use case and data related to at least one memory. For example, each row in information structure 400 may include the current bandwidth of the stored use case, the average bandwidth of the stored use case, the latency of the stored use case, the size of the stored memory, the refresh rate of the stored memory, and the memory frequency. Optionally, each row may also include a use case identifier (ID) associated with the data related to the use case.

[0060] The memory frequency selector can compare any one or more of at least one use case bandwidth and / or use case delay received from the use case module with corresponding one or more of at least one stored use case bandwidth and stored use case delay in the information structure 400. For example, the memory frequency selector can compare at least one use case bandwidth and use case delay received from the use case module with at least one stored use case bandwidth and stored use case delay in the information structure 400. The memory frequency selector can select from the memory subsystem (e.g., Figure 2 and Figure 3 The memory subsystem 206 receives one or more of the programmed memory size and memory refresh rate, and compares them with one or more corresponding values ​​of the memory size and memory refresh rate stored in the information structure 400. For example, the memory frequency selector can compare the programmed memory size and memory refresh rate received from the memory subsystem with the memory size and memory refresh rate stored in the information structure 400. Based on at least one, or at most all, of the associated items of the data in the matching information structure, the memory frequency selector can select an associated memory frequency.

[0061] Figure 5 Example methods 500 for implementing dynamic DDR scaling and use case management based on DDR refresh rate and size, according to various implementation schemes, are illustrated. References Figures 1 to 5 Method 500 can be used in computing devices (e.g., Figure 1 The computing device 10 in Figure 1 and Figure 2 SoC 12 in Figure 2 In system 200), in hardware (e.g., Figure 2 and Figure 3 In the memory interface 34 and memory frequency selector 204, in the processor (e.g., Figure 1 Software executed in the processor 14 and memory interface 34 (e.g., Figure 2 and Figure 3 In the memory frequency selector 204) or in a combination of software-configured processor and dedicated hardware (such as including other individual components such as various memory / caches, e.g., Figure 1 The memory in the 16, 24, Figures 1 to 3 The memory 36 in the memory and various memory / cache controllers (e.g., Figure 1 Memory interface 34 in Figure 2 and Figure 3 The memory subsystem 206 in the system (e.g., Figure 2The system 500 is implemented in the system 200. To cover alternative configurations implemented in various implementations, the hardware implementing method 500 is referred to herein as a "memory frequency device".

[0062] In block 502, the memory frequency device can receive memory (e.g., Figures 1 to 3 The memory refresh rate of the memory (36) in the memory subsystem. This can be achieved, for example, via the memory subsystem (e.g., Figure 2 and Figure 3 The memory subsystem 206 in block 502 receives the memory refresh rate from the memory. The memory refresh rate can be a proxy for the temperature conditions of the memory, as the memory can be configured with temperature thresholds at which the memory refresh rate can be increased and / or decreased. In some embodiments, the memory frequency device receiving the memory refresh rate in block 502 can be a processor (e.g., ...). Figure 1 The processor 14) and / or memory frequency selector (e.g., Figure 2 and Figure 3 (Memory frequency selector 202 in the memory).

[0063] In box 504, the memory frequency device can compare memory characteristics and use case parameters with stored data of stored memory characteristics and stored use case parameters. Use case parameters can be obtained from use case modules (e.g., Figure 2 and Figure 3 The use case module 202 in the document receives, and may be, parameters for the appropriate functionality of the use case implemented in the memory. (This document references...) Figure 6A and Figure 6B Methods 600a and 600b further describe comparing memory characteristics and use case parameters with stored data. In some embodiments, the memory frequency device that compares memory characteristics and use case parameters with stored data in block 504 may be a processor and / or a memory frequency selector.

[0064] The use case parameters used in box 504 may include at least one use case bandwidth (such as the current bandwidth of the use case at a certain time and the average bandwidth of the use case over a certain period of time) and use case latency. The memory characteristics used in box 504 may include the memory refresh rate received in box 502 and the memory size, which may be pre-programmed.

[0065] The stored data compared in box 504 may include data stored in an information structure (e.g., Figure 4The data at information structure 400 is configured to associate the memory characteristics and use case parameters of the storage with the memory frequency configured to perform the appropriate functions of the memory in implementing the use cases. For example, the use case parameters of the storage may include at least one use case bandwidth of the storage (such as the current bandwidth of the use case at a given time and the average bandwidth of the use case over a given period) and the use case latency of the storage. Memory characteristics may include the memory refresh rate and the memory size of the storage.

[0066] In box 506, the memory frequency device may select a memory frequency based on the results of a comparison. Matching all items associated with a memory frequency may result in the selection of a memory frequency. Failure to match at least one item associated with any memory frequency may result in the selection of the maximum memory frequency for the memory. (References) Figure 6A and Figure 6B Methods 600a and 600b further describe the selection of memory frequency based on the comparison results. In some embodiments, the memory frequency device for selecting the memory frequency based on the comparison results in block 506 may be a processor and / or a memory frequency selector.

[0067] In block 508, the memory frequency device can configure the memory for a memory frequency. The memory frequency can be a memory frequency selected in block 506. The memory frequency device can generate a signal indicating the memory frequency used to configure the memory and transmit that signal to the memory subsystem. Transmitting the signal indicating the memory frequency prompts the memory subsystem to configure the memory for that memory frequency. In some embodiments, the memory frequency device configuring the memory for a memory frequency in block 508 may include a processor, a memory frequency selector, and / or the memory subsystem.

[0068] In optional block 510, the memory frequency device may issue an alarm signal configured to indicate a change in the use case to enable the memory to implement use case parameters for the appropriate use case functionality. Implementation of block 510 may be optional, as it may respond to a failure to match at least one item associated with any memory frequency in block 506. The memory frequency device may generate the alarm signal and transmit it to a use case module that can respond by changing the use case and transmitting use case parameters and / or representations of those parameters (such as use case IDs) to the memory frequency device. In some embodiments, the memory frequency device issuing the alarm signal in block 510 may include a processor and / or a memory frequency selector.

[0069] Figure 6A and Figure 6BExample methods 600a and 600b, based on various implementation schemes, are illustrated for implementing dynamic DDR scaling and use case management based on DDR refresh rate and size. References Figures 1 to 6B Methods 600a and 600b can be used in computing devices (e.g., Figure 1 The computing device 10 in Figure 1 and Figure 2 SoC 12 in Figure 2 In system 200), in hardware (e.g., Figure 2 and Figure 3 In the memory interface 34 and memory frequency selector 204, in the processor (e.g., Figure 1 Software executed in the processor 14 and memory interface 34 (e.g., Figure 2 and Figure 3 In the memory frequency selector 204) or in a combination of software-configured processor and dedicated hardware (such as including other individual components such as various memory / caches, e.g., Figure 1 The memory in the 16, 24, Figures 1 to 3 The memory 36 in the memory and various memory / cache controllers (e.g., Figure 1 Memory interface 34 in Figure 2 and Figure 3 The memory subsystem 206 in the system (e.g., Figure 2 The system 600 is implemented in system 200). To cover alternative configurations implemented in various implementation schemes, the hardware implementing methods 600a and 600b is referred to herein as a "memory frequency device".

[0070] Blocks 602-608 of methods 600a and 600b can be implemented in a similar manner, and unless otherwise stated, refer to [reference needed]. Figure 6A and Figure 6B Methods 600a and 600b are described once. Blocks 602-608 can be implemented in any order, and any one of blocks 602-608 can be implemented serially and / or in parallel.

[0071] In box 602, the memory frequency device can be identified as a memory (e.g., Figures 1 to 3 The memory refresh rate of the memory (36) in the memory matches the memory refresh rate of the storage. This can be achieved from the information structure (e.g., Figure 4 The memory refresh rate is retrieved from the information structure 400 in the document. This information structure is configured to associate the memory characteristics and use case parameters of the memory with the appropriate memory frequency configured for the memory implementation use case. The memory refresh rate can be found in the reference document. Figure 5The memory refresh rate received in block 502 of the described method 500. A memory frequency device may compare at least one stored memory refresh rate with a memory refresh rate to identify which at least one stored memory refresh rate matches the memory refresh rate. In some embodiments, the memory frequency device identifying the stored memory refresh rate that matches the memory refresh rate in block 602 may be a processor (e.g., Figure 1 The processor 14) and / or memory frequency selector (e.g., Figure 2 and Figure 3 (Memory frequency selector 202 in the memory).

[0072] In block 604, the memory frequency device can identify the memory size of a storage device that matches the memory size of the memory device. The memory size of a storage device can be retrieved from an information structure, and the memory size can be programmed into the memory frequency device. The memory frequency device can compare the memory size of at least one storage device with the memory size to identify which at least one storage device's memory size matches the memory size. In some embodiments, the memory frequency device identifying the memory size of a storage device that matches the memory size in block 604 can be a processor and / or a memory frequency selector.

[0073] In box 606, the memory frequency device can identify at least one storage use case bandwidth that matches at least one use case bandwidth. The at least one storage use case bandwidth may include the current bandwidth of the storage use case at a given time, which can be retrieved from the information structure, and / or the average bandwidth of the storage use cases over a given period. The at least one use case bandwidth may include bandwidth that can be retrieved from use case modules (e.g., Figure 2 and Figure 3 The use case module 202 receives the current bandwidth of the use cases at a certain time and / or the average bandwidth of the use cases over a certain period. The memory frequency device can compare at least one stored use case bandwidth with at least one use case bandwidth to identify which at least one stored use case bandwidth matches at least one use case bandwidth. In some embodiments, the memory frequency device that identifies the at least one stored use case bandwidth that matches at least one use case bandwidth in block 606 can be a processor and / or a memory frequency selector.

[0074] In block 608, the memory frequency device can identify at least one stored use case delay that matches a use case delay. At least one stored use case delay can be retrieved from an information structure. The use case delay can be received from a use case module. The memory frequency device can compare at least one stored use case delay with a use case delay to identify which at least one stored use case delay matches the use case delay. In some embodiments, the memory frequency device identifying at least one stored use case delay matching a use case delay in block 608 can be a processor and / or a memory frequency selector.

[0075] refer to Figure 6A In block 610, the memory frequency device may identify a stored memory frequency associated with a stored memory refresh rate, a stored memory size, a used-case bandwidth of at least one stored memory, and a used-case latency of at least one stored memory. The information structure may be configured to associate the stored memory refresh rate, the stored memory size, the used-case bandwidth of at least one stored memory, and the used-case latency of at least one stored memory with a memory frequency configured for the appropriate function of the memory to implement a used case. The memory frequency device may identify the stored memory refresh rate, the stored memory size, the used-case bandwidth of at least one stored memory, and the used-case latency based on a comparison with the memory refresh rate, the memory size, the used-case bandwidth of at least one stored memory, and the used-case latency of at least one stored memory. In some embodiments, the memory frequency device identifying the stored memory frequency associated with the stored memory refresh rate, the stored memory size, the used-case bandwidth of at least one stored memory, and the used-case latency of at least one stored memory in block 610 may be a processor and / or a memory frequency selector.

[0076] refer to Figure 6B In block 612, the memory frequency device can identify the maximum memory frequency and generate an alarm signal in response to failure to identify at least one memory use case bandwidth and / or at least one memory use case delay. Failure to identify at least one memory use case bandwidth and / or at least one memory use case delay may be a result of a mismatch between the memory refresh rate, memory size, at least one memory use case bandwidth, and at least one memory use case delay, and the memory refresh rate, memory size, at least one memory use case bandwidth, and at least one memory use case delay. Therefore, there may not be a memory frequency available for the memory to utilize at least one memory use case bandwidth and at least one memory use case delay to perform the function of the use case.

[0077] However, there may be memory frequencies available for the memory to utilize at least one different use case bandwidth and / or different use case latency to achieve the appropriate functionality of the use case. Alarm signals can be configured to alert to changes in the use case. Although the memory configuration may not meet at least one use case bandwidth and / or use case latency, the memory may be configured with a maximum frequency to achieve the highest possible performance in terms of bandwidth and / or latency. In some embodiments, the memory frequency device that identifies the maximum memory frequency in block 612 and generates an alarm signal in response to the failure to identify at least one use case bandwidth and / or at least one use case latency of the memory can be a processor and / or a memory frequency selector.

[0078] According to various implementation plans (including but not limited to the references above) Figures 1 to 6B The system described in the implementation scheme can be implemented in a wide variety of computing systems, including mobile computing devices, and examples of such mobile computing devices suitable for use with various implementation schemes are shown in Figure 7 The mobile computing device 700 may include a processor 702 coupled to a touchscreen controller 704 and internal memory 706. The processor 702 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 706 may be volatile or non-volatile memory, and may also be secure and / or encrypted memory, or insecure and / or unencrypted memory, or any combination thereof. Examples of available memory types include, but are not limited to, DDR, low-power DDR (LPDDR), graphics DDR (GDDR), Wide-Input DDR, RAM, static RAM (SRAM), dynamic RAM (DRAM), parametric RAM (P-RAM), resistive RAM (R-RAM), magnetoresistive RAM (M-RAM), spin-transfer torque RAM (STT-RAM), and embedded DRAM. The touchscreen controller 704 and processor 702 may also be coupled to a touchscreen panel 712, such as a resistive-sensing touchscreen, a capacitive-sensing touchscreen, an infrared-sensing touchscreen, etc. Additionally, the display of the mobile computing device 700 does not need to have touchscreen capability.

[0079] Mobile computing device 700 may have one or more radio transceivers 708 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 710 coupled to each other and / or coupled to processor 702 for transmitting and receiving communications. The transceivers 708 and antennas 710 may be used with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. Mobile computing device 700 may include a cellular wireless modem chip 716 that enables communication via a cellular network and is coupled to the processor.

[0080] Mobile computing device 700 may include a peripheral device connection interface 718 coupled to processor 702. The peripheral device connection interface 718 may be configured individually to accept one type of connection, or it may be configured to accept various types of shared or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 718 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0081] The mobile computing device 700 may also include a speaker 714 for providing audio output. The mobile computing device 700 may also include a housing 720 for accommodating all or some of the components described herein, the housing being constructed of plastic, metal, or a combination of materials. The mobile computing device 700 may include a power source 722 coupled to the processor 702, such as a disposable battery or a rechargeable battery. The rechargeable battery may also be coupled to a peripheral device connection port to receive charging current from a source external to the mobile computing device 700. The mobile computing device 700 may also include a physical button 724 for receiving user input. The mobile computing device 700 may also include a power button 726 for turning the mobile computing device 700 on and off.

[0082] According to various implementation plans (including but not limited to the references above) Figures 1 to 6B The system described in the implementation scheme can be implemented in a wide variety of computing systems, including a laptop computer 800, an example of which is... Figure 8 The following is an example. Many laptop computers include a touchpad touch surface 817, which serves as a pointing device for the computer and is therefore capable of receiving gestures similar to those implemented on computing devices equipped with touchscreen displays and as described above. A laptop computer 800 will typically include a processor 802 coupled to volatile memory 812 and a disk drive 813 containing mass non-volatile memory such as flash memory. Additionally, the computer 800 may have one or more antennas 808 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or to a cellular transceiver 816 coupled to the processor 802. The computer 800 may also include a floppy disk drive 814 and a compact disc (CD) drive 815 coupled to the processor 802. In a laptop configuration, the computer casing includes a touchpad 817, a keyboard 818, and a display 819, all coupled to the processor 802. Other configurations of the computing device may include a computer mouse or trackball, which are well known to be coupled to the processor (e.g., via USB input), and may also be used in combination with various implementation schemes.

[0083] According to various implementation plans (including but not limited to the references above) Figures 1 to 6BThe system described in the implementation scheme can also be implemented in a fixed computing system, such as any of a variety of commercially available servers. Figure 9 Example server 900 is illustrated. Such a server 900 typically includes one or more multi-core processor assemblies 901 coupled to volatile memory 902 and mass non-volatile memory (such as disk drives 904). Figure 9 As illustrated, a multi-core processor assembly 901 can be added to a server 900 by inserting them into the rack of the assembly. The server 900 may also include a floppy disk drive, compact disc (CD), or digital multi-disc (DVD) drive 906 coupled to the processor 901. The server 900 may also include a network access port 903 coupled to the multi-core processor assembly 901 for establishing a network interface connection to a network 905, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0084] According to various implementation plans (including but not limited to the references above) Figures 1 to 6B The methods described in the implementation scheme and the apparatus for implementing such methods can be implemented in a wide variety of computing systems, including the embedded vehicle computing system 1000, an example of which is shown in [example of embedded vehicle computing system 1000]. Figures 10A to 10C The embedded vehicle computing system 1000 may include a vehicle control unit 1040 (such as an ECU), which may include a processor, such as a CPU, AI processor, etc. The embedded vehicle computing system 1000 may include multiple sensors 1042-1070, including a satellite GNSS receiver 1042, an accelerometer 1044, occupancy sensors 1046, 1048, 1050, 1052, tire pressure sensors 1054, 1056, a camera 1058, 1060, a microphone 1062, 1064, an impact sensor 1066, and external sensors 1068, 1070.

[0085] Multiple sensors 1042 to 1070 installed in or on a vehicle can be used for various purposes, such as navigation, collision avoidance, and providing sensor data about objects and people in or on the vehicle. Sensors 1042 to 1070 may include one or more of a wide variety of sensors capable of detecting various types of information useful for navigation and collision avoidance. Each sensor 1042 to 1070 may communicate wiredly or wirelessly with the control unit 1040 and with each other. Specifically, sensors may include one or more cameras 1058, 1060, or other optical or photoelectric sensors. Sensors may also include other types of object detection and ranging sensors, such as external sensors 1068, 1070, IR sensors, and ultrasonic sensors. Sensors may also include tire pressure sensors 1054, 1056, humidity sensors, temperature sensors, satellite GNSS receivers 1042, control input sensors 1045, accelerometers 1044, vibration sensors, gyroscopes, gravimeters, impact sensors 1066, force gauges, stress gauges, strain sensors, fluid sensors, chemical sensors, gas content analyzers, pH sensors, radiation sensors, Geiger counters, neutron detectors, biomaterial sensors, microphones 1062, 1064, occupancy sensors 1046, 1048, 1050, 1052, proximity sensors, and other sensors.

[0086] The vehicle control unit 1040 may include one or more processors configured with processor-executable instructions to perform navigation and collision avoidance operations using information received from various sensors, particularly cameras 1058 and 1060. In some embodiments, the control unit 1040 may supplement the processing of camera images with distance and relative positioning (e.g., relative azimuth) available from external sensors 1068 and 1070. The control unit 1040 may be further configured to control the steering, braking, and speed of the vehicle using information about other vehicles determined using various embodiments. The vehicle control unit 1040 may include one or more processors configured with processor-executable instructions to receive information from sensors 1042 through 1070 and perform operations using such information, as further described herein. In various embodiments, the vehicle control unit 1040 may include V2X onboard equipment of the vehicle, may be a component of the vehicle's V2X onboard equipment, or may communicate with the vehicle's V2X onboard equipment.

[0087] Figure 10CThis is a component block diagram illustrating an embedded vehicle computing system 1000, including components and support systems, suitable for implementing various embodiments. The embedded vehicle computing system 1000 may include a control unit 1040, which may include various circuitry and devices for controlling the operation of the vehicle. The control unit 1040 may include a processor 1040a (such as a CPU, AI processor, etc.), a memory 1040b, an input module 1040c, an output module 1040d, and a radio module 1040e. The control unit 1040 may be coupled to a driving control component 1072a, a navigation component 1072b, and one or more sensors 1072c of the embedded vehicle computing system 1000, and is configured to control these driving control components, the navigation components, and the one or more sensors. The control unit 1040 may communicate with V2X onboard equipment 1040f. The processor 1040a may be configured with processor-executable instructions to control the maneuvering, navigation, and / or other operations of the vehicle, including operations in various embodiments, including acquiring and analyzing real-world vehicle operation data collected from the sensors 1072c. Processor 1040a may be coupled to memory 1040b. V2X onboard equipment 1040f may include one or more processors 1040g, which are configured with processor-executable instructions to perform various operations of various implementations, including transmitting real-world vehicle operation data acquired from sensor 1072c between embedded vehicle computing system 1040 and computing devices on wireless communication device 1012 and / or communication network (e.g., core network 1032) via radio module 1040e.

[0088] Radio module 1040e can be configured for wireless communication. Radio module 1040e can exchange signals (e.g., command signals for controlling maneuver, signals from navigation facilities, data signals, etc.) with a network transceiver (e.g., base station 1010) via communication link 1022, and can provide these signals to processors 1040a, 1040g, and / or navigation unit 1072b. In some embodiments, radio module 1040e enables embedded vehicle computing system 1000 to communicate with wireless communication device 1012 via wireless communication link 1024. Wireless communication link 1024 can be a bidirectional or unidirectional communication link and can use one or more communication protocols.

[0089] The input module 1040c can receive sensor data from one or more vehicle sensors 1072c and electronic signals from other components, including the driving control component 1072a and the navigation component 1072b. The output module 1040d can communicate with or activate various components of the embedded vehicle computing system 1000, including the driving control component 1072a, the navigation component 1072b, and the sensors 1072c.

[0090] Control unit 1040 may be coupled to driving control component 1072a to control physical elements of the vehicle related to its maneuverability and navigation, such as engine, motor, throttle, steering elements, flight control elements, braking or deceleration elements, etc. Driving control component 1072a may also include components for controlling other devices of the vehicle, including interior environmental controls (e.g., air conditioning and heating), exterior and / or interior lighting, interior and / or exterior information displays (which may include displays or other devices for displaying information), safety devices (e.g., haptic devices, auditory alarms, etc.), and other similar devices.

[0091] Control unit 1040 may be coupled to navigation component 1072b and may receive data from navigation component 1072b and be configured to use such data to determine the current position and orientation of the vehicle, as well as the appropriate route toward the destination. Navigation component 1072b may include or be coupled to a GNSS receiver system (e.g., one or more Global Positioning System (GPS) receivers) that enables embedded vehicle computing system 1000 to use GNSS signals to determine its current location. Alternatively or additionally, navigation component 1072b may include radio navigation receivers for receiving navigation beacons or other signals from radio nodes (such as Wi-Fi access points, cellular network sites, radio stations, telecomputing devices, other vehicles, etc.). Through control of driving control element 1072a, processor 1040a may control the vehicle for navigation and maneuvering. Processors 1040a, 1040g and / or navigation component 1072b may be configured to communicate with network elements (such as servers in a communication network (e.g., core network 1032)) via wireless communication links 1022, 1026 to receive commands for controlling maneuvers, receive useful data in navigation, provide real-time positioning reports, etc.

[0092] The control unit 1040 may be coupled to one or more sensors 1072c. The sensors 1072c may include sensors 1042 to 1070 as described, and may be configured to provide various data to processors 1040a, 1040g.

[0093] Although the control unit 1040 is described as comprising separate components, in some embodiments, some or all of the components (e.g., processor 1040a, memory 1040b, input module 1040c, output module 1040d, and radio module 1040e) may be integrated into a single device or module (such as a SoC processing device). Such a SoC processing device may be configured for use in a vehicle and is configured to have processor-executable instructions, such as those executed in processor 1040a, to perform navigation and collision avoidance operations.

[0094] The following paragraphs describe specific implementation examples. While some of the specific implementation examples described below are based on example systems, devices, or methods, other example implementations may include: example systems or devices implemented as methods for performing operations of example systems or devices, as discussed in the following paragraphs; example systems, devices, or methods implemented by computing devices including processing devices configured with processing device-executable instructions and / or memory frequency devices to perform operations of example systems, devices, or methods, as discussed in the following paragraphs; memory frequency devices configured to perform operations of example systems, devices, or methods; computing devices configured to perform operations of example systems, devices, or methods; example systems, devices, or methods implemented by computing devices, as discussed in the following paragraphs, the computing devices including components for performing the functions of example systems, devices, or methods; and example systems, devices, or methods implemented as non-transitory processor-readable storage media storing processor-executable instructions thereon, these processor-executable instructions being configured to cause the processor of the computing device to perform operations of the example systems, devices, or methods, as discussed in the following paragraphs.

[0095] Example 1. A method for scaling the memory frequency configuration of a memory of a computing device, the method comprising: comparing at least a memory refresh rate, a memory size, at least one use case bandwidth for transmission between the memory and a system on-chip (SoC), and a use case latency for transmission between the memory and the SoC with at least one storage's memory refresh rate, at least one storage's memory size, at least one storage's use case bandwidth for transmission between the memory and the SoC, and at least one storage's use case latency for transmission between the memory and the SoC; selecting a memory frequency based on the result of the comparison; and configuring the memory for the memory frequency.

[0096] Example 2. According to the method described in Example 1, wherein: the at least one use case bandwidth includes the current bandwidth of the use case and the average bandwidth of the use case; and the at least one stored use case bandwidth includes the stored current bandwidth of the use case and the stored average bandwidth of the use case.

[0097] Example 3. The method according to any one of Examples 1 or 2, the method further comprising: identifying a memory refresh rate of a storage that matches the memory refresh rate; identifying a memory size of a storage that matches the memory size; identifying a use case bandwidth of the at least one storage that matches the at least one use case bandwidth; identifying a use case latency of the at least one storage that matches the use case latency, wherein the result of the comparison includes the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage; and identifying the memory frequency stored in association with the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage.

[0098] Example 4. The method according to any one of Examples 1 to 3, the method further comprising identifying a maximum memory frequency as the memory frequency in response to failure to identify at least one of the at least one storage use case bandwidth matching the at least one use case bandwidth or the at least one storage use case latency matching the at least one use case latency, wherein the result of the comparison includes less than all of the at least one storage use case bandwidth matching the at least one use case bandwidth or the at least one storage use case latency matching the at least one use case latency.

[0099] Example 5. The method according to any one of Examples 1 to 4, the method further includes issuing an alarm signal, the alarm signal being configured to indicate a change in the use case so that the memory can implement the use case parameters.

[0100] Example 6. The method according to any one of Examples 1 to 5, the method further includes receiving the memory refresh rate from the memory subsystem.

[0101] Example 7. The method according to any one of Examples 1 to 6, the method further includes sending a memory frequency modification signal to the memory subsystem.

[0102] Computer program code or "program code" intended to be executed on a programmable processor to perform operations of various implementation schemes may be written in a high-level programming language (such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic), a structured query language (such as Transact-SQL), Perl, or in a variety of other programming languages. As used herein, program code or program stored on a computer-readable storage medium may refer to machine language code (such as object code) in a format that is understandable by a processor.

[0103] The foregoing method descriptions and process flowcharts are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As those skilled in the art will appreciate, the operations of the foregoing embodiments can be performed in any order. Words such as “afterward,” “then,” “next,” etc., are not intended to restrict the order of operations; these words are only used to guide the reader through the description of the method. Furthermore, any reference to singular claim elements (e.g., references using the articles “a,” “an,” or “described”) should not be construed as limiting that element to the singular.

[0104] The various exemplary logic blocks, modules, circuits, and algorithmic operations described in conjunction with various implementation schemes can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. While those skilled in the art may implement the described functionality in different ways for each specific application, such implementation decisions should not be construed as departing from the scope of the claims.

[0105] Hardware used to implement the various exemplary logics, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0106] In one or more embodiments, the described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operation of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium can be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media can include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above can also be included within the scope of non-transitory computer-readable and processor-readable media. In addition, the operation of a method or algorithm may reside as a single piece of code and / or instruction, or any combination or set of code and / or instructions, on a non-transitory processor-readable medium and / or computer-readable medium that may be incorporated into a computer program product.

[0107] The above description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and implementations without departing from the scope of the claims. Therefore, this disclosure is not intended to be limited to the embodiments and implementations described herein, but should be granted the broadest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method for scaling the memory frequency configuration of a memory of a computing device, the method comprising: A real-time test case parameter set is obtained when the test case is executed by the computing device, wherein the real-time test case parameter set includes... The minimum memory refresh rate of the memory, The memory size of the memory, At least one use case bandwidth for transmission between the memory and the system-on-chip (SoC), and Use case latency for transmission between the memory and the SoC; The real-time test case parameter set is compared with the stored test case parameter set, wherein the stored test case parameter set includes... At least one memory refresh rate, At least one storage memory size, The bandwidth of at least one storage use case for transmission between the memory and the SoC, and The use case latency of at least one storage transmission between the memory and the SoC; The memory frequency is selected based on the results of the comparison. as well as The memory is configured to operate at the memory frequency for use by the computing device to execute the use case.

2. The method according to claim 1, wherein: The at least one use case bandwidth includes the current bandwidth of the use case and the average bandwidth of the use case; and The bandwidth of the at least one stored use case includes the current bandwidth of the stored use case and the average bandwidth of the stored use case.

3. The method according to claim 1, further comprising: The memory refresh rate that identifies the storage that matches the memory refresh rate; The memory size that identifies the storage that matches the memory size; Identify the bandwidth of the at least one stored use case that matches the bandwidth of the at least one use case; Identify the use case latency of the at least one storage that matches the use case latency, wherein the result of the comparison includes the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage; as well as The memory frequency is identified as being stored in association with the memory refresh rate of the stored memory, the memory size of the stored memory, the use case bandwidth of the at least one stored memory, and the use case latency of the at least one stored memory.

4. The method of claim 1, further comprising identifying a maximum memory frequency as the memory frequency in response to failure to identify at least one of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency, wherein the result of the comparison includes less than all of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency.

5. The method of claim 1, further comprising issuing an alarm signal configured to indicate a change in the use case to enable the memory to implement use case parameters.

6. The method of claim 1, further comprising receiving the memory refresh rate from the memory subsystem.

7. The method according to claim 1, further comprising sending a memory frequency modification signal to the memory subsystem.

8. A computing device, the computing device comprising: Memory frequency device, the memory frequency device being configured to: A real-time test case parameter set is obtained when the test case is executed by the computing device, wherein the real-time test case parameter set includes... The memory refresh rate of the computing device's memory. The memory size of the memory, At least one use case bandwidth for transmission between the memory and the system-on-chip (SoC), and Use case latency for transmission between the memory and the SoC; The real-time test case parameter set is compared with the stored test case parameter set, wherein the stored test case parameter set includes... At least one memory refresh rate, At least one storage memory size, The bandwidth of at least one storage use case for transmission between the memory and the SoC, and The use case latency of at least one storage transmission between the memory and the SoC; The memory frequency is selected based on the results of the comparison. as well as The memory is configured to operate at the memory frequency for use by the computing device to execute the use case.

9. The computing device of claim 8, wherein the memory frequency device is configured such that: The at least one use case bandwidth includes the current bandwidth of the use case and the average bandwidth of the use case; and The bandwidth of the at least one stored use case includes the current bandwidth of the stored use case and the average bandwidth of the stored use case.

10. The computing device of claim 8, wherein the memory frequency device is further configured to: The memory refresh rate that identifies the storage that matches the memory refresh rate; The memory size that identifies the storage that matches the memory size; Identify the bandwidth of the at least one stored use case that matches the bandwidth of the at least one use case; Identify the use case latency of the at least one storage that matches the use case latency, wherein the result of the comparison includes the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage; as well as The memory frequency is identified as being stored in association with the memory refresh rate of the stored memory, the memory size of the stored memory, the use case bandwidth of the at least one stored memory, and the use case latency of the at least one stored memory.

11. The computing device of claim 8, wherein the memory frequency device is further configured to identify a maximum memory frequency as the memory frequency in response to failure to identify at least one of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency, wherein the result of the comparison includes less than all of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency.

12. The computing device of claim 8, wherein the memory frequency device is further configured to issue an alarm signal, the alarm signal being configured to indicate a change in the use case to enable the memory to implement use case parameters.

13. The computing device of claim 8, wherein the memory frequency device is further configured to receive the memory refresh rate from the memory subsystem.

14. The computing device of claim 8, wherein the memory frequency device is further configured to send a memory frequency modification signal to the memory subsystem.

15. A computing device, the computing device comprising: A component for obtaining a real-time set of test case parameters for a test case when the test case is executed by the computing device, wherein the real-time test case parameter set includes... The memory refresh rate of the computing device's memory. The memory size of the memory, At least one use case bandwidth for transmission between the memory and the system-on-chip (SoC), and Use case latency for transmission between the memory and the SoC; A component for comparing the real-time test case parameter set with a stored test case parameter set, wherein the stored test case parameter set includes... At least one memory refresh rate, At least one storage memory size, The bandwidth of at least one storage use case for transmission between the memory and the SoC, and The use case latency of at least one storage transmission between the memory and the SoC; Components used to select the memory frequency based on the results of the comparison; as well as Components for configuring the memory to operate at the memory frequency for executing the use case by the computing device.

16. The computing device according to claim 15, wherein: The at least one use case bandwidth includes the current bandwidth of the use case and the average bandwidth of the use case; and The bandwidth of the at least one stored use case includes the current bandwidth of the stored use case and the average bandwidth of the stored use case.

17. The computing device of claim 15, further comprising: A component used to identify the memory refresh rate of a storage device that matches the memory refresh rate. A component used to identify the memory size that matches the memory size; A component for identifying the bandwidth of at least one stored use case that matches the bandwidth of the at least one use case; A component for identifying the use case latency of the at least one storage that matches the use case latency, wherein the result of the comparison includes the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage; as well as A component for identifying the frequency of the memory stored in association with the memory refresh rate of the stored memory, the memory size of the stored memory, the use case bandwidth of the at least one stored memory, and the use case latency of the at least one stored memory.

18. The computing device of claim 15, further comprising means for identifying a maximum memory frequency as the memory frequency in response to failure to identify at least one of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency, wherein the result of the comparison includes less than all of the use case bandwidth of the at least one storage that matches the at least one use case bandwidth or the use case latency of the at least one storage that matches the at least one use case latency.

19. The computing device of claim 15, further comprising a component for issuing an alarm signal configured to indicate a change in the use case to enable the memory to implement use case parameters.

20. The computing device of claim 15, further comprising a component for receiving the memory refresh rate from the memory subsystem.

21. The computing device of claim 15, further comprising a component for sending a memory frequency modification signal to a memory subsystem.

22. A non-transitory processor-readable medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a memory frequency device of a computing device to perform an operation, the operation comprising: A real-time test case parameter set is obtained when the test case is executed by the computing device, wherein the real-time test case parameter set includes... The memory refresh rate of the computing device's memory. The memory size of the memory, At least one use case bandwidth for transmission between the memory and the system-on-chip (SoC), and Use case latency for transmission between the memory and the SoC; The real-time test case parameter set is compared with the stored test case parameter set, wherein the stored test case parameter set includes... At least one memory refresh rate, At least one storage memory size, The bandwidth of at least one storage use case for transmission between the memory and the SoC, and The use case latency of at least one storage transmission between the memory and the SoC; The memory frequency is selected based on the results of the comparison. as well as The memory is configured to operate at the memory frequency for use by the computing device to execute the use case.

23. The non-transitory processor-readable medium according to claim 22, wherein: The at least one use case bandwidth includes the current bandwidth of the use case and the average bandwidth of the use case; and The bandwidth of the at least one stored use case includes the current bandwidth of the stored use case and the average bandwidth of the stored use case.

24. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the memory frequency device to perform an operation, the operation further comprising: The memory refresh rate that identifies the storage that matches the memory refresh rate; The memory size that identifies the storage that matches the memory size; Identify the bandwidth of the at least one stored use case that matches the bandwidth of the at least one use case; Identify the use case latency of the at least one storage that matches the use case latency, wherein the result of the comparison includes the memory refresh rate of the storage, the memory size of the storage, the use case bandwidth of the at least one storage, and the use case latency of the at least one storage; as well as The memory frequency is identified as being stored in association with the memory refresh rate of the stored memory, the memory size of the stored memory, the use case bandwidth of the at least one stored memory, and the use case latency of the at least one stored memory.

25. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the memory frequency device to perform an operation, the operation further comprising identifying a maximum memory frequency as the memory frequency in response to failure to identify at least one of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case delay matching the at least one use case delay, wherein the result of the comparison includes less than all of the at least one stored use case bandwidth matching the at least one use case bandwidth or the at least one stored use case delay matching the at least one use case delay.

26. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the memory frequency device to perform an operation, the operation further comprising issuing an alarm signal configured to indicate a change in the use case to enable the memory to implement use case parameters.

27. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the memory frequency device to perform an operation, the operation further comprising receiving the memory refresh rate from the memory subsystem.

28. The non-transitory processor-readable medium of claim 22, wherein the stored processor-executable instructions are configured to cause the memory frequency device to perform an operation, the operation further comprising sending a memory frequency modification signal to the memory subsystem.

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