Joined body
By controlling the coating amount and heating process of Au-Sn alloy solder, a bonding layer with a thickness of less than 10μm is formed, and the area ratio of irregular voids is limited to less than 15%, thus solving the problem of insufficient bonding strength of Au-Sn alloy solder and achieving excellent bonding strength and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-09
- Publication Date
- 2026-03-13
AI Technical Summary
When using Au-Sn alloy solder for bonding, the thinning of the thin film leads to a decrease in bonding strength, and the formation of voids affects the bonding quality.
By controlling the coating amount and heating process of Au-Sn alloy solder, the thickness of the bonding layer is ensured to be less than 10 μm, and the area ratio of irregular voids is limited to less than 15%. At the same time, an Au-free metallization layer is formed on the bonding surface to suppress void formation.
It achieves excellent bonding strength, ensures stable bonding between the first and second components, avoids voids, and improves the reliability of the bonding.
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Figure CN121666901A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a joint body formed by joining a first component and a second component via a bonding layer made of Au-Sn alloy. Background Technology
[0002] For example, various devices such as LEDs or power modules are structures in which electronic components such as semiconductor elements are bonded on a substrate having a circuit layer made of metal parts.
[0003] When bonding electronic components such as semiconductor elements to circuit layers, methods using solder materials made of Au-Sn alloys are widely used, for example, as shown in Patent Document 1.
[0004] Here, when using Au-Sn alloy solder to bond the substrate (circuit layer) to electronic components, in order to ensure wettability with the Au-Sn alloy solder, a thin Au plating layer (Au flash plating layer) is formed on the bonding surface of the substrate (circuit layer).
[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-010152 (A)
[0006] However, due to the extremely high price of Au-Sn alloy solder, it is necessary to reduce the thickness of the bonding layer.
[0007] Here, when reducing the coating amount of Au-Sn alloy solder, forming an Au flash plating layer on the bonding surface and using Au-Sn alloy solder for solder bonding, a large number of voids may be generated in the bonding layer, resulting in a decrease in bonding strength. Summary of the Invention
[0008] The present invention was made in view of the above circumstances, and its object is to provide a joint in which the bonding layer of Au-Sn alloy is formed thinner and the bonding strength is excellent.
[0009] To address the aforementioned issues, the inventors, through in-depth research, discovered that when forming an Au flash plating layer on the bonding surface and using Au-Sn alloy solder for solder bonding, the Au in the flash plating layer mixes into the Au-Sn alloy solder disposed at the bonding interface during bonding heating. This causes the liquid phase composition of the Au-Sn alloy at the bonding interface to shift towards the Au-rich side, thereby increasing its melting point (liquidotherm temperature). Therefore, even when heated and maintained at a specified temperature during bonding, a solid phase forms in the liquid phase of the solder at the bonding interface, reducing the fluidity of the liquid phase and resulting in voids within the bonded layer after bonding, thus reducing the bonding strength. Furthermore, the voids formed in this way exhibit low roundness and a distorted shape. Additionally, the compositional shift becomes more significant with decreasing Au-Sn solder coating thickness.
[0010] The present invention is based on the above insights. The joint of the present invention is a joint formed by joining a first component and a second component via a joint layer. The joint layer is characterized in that the joint layer is made of Au-Sn alloy and the thickness of the joint layer is less than 10 μm. In the joint layer, the area ratio of irregular voids with a roundness of less than 60% is less than 15% of the joint area.
[0011] According to the present invention, since the bonding layer made of Au-Sn alloy is formed to be thin, with a thickness of less than 10 μm, and the area ratio of irregular voids with a roundness of less than 60% is less than 15% of the bonding area, the fluidity of the liquid phase is ensured during bonding heating, and the first component and the second component can be stably bonded, thereby achieving excellent bonding strength between the first component and the second component.
[0012] Here, in the joint of the present invention, it is preferable that the area ratio of voids in the joint layer is less than 25% of the joint area.
[0013] In this case, since the area ratio of voids in the bonding layer is less than 25%, the bonding strength between the first component and the second component is sufficiently excellent.
[0014] Furthermore, in the joint of the present invention, it is preferable to form an Au-free metallization layer on either or both of the joint surfaces of the first component and the second component.
[0015] In this case, even when a metallization layer without Au is formed, the generation of irregular voids is suppressed, and the bonding strength between the first component and the second component is excellent.
[0016] According to the present invention, it is possible to provide a joint in which the bonding layer of Au-Sn alloy is formed relatively thin and the bonding strength is excellent. Attached Figure Description
[0017] Figure 1 This is an explanatory diagram of a joint according to an embodiment of the present invention.
[0018] Figure 2 This is a phase diagram of the Au-Sn alloy.
[0019] Figure 3 This is a flowchart of a method for manufacturing a joint according to an embodiment of the present invention.
[0020] Figure 4 This is an explanatory diagram of a method for manufacturing a joint according to an embodiment of the present invention. Detailed Implementation
[0021] Hereinafter, the assembly of an embodiment of the present invention will be described with reference to the accompanying drawings.
[0022] like Figure 1 As shown, the bonding body 10 involved in this embodiment is formed by bonding a first component 11 and a second component 12 via a bonding layer 13. In this embodiment, the bonding body 10 is a semiconductor device formed by bonding a circuit layer (first component 11) of an insulating circuit board and a semiconductor element (second component 12) via a bonding layer 13. Furthermore, as... Figure 1 As shown, the area of the circuit layer (first component 11) of the insulating circuit board is larger than the area of the semiconductor element (second component 12).
[0023] Here, the circuit layer (first component 11) is made of a metal with excellent conductivity, such as copper or copper alloy, aluminum or aluminum alloy, iron or iron alloy. In this embodiment, it is made of an iron alloy (Kovar alloy).
[0024] Here, an Au-free metallization layer 11a (a metallization layer 11a composed of a metal or alloy that does not contain Au) can be formed on the bonding surface of the circuit layer (first component 11). Examples of Au-free metallization layers 11a include layers (films) composed of Ni, Pd, Ag, Cu, etc.
[0025] Furthermore, a noble metal film such as Au can be formed on the bonding surface of the semiconductor element (second component 12).
[0026] In this embodiment, the bonding layer 13 is made of an Au-Sn alloy. Furthermore, the thickness t of the bonding layer 13 is 10 μm or less. Preferably, the thickness t of the bonding layer 13 is 10 μm or less, and more preferably 4 μm or less.
[0027] Although there are no specific limitations, the thickness t of the bonding layer 13 can be 0.1 μm or more.
[0028] Here, in Figure 2 The diagram shows the phase profile of the Au-Sn alloy. Figure 2 As shown, the Au-Sn alloy is a eutectic alloy that undergoes a eutectic reaction. The Au-20 mass%Sn has a eutectic composition and a melting point at the eutectic temperature of 278℃.
[0029] Au-Sn alloys are Au-based alloys containing 18% by mass and less than 25% by mass of Sn.
[0030] Furthermore, in the joint body 10 of this embodiment, the area ratio of voids (irregular voids) with a roundness C of 60% or less in the joint layer 13 is less than 15% of the joint area.
[0031] Furthermore, in the joint body 10 of this embodiment, the area ratio of the voids (vacuums) in the joint layer 13 (i.e., the area ratio of all voids including irregular voids) is preferably less than 25% of the joint area.
[0032] Here, regarding the roundness C of the cavity, from the direction opposite to the mating surface ( Figure 1 (Observe the joint layer 13 in the direction of arrow A) and define it as follows based on the area A1 of the cavity and the area A0 of the circle drawn with the two furthest points in the outline of the cavity as diameters.
[0033] The roundness C (%) of the cavity = A1 / A0 × 100
[0034] Furthermore, regarding the area ratio of the irregular cavity and the area ratio of all cavities containing the irregular cavity, from the direction opposite to the joint surface ( Figure 1 (Observe the bonding layer 13 in the direction of arrow A) and calculate.
[0035] Observation was performed, for example, using an ultrasonic flaw detector (Hitachi Power Solutions Co., Ltd. FSP8V) with an observation field of view of 1.5mm × 1.5mm.
[0036] Here, the area ratio of irregularly shaped cavities with a roundness C of 60% or less is preferably 15% or less of the joint area, more preferably 10% or less.
[0037] Although there are no specific restrictions, the area ratio of irregularly shaped voids can be above 0.1%.
[0038] Furthermore, the area ratio of the voids (including the area ratio of all voids, including irregular voids) is more preferably 25% or less of the joint area, and even more preferably 15% or less.
[0039] Although there are no specific restrictions, the area ratio of the void can be above 0.2%.
[0040] Next, refer to Figure 3 and Figure 4 The manufacturing method of the joint 10 of this embodiment will be described.
[0041] (First component preparation process S01)
[0042] First, prepare the first component 11 to be joined. For example... Figure 4 As shown, an Au-free metallization layer 11a can be formed on the surface of the first component 11.
[0043] Then, and as Figure 4 As shown, an Au flash plating layer 21 may also be further formed on the bonding surface of the first component 11 (between the solder material 23 and the Au-free metallization layer 11a) as needed. Here, the thickness t0 of the Au flash plating layer 21 is preferably 10 nm or less, and more preferably 4 nm or less.
[0044] (Solder coating process S02)
[0045] Next, as Figure 4 As shown, solder material 23 is applied to one or both of the mating surfaces of the first component 11 and the second component 12. The application method is not particularly limited and can include, for example, metal masking, screen printing, or dispensing.
[0046] Here, for example, when using the dispensing method, the coating amount of solder material 23 is preferably in the range of 0.2 nL or more and 50 nL or less.
[0047] Furthermore, when an Au flash plating layer 21 is formed on the bonding surface of the first component 11, the ratio t0 / t of the thickness t0 of the Au flash plating layer 21 to the thickness t of the bonding layer 12 after bonding is preferably 0.003 or less, more preferably 0.001 or less. In addition, when the Au flash plating layer 21 is not formed, t0 / t is 0.
[0048] Furthermore, the thickness t0 of the Au flash plating layer 21 after bonding can be determined by measuring the area other than the area where the first component 11 and the second component 12 are bonded. In this embodiment, the thickness t0 of the Au flash plating layer 21 can be determined by measuring the outer surface of the area where the semiconductor element (second component 12) is bonded in the circuit layer (first component 11).
[0049] Solder material 23 is a solder material containing metal powder and flux (solvent, thixotropic agent, activator, resin).
[0050] The metal powder can be an alloy powder or a mixed powder. In this embodiment, it is a mixed powder of Au powder and Sn powder. Furthermore, the mixing ratio of the mixed powder is Au:Sn = 78:22 by mass. That is, the solder material 23 in this embodiment is Au - 22%Sn by mass.
[0051] Solvents used in fluxes include, for example, alcohols, ketones, esters, ethers, aromatic compounds, hydrocarbons, terpenes, and terpenes. Specifically, benzyl alcohol, ethanol, ethyl alcohol, isopropanol, butanol, diethylene glycol, ethylene glycol, ethyl cellosolve, butyl cellosolve, butyl carbitol, isopropanol, ethyl acetate, butyl acetate, butyl benzoate, diethyl adipate, dodecane, tetradecene, α-terpineol, 2-methyl-2,4-pentanediol, 2-ethyl-1,3-hexanediol, toluene, xylene, propylene glycol monophenyl ether, diethylene glycol monohexyl ether, ethylene glycol monobutyl ether, diethylene glycol monobutyl ether, diisobutyl adipate, hexanediol, cyclohexanediol, 2-terpinenoxyethanol, 2-dihydroterpinenoxyethanol, citral, linalool, limonene, carvacrol, pinene, farnesene, etc., or mixtures thereof can be used alone.
[0052] As a thixotropic agent, it can be used alone, such as hydrogenated castor oil, hydrogenated castor oil, carnauba wax, amides, hydroxy fatty acids, dibenzylidene sorbitol, bis(p-methylbenzylidene) sorbitol, beeswax, stearamide, hydroxystearic acid vinylidene diamide, etc., or in combination.
[0053] As surfactants, fatty acids such as adipic acid, caprylic acid, lauric acid, myristic acid, palmitic acid, stearic acid, behenic acid, hydroxy fatty acids such as 1,2-hydroxystearic acid, antioxidants, surfactants, and amines can be added.
[0054] As a resin, it can be made of materials such as polymerized rosin, natural rosin, purified rosin, etc.
[0055] (Lamination process S03)
[0056] Next, as Figure 4 As shown, the first component 11 and the second component 12 are stacked using the aforementioned solder material 23.
[0057] (Jointing process S04)
[0058] Next, as Figure 4 As shown, a liquid phase is generated by heating the first component 11 and the second component 12, which are stacked by solder material 23, and the liquid phase is solidified to form a bonding layer 13, thereby bonding the first component 11 and the second component 12.
[0059] Here, as described above, the solder material 23 is Au-22% Sn by mass. However, when the Au flash plating layer 21 is formed, during heating in the bonding process S04, the Au in the Au flash plating layer 21 mixes with the liquid phase formed by the melting of the solder material 23, thereby causing a compositional deviation on the Au-enriched side, such as... Figure 2 As shown in the state diagram, the liquidus temperature will rise. Therefore, depending on the holding temperature at the time of bonding, a solid phase is generated in the liquid phase during the holding period, the fluidity of the liquid phase will decrease, and irregular voids with a roundness C of less than 60% will be generated.
[0060] Therefore, in this embodiment, when an Au flash plating layer 21 is formed, it is preferable to set the ratio of the thickness t0 of the Au flash plating layer 21 to the thickness t of the bonded layer 12 after bonding to 0.003 or less, and more preferably to 0.001 or less.
[0061] Furthermore, it is preferable not to form an Au flash plating layer 21. However, if an Au flash plating layer 21 is not formed, the wettability of the solder material 23 and the first component 11 may be reduced.
[0062] Therefore, in this embodiment, in the bonding process S04, the heating rate within the temperature range of ±5°C of the melting point of the solder material 23 is set to 0.1°C / min or more and 5°C / min or less, preferably within the range of 0.1°C / min or more and 1°C / min, and the heating rate is set very slowly. As a result, the solder material 23 sufficiently wets the bonding surface of the first component 11.
[0063] In this embodiment, the alloy composition of solder material 23 is Au-22%Sn by mass, and the melting point of this composition is 280°C. Therefore, the heating rate from 275°C to 285°C is set to be in the range of 0.1°C / min or more and 5°C / min or less.
[0064] Furthermore, the holding temperature in the bonding process S04 is preferably within the range of +5°C to +50°C of the melting point of the solder material 23. Specifically, it is preferably within the range of 285°C to 330°C. Further, the holding time at the holding temperature is preferably within the range of 0.5 minutes to 3 minutes.
[0065] Furthermore, during heat treatment, the laminate can be pressurized in the lamination direction with a pressure of 0 MPa or more and 0.0007 MPa or less.
[0066] The joint body 10 of this embodiment is manufactured through the first component preparation process S01, solder material coating process S02, lamination process S03, and bonding process S04 described above.
[0067] According to the joint body 10 of this embodiment with the configuration described above, since the joint layer 13 made of Au-Sn alloy is formed to be relatively thin, with a thickness of 10 μm or less, and the area ratio of irregular voids with a roundness C of 60% or less is less than 15% of the joint area, the fluidity of the liquid phase is ensured during the jointing process S04, and the first component 11 and the second component 12 can be stably joined, thereby resulting in excellent joint strength between the first component 11 and the second component 12.
[0068] Furthermore, in the joint 10 of this embodiment, when the area ratio of voids in the joint layer 13 (including the area ratio of all voids including irregular voids) is less than 25% of the joint area, the joint strength between the first component 11 and the second component 12 is particularly excellent.
[0069] Furthermore, in the joint 10 of this embodiment, even if a metallization layer 11a without Au is formed on the joint surface of the first component 11, the generation of irregular voids in the joint layer 13 is suppressed, and the joint strength between the first component 11 and the second component 12 is excellent.
[0070] The embodiments of the present invention have been described above, but the present invention is not limited thereto, and appropriate changes can be made without departing from the technical concept of the invention.
[0071] Example
[0072] The results of the verification experiments conducted to confirm the effectiveness of the present invention will be described below.
[0073] As the first component, a substrate with a metallization layer as shown in Table 1 formed on the surface of an iron alloy (Kova alloy) plate (250mm × 150mm × 0.1mm thickness) was prepared. Furthermore, an Au flash plating layer as shown in Table 1 was formed on a portion of the bonding surface of the substrate.
[0074] As a second component, a SiC chip (1mm × 1mm × 0.4mm thick) with nickel plating (4μm thickness) on the bonding surface was prepared.
[0075] Furthermore, as the solder material, a slurry composed of Au-22% Sn alloy powder as described in the embodiments and a flux was used. The ratio of metal powder to flux was 50:50 (volume ratio), and a flux composed of polymeric rosin, terpene solvent, amide thixotropic agent, and organic acid activator was used.
[0076] Solder material was applied to the mating surface of the first component using a dispensing device (manufactured by Musashi Engineering, Inc., pneumatic pulse type, nozzle inner diameter 0.25 mm). The amount of solder applied is shown in Table 1. Furthermore, the ratio t0 / t of the thickness t0 of the Au flash plating layer to the thickness t of the bonding layer 12 is shown in Table 1.
[0077] Then, the first component and the second component were joined by maintaining a temperature of 300°C, a holding time of 1 minute, and a pressure of 0 MPa.
[0078] At this point, the heating rate within the temperature range (from 275°C to 285°C) of the solder's melting point (280°C) ± 5°C is set to the conditions shown in Table 1.
[0079] The following items were evaluated for the joints obtained as described above.
[0080] (Thickness of the bonding layer)
[0081] The thickness of the laminated layers was determined by SEM observation of the cross-section along the stacking direction of the joint. The observation was performed at 1000x magnification, and the thickness was measured at five points within one field of view. The average thickness of the five measurements was taken as the thickness of the joint layer and is shown in Table 1.
[0082] (The roundness of the hole)
[0083] Using an ultrasonic flaw detector (Hitachi Power Solutions Co., Ltd. FSP8V), observe the joint layer from the direction opposite to the joint surface, and designate the unjoined portion, indicated in white, as a void. Calculate the roundness C (%) of the void based on the area A1 of the void and the area A0 of the circle drawn with the two furthest points in the void's outline as diameters.
[0084] (Area ratio of irregular voids)
[0085] The bonding layer was observed from the direction opposite to the bonding surface using an ultrasonic flaw detector (FSP8V manufactured by Hitachi Power Solutions Co., Ltd.). Unbonded areas, indicated in white, were designated as voids. The area of irregular voids with a roundness C of 60% or less was then measured and divided by the bonding area (1 mm × 1 mm) to calculate the area ratio of the irregular voids.
[0086] The case where the area ratio of the irregular cavity is less than 10% is designated as "A", the case where the area ratio of the irregular cavity is more than 10% but less than 15% is designated as "B", and the case where the area ratio of the irregular cavity is more than 15% is designated as "C".
[0087] (Area ratio of voids)
[0088] The joint layer was observed from the direction opposite to the joint surface using an ultrasonic flaw detector (FSP8V manufactured by Hitachi Power Solutions Co., Ltd.), and the unjoined areas, indicated in white, were designated as voids. Then, the area of all voids, including irregularly shaped voids, was measured and divided by the joint area (1mm × 1mm) to calculate the area ratio of the voids.
[0089] Cases with a void area ratio of less than 15% are designated as "A", cases with a void area ratio of more than 15% but less than 25% are designated as "B", and cases with a void area ratio of more than 25% are designated as "C".
[0090] (Joint strength)
[0091] The bond strength of the obtained joint was determined using a shear strength evaluation testing machine (RHESCA CO., LTD. BondingTester PTR-1101). For the test, the first component of the joint was horizontally fixed, and a shearing tool was used to press it horizontally from a position 100 μm above the surface of the bond layer. The strength of the second component at fracture was then measured. The shearing tool moved at a speed of 0.1 mm / s. Three tests were performed under each condition, and their arithmetic mean was taken as the measured value.
[0092] Cases with a joint strength of 50 MPa or more are designated as "A", cases with a joint strength of 30 MPa or more but less than 50 MPa are designated as "B", and cases with a joint strength less than 30 MPa are designated as "C".
[0093] [Table 1]
[0094]
[0095] In Comparative Example 1, the thickness t0 of the Au flash coating formed on the bonding surface of the first component is 3.5 nm, and the ratio t0 / t of the Au flash coating thickness t0 to the thickness t of the bonding layer after bonding is 0.0035. In the bonding layer, the area ratio of irregularly shaped voids with a roundness of less than 60% is more than 15%, and the area ratio of voids is more than 25%. As a result, the bonding strength is less than 30 MPa, and the bonding strength is insufficient.
[0096] In Comparative Example 2, the thickness t0 of the Au flash coating formed on the bonding surface of the first component is 10.0 nm, and the ratio t0 / t of the Au flash coating thickness t0 to the thickness t of the bonding layer after bonding is 0.0033. In the bonding layer, the area ratio of irregularly shaped voids with a roundness of less than 60% is more than 15%, and the area ratio of voids is more than 25%. As a result, the bonding strength is less than 30 MPa, and the bonding strength is insufficient.
[0097] In contrast, in Examples 1-10 of the present invention, the thickness of the bonding layer is less than 10 μm, and the area ratio of irregularly shaped voids with a roundness of less than 60% in the bonding layer is more than 15%, and the bonding strength is more than 30 MPa, which is excellent.
[0098] Based on the results of the above confirmation experiments, it has been confirmed that, according to the present invention, it is possible to provide a joint with a thinner bonding layer made of Au-Sn alloy and excellent bonding strength.
[0099] Industrial availability
[0100] It can provide a joint with a thinner bonding layer made of Au-Sn alloy and excellent bonding strength.
[0101] Symbol Explanation
[0102] 10 joints
[0103] 11 First Component
[0104] 11a metallization layer
[0105] 12 Second Component
[0106] 13 bonding layers
[0107] 21Au flash coating
[0108] 23 Welding Materials
Claims
1. A joint body, which is formed by joining a first component and a second component via a bonding layer, characterized in that, The bonding layer is made of Au-Sn alloy, and the thickness of the bonding layer is less than 10 μm. In the bonding layer, the area ratio of irregularly shaped voids with a roundness of less than 60% is less than 15% of the bonding area.
2. The joint according to claim 1, characterized in that, The area ratio of voids in the bonding layer is less than 25% of the bonding area.
3. The joint according to claim 1 or 2, characterized in that, An Au-free metallization layer is formed on either or both of the mating surfaces of the first component and the second component.
Citation Information
Patent Citations
Crystal device
JP2021010152A