A highly configurable radar two-dimensional CFAR detection circuitry

Abstract

This invention provides a highly configurable radar 2D CFAR detection circuit system, comprising: a target detection processor and a 2D CFAR target detection hardware accelerator; the target detection processor is used to send range-Doppler matrix data, configure the parameters of the accelerator through a configuration interface, and receive the detection results of the accelerator; the 2D CFAR target detection hardware accelerator includes a frame data dimensionality reduction module and a sliding window target detection module, used to receive the range-Doppler matrix data, perform frame data dimensionality reduction processing and sliding window target detection according to the configured parameters, and output the target detection results. The beneficial effects of this invention are: by coordinating the target detection processor and the 2D CFAR target detection hardware accelerator with a specific dual-module architecture, high configurability and adaptability to radar parameters in multiple scenarios are achieved while ensuring low power consumption and high real-time performance.

Description

Technical Field

[0001] This invention relates to the field of radar image detection circuit technology, and in particular to a highly configurable radar two-dimensional CFAR detection circuit system. Background Technology

[0002] Millimeter-wave radar transmits frequency-modulated continuous waves and receives target echoes, generating a range-Doppler matrix after one-dimensional and two-dimensional Fast Fourier Transforms (CFARs). The constant false alarm rate (CFAR) detection algorithm, by applying a sliding window to this matrix to distinguish noise from the target, is a crucial step in achieving target detection. Existing one-dimensional CFAR methods only perform detection in a single dimension, which can easily lead to missed detections or increased false alarm rates in scenarios with non-uniform clutter, dense targets, or coexistence of strong and weak targets. Furthermore, they are difficult to flexibly adapt to the needs of different application scenarios.

[0003] To improve processing performance, some solutions use CPUs or GPUs for software processing. While these solutions offer algorithmic flexibility, they are limited by storage bandwidth, caching mechanisms, and thread scheduling. Consequently, they generally suffer from high power consumption, large processing latency jitter, and difficulty in guaranteeing real-time performance and determinism, making it difficult to meet the stringent energy efficiency and real-time requirements of edge devices.

[0004] Another approach is to design dedicated hardware accelerators. However, existing fixed-function hardware accelerators typically have fixed window sizes, data layouts, and boundary processing strategies to optimize area and throughput. Such designs lack configurability when faced with different radar frame structures, channel numbers, or changes in detection parameters, requiring redesign or significant hardware modifications. This results in poor reusability, high development costs, and an inability to adapt to the application requirements of rapid adaptation across multiple scenarios. Summary of the Invention

[0005] The technical problem to be solved by this invention is the core technical problem that existing radar CFAR detection schemes cannot balance hardware flexibility and processing efficiency.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a highly configurable radar two-dimensional CFAR detection circuit system, including: a target detection processor and a two-dimensional CFAR target detection hardware accelerator; The target detection processor is used to send range-Doppler matrix data, configure the parameters of the two-dimensional CFAR target detection hardware accelerator through a configuration interface, and receive the detection results of the two-dimensional CFAR target detection hardware accelerator. The two-dimensional CFAR target detection hardware accelerator includes a frame data dimensionality reduction module and a sliding window target detection module, which are used to receive the range-Doppler matrix data, perform frame data dimensionality reduction processing and sliding window target detection according to the configuration parameters, and output the target detection results.

[0007] Furthermore, the frame data dimensionality reduction module is used to preprocess, channel merge, and power compress the input range-Doppler matrix complex data to generate an energy matrix for CFAR detection. The sliding window target detection module is used to perform sliding window noise estimation and threshold decision on the energy matrix, and output the target detection results and related auxiliary information.

[0008] Furthermore, the frame data dimensionality reduction module includes a preprocessing submodule, a transmit channel merging submodule, a power compression submodule, and a receive channel merging submodule connected in sequence. The preprocessing submodule is used to convert floating-point data into fixed-point data and extract the real and imaginary parts of complex data; The transmission channel merging submodule is used to perform weighted fusion of data from different transmission channel dimensions according to configurable weights; The power compression submodule is used to calculate the energy value of the fused complex data and perform approximate logarithmic operations to achieve dynamic range compression. The receiving channel merging submodule is used to perform weighted fusion of logarithmic energy data from different receiving channel dimensions according to configurable weights, and output the energy matrix.

[0009] Furthermore, the power compression submodule includes a logarithmic operation unit, which is configured to: find the highest non-zero bit of the input energy value as the integer part, and truncate a specific number of bits after the highest bit for logical processing to generate a fractional part with at least 3 significant decimal places, and combine the integer part and the fractional part for output, so as to control the operation error while reducing the data bit width.

[0010] Furthermore, the sliding window target detection module includes a row data caching submodule, a sliding window noise solving submodule, and a data integration submodule; The row data caching submodule uses a streaming cache array composed of multiple RAMs to cache and update the input energy matrix row by row, so as to support fast data access of the sliding window in the two-dimensional neighborhood. The sliding window noise solving submodule is used to perform noise statistics on the training unit and generate a decision threshold based on the configurable sliding window size and boundary pattern. The data integration submodule is used to compare and decide the threshold with the energy of the unit to be detected, and to output the decision result, row and column coordinates, noise estimate, energy value and frame target number in a structured manner.

[0011] Furthermore, the row data caching submodule includes a pipelined row cache array consisting of ref_A+1 RAMs, additional RAM for caching the boundary data of the preceding ref_A-1 rows, and read / write control logic; Wherein, ref_A is the configurable sliding window row size; the read / write control logic drives data to be written cyclically to the pipelined row cache array, and when the sliding window crosses the matrix boundary, it reads data from the additional RAM to pad with zeros or performs loopback splicing according to the configured boundary mode.

[0012] Furthermore, the sliding window noise solving submodule includes a parallel binary tree summation unit, a shift register array, and a boundary processing unit; The parallel binary tree summation unit is used to quickly sum the multiple rows of data read in parallel from the row data cache submodule by column. The shift register array is used to perform pipelined shifting of column summation results to simultaneously provide the multi-column summation data required around the current detection unit; The boundary processing unit is used to save, replace, or compensate the column summation data of the training unit according to the configured boundary mode when the current detection unit is located at the matrix boundary, so as to maintain the consistency of noise statistics.

[0013] Furthermore, the highly configurable radar 2D CFAR detection circuit system also includes a set of configurable registers for storing and receiving configuration parameters from the target detection processor via a bus interface; The configurable registers include at least: a frame size configuration register for configuring the distance dimension and Doppler dimension, a channel configuration register for configuring the number of transmit and receive channels and enabling merging, a channel weight configuration register for configuring the fusion coefficients of each channel, a boundary mode configuration register for selecting the boundary zero-padding or boundary loop processing strategy, and a sliding window size configuration register for configuring the window size of the training unit and the protection unit.

[0014] Furthermore, the two-dimensional CFAR target detection hardware accelerator is connected to the target detection processor via an AXI bus interface; the AXI bus interface includes an AXI-Lite interface and an AXI-Stream interface; The AXI-Lite interface is used to transmit register configuration information, and the AXI-Stream interface is used to stream the range-Doppler matrix data and the target detection results.

[0015] Furthermore, the target detection processor is also configured to: The range-Doppler matrix data is sent to the two-dimensional CFAR target detection hardware accelerator via direct memory access, and the target detection result is received. The target detection results are sent to the host computer for visualization via a serial communication interface.

[0016] The beneficial effects of this invention are as follows: By combining a target detection processor with a dedicated hardware accelerator containing a frame data dimensionality reduction module and a sliding window target detection module, a collaborative processing circuit system is constructed. This architecture enables the system to flexibly adapt to different radar operating parameters and application scenarios through the processor's configuration interface, and to perform efficient and parallel dimensionality reduction and detection operations on the range-Doppler matrix through a dedicated hardware pipeline. This fundamentally solves the contradiction between flexibility and processing efficiency in traditional solutions, achieving low power consumption, high real-time performance, and deterministic target detection capabilities with high configurability, providing a stable hardware foundation for subsequent processing. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a diagram illustrating the overall architecture of the CFAR target detection accelerator according to an embodiment of the present invention. Figure 2 This is a structural diagram of the preprocessing submodule according to an embodiment of the present invention; Figure 3 This is a structural diagram of the transmission channel merging submodule according to an embodiment of the present invention; Figure 4 This is a structural diagram of the power compression submodule according to an embodiment of the present invention; Figure 5 This is a structural diagram of the receiving channel merging submodule according to an embodiment of the present invention; Figure 6 This is a structural diagram of the row data caching submodule according to an embodiment of the present invention; Figure 7 This is a structural diagram of the sliding window noise solving submodule according to an embodiment of the present invention; Figure 8 This is an example diagram of boundary loop calculation according to an embodiment of the present invention; Figure 9 This is an example diagram of boundary zero-padding calculation in an embodiment of the present invention; Figure 10 This is a schematic diagram of the summation binary tree calculation method according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the FPGA-based radar two-dimensional CFAR detection SoC architecture according to an embodiment of the present invention; Figure 12 This is a flowchart illustrating the target detection system of an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that the descriptions involving "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0021] Please see Figure 1 The first embodiment of the present invention is: a highly configurable radar two-dimensional CFAR detection circuit system, including: a target detection processor and a two-dimensional CFAR target detection hardware accelerator.

[0022] The target detection processor is used to send range-Doppler matrix data, configure the parameters of the two-dimensional CFAR target detection hardware accelerator through a configuration interface, and receive the detection results of the two-dimensional CFAR target detection hardware accelerator.

[0023] The two-dimensional CFAR target detection hardware accelerator includes a frame data dimensionality reduction module and a sliding window target detection module, which are used to receive the range-Doppler matrix data, perform frame data dimensionality reduction processing and sliding window target detection according to the configuration parameters, and output the target detection results.

[0024] The highly configurable radar 2D CFAR detection circuit system includes a set of configurable registers for storing and receiving configuration parameters from the target detection processor via a bus interface. The configurable registers include at least: a frame size configuration register for configuring the distance dimension and Doppler dimension, a channel configuration register for configuring the number of transmit and receive channels and enabling merging, a channel weight configuration register for configuring the fusion coefficients of each channel, a boundary mode configuration register for selecting the boundary zero-padding or boundary loop processing strategy, and a sliding window size configuration register for configuring the window size of the training unit and the protection unit.

[0025] In a specific embodiment, the two-dimensional CFAR target detection hardware accelerator is connected to the target detection processor via an AXI bus interface; the AXI bus interface includes an AXI-Lite interface and an AXI-Stream interface; The AXI-Lite interface is used to transmit register configuration information, and the AXI-Stream interface is used to stream the range-Doppler matrix data and the target detection results.

[0026] In a specific embodiment, the target detection processor is further configured to: The range-Doppler matrix data is sent to the two-dimensional CFAR target detection hardware accelerator via direct memory access, and the target detection result is received. The target detection results are sent to the host computer for visualization via a serial communication interface.

[0027] Compared to traditional single-parameter configurations, the register configuration of this invention covers multiple scenarios, enhancing the module's flexibility. In different radar target detection scenarios, the register values ​​can be configured to achieve efficient operation adapted to the specific scenario. Furthermore, the corresponding chip performance also boasts advantages such as low power consumption and small size.

[0028] The configurable parameters and register definitions of the configurable registers are shown in Table 1 below. These registers enable the system to flexibly adapt to different radar parameters and application scenarios. Table 1 Configurable Register Parameters In a specific embodiment, the frame data dimensionality reduction module is used to preprocess, channel merge, and power compress the input range-Doppler matrix complex data to generate an energy matrix for CFAR detection. The sliding window target detection module is used to perform sliding window noise estimation and threshold decision on the energy matrix, and output the target detection results and related auxiliary information.

[0029] In a specific embodiment, the frame data dimensionality reduction module includes a preprocessing submodule, a transmit channel merging submodule, a power compression submodule, and a receive channel merging submodule connected in sequence.

[0030] The preprocessing submodule is used to convert floating-point data into fixed-point data and extract the real and imaginary parts of complex data.

[0031] In this embodiment, please refer to Figure 2 The input floating-point data format consists of signed real part data, imaginary part data, and exponent data, with bit width representing bits: The formula for {Real_part[31:19],Imag_part[18:4],Exp_part[3:0]}, in floating-point data format, is as follows: Where V represents the converted floating-point data, S represents the sign bit of the exponent, M represents the data value, and E represents the exponent. In the actual conversion process, the sign bit of the exponent is extracted first. If it is positive, the data is shifted left by the exponent bits; if it is negative, the data is shifted right by the exponent bits. It's important to note that the real and imaginary parts are processed in parallel during the conversion, and the fixed-point real and imaginary parts are output in parallel. This process converts floating-point arithmetic to fixed-point arithmetic, reducing the complexity of subsequent hardware operations.

[0032] The transmission channel merging submodule is used to perform weighted fusion of data from different transmission channel dimensions according to configurable weights.

[0033] In this embodiment, please refer to Figure 3 The transmit channel merging submodule performs a weighted summation of the real and imaginary parts of the data from each transmit channel. Using externally configured channel number and weight data, a counter generates channel indices, and a multiplexer sequentially selects the input data for each channel. Simultaneously, the corresponding weight coefficients are read. The selected data and weight coefficients are multiplied in a multiplier, and the product result is written to a register buffer for alignment. Channel accumulation is then performed, and when the number of accumulations reaches the specified channel number, the merged result is output. Finally, the weighted summation of the real and imaginary parts is output in parallel.

[0034] The power compression submodule is used to calculate the energy value of the fused complex data and perform approximate logarithmic operations to achieve dynamic range compression.

[0035] In this embodiment, please refer to Figure 4 The structure of the power compression submodule is as follows: Figure 4 As shown, this includes power spectrum calculation and logarithmic operation processing: 1. The power spectrum calculation and processing mainly involves solving for the energy of the real and imaginary parts of the weighted summation data. The energy data is output by squaring the real and imaginary parts of the input data and then summing them.

[0036] 2. In the logarithmic operation processing section, the energy data is sliced ​​using parallel bit widths to find the indices of each non-zero group. Then, a priority encoder is used to obtain the group with the highest bit set to 1. Simultaneously, the group with the highest bit set to 1 is again subjected to a priority encoder to obtain the index of the highest bit set to 1 as the integer part. Then, the corresponding bit width index is selected, and the following 5 decimal places are taken (separate operations are performed for the highest bit set to 1). When the higher 3 bits are all 1, they are directly used as the decimal result. When they are not all 1, a bitwise OR operation is performed on the lower 2 bits to obtain the least significant decimal bit. Specific details regarding decimal places are as follows: Here, `frac_bit` represents the data in the fractional slice. The integer part is then shifted left by 3 bits, and a bitwise OR operation is performed between the integer and fractional parts to output the corresponding logarithmic energy data. Specifically, this has the following advantages: 1. By performing logarithmic operations, the bit width representation of energy values ​​can be reduced, which can significantly reduce the amount of computation and buffer usage required in subsequent calculations. This will greatly improve the computational efficiency of the subsequent receiver channel merging submodule and sliding window target detection module, especially under larger range-Doppler matrix sizes.

[0037] 2. By adding decimal places, the error is reduced. For the log2 operation, the highest integer 1 is found. However, if only the integer part is found, the error after the operation is large. If every subsequent digit is operated to obtain the decimal part, it will lead to an increase in computing resources and latency. Therefore, this invention designs a simplified log2 approximation operation with a maximum operation error of 0.125, which can greatly reduce the error compared to simple rounding.

[0038] 3. Reducing computational and storage requirements will effectively lower system energy consumption, achieving a better balance between hardware performance and power consumption.

[0039] The receiving channel merging submodule is used to perform weighted fusion of logarithmic energy data from different receiving channel dimensions according to configurable weights, and output the energy matrix.

[0040] In this embodiment, please refer to Figure 5 The receiving channel merging submodule performs a weighted summation of the logarithmic energy data from each receiving channel. Using externally configured channel number and weight data, a counter generates channel indices, and a multiplexer sequentially selects the input data for each channel. Simultaneously, the corresponding weight coefficients are read. The selected data and weight coefficients are multiplied in a multiplier, and the product result is written to a register buffer for alignment. Channel accumulation is then performed. When the number of accumulations reaches the specified channel number, the merged result is output, and range-Doppler frame data is streamed.

[0041] In a specific embodiment, the power compression submodule includes a logarithmic operation unit, which is configured to: find the highest non-zero bit of the input energy value as the integer part, and truncate a specific number of bits after the highest bit for logical processing to generate a fractional part with at least 3 significant decimal places, and combine the integer part and the fractional part for output, so as to control the operation error while reducing the data bit width.

[0042] In a specific embodiment, the sliding window target detection module includes a row data caching submodule, a sliding window noise solving submodule, and a data integration submodule.

[0043] The row data caching submodule employs a streaming cache array composed of multiple RAMs to cache and update the input energy matrix row by row, thereby supporting fast data access within the two-dimensional neighborhood of the sliding window.

[0044] In this embodiment, please refer to Figure 6 The row data cache submodule provides the necessary row data for sliding window data operations in the pipelined cache frame data. It includes a pipelined row cache array consisting of (ref_A+1) RAMs, an additional RAM cache for the boundary (ref_A-1) rows, and chip select decoding and read / write control logic consisting of counters and shift registers. Here, ref_A is the sliding window row dimension of the configured distance-Doppler matrix, and RAM is on-chip random access memory. During continuous data input, the read / write control logic drives the input to be written row by row into the (ref_A+1) RAMs and cyclically overwritten with each clock cycle. Simultaneously, at each moment, A rows of data are selected from the pipelined row buffer array for output. At the frame start stage, the first ref_A-1 rows of data are written to the additional buffer for subsequent boundary padding. Boundary modes are divided into loopback mode and zero-padding mode. In loopback mode, when the sliding window crosses the frame boundary area, the chip select decoding unit generates a control signal and reads the corresponding row of data from the additional buffer, concatenating it with the current pipelined row of data for output. In zero-padding mode, zero-filling is performed directly for output, thus stably outputting multi-channel sliding window operation data under different frame sizes and boundary modes. Specifically, it has the following characteristics: 1. Streaming RAM replaces register caching. Register caching, simply put, involves predefining a register that can cache an entire frame of data. Then, after caching the data necessary for computation, computation begins. This method can read the data required for computation in one cycle, which is faster, but the power consumption is huge because not all the data is needed for each computation.

[0045] 2. Streaming RAM as a replacement for single-frame RAM caching: Similarly, if a frame of data is cached at once, power consumption can be reduced. However, since RAM can only read and write one piece of data at a time, this will lead to low computational efficiency and cannot meet the real-time requirements for large input sizes.

[0046] 3. The streaming cache RAM approach can reduce area and power consumption, and also improve throughput, thereby increasing the computational efficiency of the subsequent noise sliding window noise solution submodule.

[0047] The sliding window noise solving submodule is used to perform noise statistics on the training unit and generate a decision threshold based on the configurable sliding window size and boundary pattern.

[0048] In this embodiment, please refer to Figure 7 The sliding window noise solution submodule performs energy summation on the sliding window data. The summation method can be divided into two types based on the register configuration: boundary loopback and boundary zero-padding. An example diagram of boundary loopback calculation is shown below. Figure 8 As shown, for the range-Doppler matrix ,in, For row index, Here, `rows` and `cols` represent the column indices, respectively, and `ref_A` and `ref_B` represent the row and column dimensions of the distance-Doppler matrix. It's important to note that `rows`, `cols`, `ref_A`, `ref_B`, and the boundary mode can all be adjusted via external register configuration. The specific summation method for the corresponding boundary loopback mode is as follows: And take the average value according to the configured sliding window size. in, As for the boundary zero-padding method, the calculation example diagram is as follows: Figure 9 As shown, the summation method is as follows: And take the average. in, When the module runs, it is cached to the first... The calculation begins at the beginning of the row, with the first CUT cell index value calculated starting from... Initially, because considering boundary loopback, the calculation data for the first line of the frame requires data from the last line of the frame to complete the corresponding calculation. In actual calculation, based on the current... The row index is used to select the corresponding row data cache module, and then the ref_A-1 data path is read in parallel. The data is then processed through a parallel binary tree summation unit (6 input units). The corresponding binary tree summation calculation method is as follows: Figure 10 As shown, the calculation method is as follows: 1. In Stage 1, three addition units are introduced to sum the two input data in parallel. 2. In Stage 2, summation is performed by introducing one addition unit, and the single-node data output in Stage 1 is cached; 3. In Stage 3, summation is performed by introducing one addition unit, and the result is output.

[0049] It should be noted that each stage runs synchronously, thus ensuring the efficient operation of the overall computation.

[0050] The data integration submodule is used to compare and decide the threshold with the energy of the unit to be detected, and to output the decision result, row and column coordinates, noise estimate, energy value and frame target number in a structured manner.

[0051] In this embodiment, the data integration module is used to sum the average noise value of the reference cells surrounding the CUT output by the sliding window noise solving module. Multiply by the threshold factor and then combine the result with the energy value of the current cell CUT. When making comparisons and decisions, it's important to note that the corresponding threshold factors are pre-generated in software and selected using a lookup table in the hardware accelerator. Finally, the decision results and related information are structured and encapsulated for output. Specifically, the data integration module receives the average noise summation value and the corresponding threshold parameter, generates the detection threshold of the current CUT, and compares the detection threshold with the CUT energy to obtain the target decision result (target / non-target) and an optional confidence index. Simultaneously, the data integration module obtains the row and column coordinate information corresponding to the current CUT, and performs alignment and formatting processing on the noise statistics, CUT energy value, and row and column coordinates. Further, the data integration module counts each CUT that is determined to be a target to obtain the frame target number, or accumulates and updates the target count. Finally, the data integration module concatenates the 1-bit target flag, 8 bits of all zeros, 11-bit target row index, 1 bit of zero, 11-bit target column index, 32-bit frame target statistics, 32-bit noise energy value, 9 bits of zero, and 23-bit CUT energy value in the order of the fields to form structured output data in a fixed format, representing the decision result, row and column coordinates, noise statistics, CUT energy value, and frame target number, respectively.

[0052] In a specific embodiment, the row data caching submodule includes a pipelined row cache array consisting of ref_A+1 RAMs, additional RAM for caching the boundary data of the preceding ref_A-1 rows, and read / write control logic; Wherein, ref_A is the configurable sliding window row size; the read / write control logic drives data to be written cyclically to the pipelined row cache array, and when the sliding window crosses the matrix boundary, it reads data from the additional RAM to pad with zeros or performs loopback splicing according to the configured boundary mode.

[0053] In a specific embodiment, the sliding window noise solving submodule includes a parallel binary tree summation unit, a shift register array, and a boundary processing unit; The parallel binary tree summation unit is used to quickly sum the multiple rows of data read in parallel from the row data cache submodule by column. The shift register array is used to perform pipelined shifting of column summation results to simultaneously provide the multi-column summation data required around the current detection unit; The boundary processing unit is used to save, replace, or compensate the column summation data of the training unit according to the configured boundary mode when the current detection unit is located at the matrix boundary, so as to maintain the consistency of noise statistics.

[0054] To verify the performance of the system of this invention, a comprehensive evaluation was conducted under the 28nm process, with a running clock of 600MHz and a supply voltage of 0.81V. The performance, power consumption, and area of ​​the proposed CFAR target detection accelerator were analyzed, as shown in Table 2 (where latency is set to the default value for the relevant register configuration). It can be seen that the CFAR target detection accelerator of this invention has the characteristics of low latency, low power consumption, and lightweight.

[0055] Table 2 PPA data of the CFAR target detection accelerator Furthermore, such as Figure 11 As shown, the CFAR target detection SoC proposed in this invention is implemented in hardware based on the Xilinx Zynq7000 series FPGA chip (specifically model xc7z020clg484-2). The main clock frequency is 100MHz, and the amount of resources consumed is shown in Table 3. Since the CFAR target detection accelerator proposed in this invention is a lightweight, low-power module, the overall SoC consumes fewer resources after being implemented on an FPGA, and it is also easy to integrate with downstream application modules such as clustering, tracking, autonomous driving obstacle avoidance, and gesture recognition.

[0056] Table 3 Resource consumption of FPGA-based target detection SoC Finally, the detection results of this invention were verified on an actual test set. The recall distribution in the actual test is shown in Table 4, with an overall recall rate of 92.6%. Among them, the (56,0) frame 5 / 6 was found to have too little actual energy during software verification, and was submerged in noise, making it undetectable.

[0057] Table 4. Recall rate under actual testing of the object detection accelerator In one specific implementation of this embodiment, the workflow of the entire system can be combined Figure 12 The specific steps are as follows: In one specific implementation of this embodiment, the workflow of the entire system can be combined Figure 12 The specific steps are as follows: 1. The FPGA system and peripherals are powered on and start up, completing hardware initialization, including the basic clock, reset and bus interconnect initialization of the A9 processor side (PS) and CFAR target detection accelerator side (PL), so that the system enters a configurable working state.

[0058] 2. Configure peripherals and interrupts for the A9 processor; including setting the enable, priority and triggering mode of peripheral interrupts, and configuring the working mode of peripherals such as UART, DMA, and GPIO for subsequent data transmission, status interaction and debugging output.

[0059] 3. The A9 processor configures the parameters of the CFAR target detection accelerator; it sends the parameter configuration information required for sliding window detection (such as the distance-Doppler matrix dimension, the number of transmit and receive channels, channel weights, boundary modes, etc.) through the register / control interface, and enables the accelerator to enter the waiting state.

[0060] 4. The A9 processor completes DMA transmit / receive packet initialization, including DMA read / write channel configuration, buffer address / length setting, descriptor preparation for one or more transfers, and bit width and burst policy configuration aligned with the accelerator data interface.

[0061] 5. The A9 processor initiates a DMA packet to send the frame data to be detected to the CFAR target detection accelerator; the frame data is a multi-channel range-Doppler matrix and is continuously written to the accelerator input port in floating-point data format.

[0062] 6. The CFAR target detection accelerator performs frame data dimensionality reduction processing on the received frame data; the processing flow includes: preprocessing, transmit channel merging, power compression, and receive channel merging.

[0063] 7. After the accelerator completes the frame data dimensionality reduction processing, it enters the sliding window target detection processing stage; this stage includes: row data buffering, sliding window noise solving and data integration.

[0064] 8. The accelerator outputs the detection results to the DMA return channel; the output data may include the target decision result, the row and column coordinates of the target, the corresponding energy / noise statistics, and frame-level statistics (such as the number of targets in the frame), and is packaged and output according to the predetermined data format.

[0065] 9. The A9 processor performs DMA packet reception and determines "Packet reception complete?". If not, it continues to execute the loop processing of steps 5 to 9 to complete the packet transmission of the same frame or the pipeline processing of multiple consecutive frames. If it is completed, it enters the subsequent visualization or reporting process.

[0066] 10. The A9 processor sends the final detection results to an external device via serial port for visualization on a host computer.

[0067] In summary, this invention designs a highly configurable 2D CFAR target detection accelerator for radar and implements the accelerator as a SoC via FPGA, primarily applicable to radar edge intelligent target detection applications. The system output includes structured information such as decision results, row and column coordinates, noise / energy estimates, and the number of targets per frame, facilitating integration with downstream clustering, target tracking, and trajectory fusion algorithms. This provides high-efficiency and portable target detection capabilities for various radar edge intelligent applications, including autonomous driving obstacle avoidance, pedestrian / vehicle detection, and gesture and posture recognition.

[0068] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A highly configurable radar two-dimensional CFAR detection circuitry, characterized by, include: Object detection processor and 2D CFAR object detection hardware accelerator; The target detection processor is used to send range-Doppler matrix data, configure the parameters of the two-dimensional CFAR target detection hardware accelerator through a configuration interface, and receive the detection results of the two-dimensional CFAR target detection hardware accelerator. The two-dimensional CFAR target detection hardware accelerator includes a frame data dimensionality reduction module and a sliding window target detection module, which are used to receive the range-Doppler matrix data, perform frame data dimensionality reduction processing and sliding window target detection according to the parameter configuration, and output the target detection results. The frame data dimensionality reduction module is used to preprocess, merge, and compress the input range-Doppler matrix complex data to generate an energy matrix for CFAR detection. The sliding window target detection module is used to perform sliding window noise estimation and threshold decision on the energy matrix, and output the target detection results and related auxiliary information; The sliding window target detection module includes a row data caching submodule, which uses a streaming cache array composed of multiple RAMs to cache and update the input energy matrix row by row, so as to support fast data access of the sliding window in the two-dimensional neighborhood. The row data caching submodule includes a pipelined row cache array consisting of ref_A+1 RAMs, additional RAM for caching the boundary data of the preceding ref_A-1 rows, and read / write control logic; Wherein, ref_A is the configurable sliding window row size; the read / write control logic drives data to be written cyclically to the pipelined row cache array, and when the sliding window crosses the matrix boundary, it reads data from the additional RAM to pad with zeros or performs loopback splicing according to the configured boundary mode.

2. The highly configurable radar two-dimensional CFAR detection circuitry of claim 1, wherein, The frame data dimensionality reduction module includes a preprocessing submodule, a transmit channel merging submodule, a power compression submodule, and a receive channel merging submodule connected in sequence. The preprocessing submodule is used to convert floating-point data into fixed-point data and extract the real and imaginary parts of complex data; The transmission channel merging submodule is used to perform weighted fusion of data from different transmission channel dimensions according to configurable weights; The power compression submodule is used to calculate the energy value of the fused complex data and perform approximate logarithmic operations to achieve dynamic range compression. The receiving channel merging submodule is used to perform weighted fusion of logarithmic energy data from different receiving channel dimensions according to configurable weights, and output the energy matrix.

3. The highly configurable radar two-dimensional CFAR detection circuitry of claim 2, wherein, The power compression submodule includes a logarithmic operation unit, which is configured to: find the highest non-zero bit of the input energy value as the integer part, extract a specific number of bits after the highest non-zero bit for logical processing to generate a fractional part with at least 3 significant decimal places, and combine the integer part and the fractional part for output, so as to control the operation error while reducing the data bit width.

4. The highly configurable radar two-dimensional CFAR detection circuitry of claim 1, wherein, The sliding window target detection module also includes a sliding window noise solving submodule and a data integration submodule; The sliding window noise solving submodule is used to perform noise statistics on the training unit and generate a decision threshold based on the configurable sliding window size and boundary pattern. The data integration submodule is used to compare and decide the threshold with the energy of the unit to be detected, and to output the decision result, row and column coordinates, noise estimate, energy value and frame target number in a structured manner.

5. The highly configurable radar two-dimensional CFAR detection circuitry of claim 4, wherein, The sliding window noise solving submodule includes a parallel binary tree summation unit, a shift register array, and a boundary processing unit. The parallel binary tree summation unit is used to quickly sum the multiple rows of data read in parallel from the row data cache submodule by column. The shift register array is used to perform pipelined shifting of column summation results to simultaneously provide the multi-column summation data required around the current detection unit; The boundary processing unit is used to save, replace, or compensate the column summation data of the training unit according to the configured boundary mode when the current detection unit is located at the matrix boundary, so as to maintain the consistency of noise statistics.

6. The highly configurable radar two-dimensional CFAR detection circuitry of any one of claims 1 to 5, wherein, It also includes a set of configurable registers for storing and receiving configuration parameters from the target detection processor via a bus interface; The configurable registers include at least: a frame size configuration register for configuring the distance dimension and Doppler dimension, a channel configuration register for configuring the number of transmit and receive channels and enabling merging, a channel weight configuration register for configuring the fusion coefficients of each channel, a boundary mode configuration register for selecting the boundary zero-padding or boundary loop processing strategy, and a sliding window size configuration register for configuring the window size of the training unit and the protection unit.

7. The highly configurable radar two-dimensional CFAR detection circuitry of claim 6, wherein, The two-dimensional CFAR target detection hardware accelerator is connected to the target detection processor via an AXI bus interface; the AXI bus interface includes an AXI-Lite interface and an AXI-Stream interface. The AXI-Lite interface is used to transmit register configuration information, and the AXI-Stream interface is used to stream the range-Doppler matrix data and the target detection results.

8. The highly configurable radar two-dimensional CFAR detection circuitry of claim 7, wherein, The target detection processor is further configured to: The range-Doppler matrix data is sent to the two-dimensional CFAR target detection hardware accelerator via direct memory access, and the target detection result is received. The target detection results are sent to the host computer for visualization via a serial communication interface.

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