A multi-channel audio synchronous transmission wide bus system and method
A multi-channel audio synchronous transmission system driven by a global system counter and a wide bus DMA engine utilizes a global clock signal to synchronize parallel data transmission, solving the phase skew and delay problems of traditional systems and improving bandwidth utilization and data transmission efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JUDI (SHANGHAI) TECHNOLOGY CO LTD
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-16
Smart Images
Figure CN121680771B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and relates to data transmission technology in integrated circuits, specifically to a multi-channel audio synchronous transmission wide bus system and method. Background Technology
[0002] With the development of immersive audio, beamforming microphone arrays, and active noise cancellation technologies, the number of audio channels that modern SoCs need to handle simultaneously has increased dramatically, typically 16, 32, or more channels. Traditional design methods usually employ a multi-instance replication strategy, which instantiates multiple independent integrated circuit-based audio bus I2S (Inter-IC Sound) controller IP (Intellectual Property) modules within the chip. Each IP module has its own independent FIFO (First-In-First-Out queue), independent clock divider, and independent DMA (Direct Memory Access) request interface. Software must manage these modules separately through interrupt service routines (ISRs).
[0003] However, the above architecture has the following fundamental flaws:
[0004] 1. Phase skew: Since each I2S module starts independently and is limited by the arbitration delay of the system bus (BUSBAR), the startup time of different modules cannot be guaranteed to be within the same clock cycle, resulting in random phase errors between channels.
[0005] 2. Uncertainty-based latency: Traditional DMA relies on requests, acknowledgments, and handshaking signals from peripheral devices. Under high load, uncertainty in bus arbitration can lead to FIFO underruns or data jitter.
[0006] 3. Waste of resources: Multiple independent small-bit-width DMA transfers, such as 32-bit, cannot effectively utilize the wide bus bandwidth of modern SoCs, such as 128-bit or 256-bit bandwidth, which increases power consumption and arbitration overhead. Summary of the Invention
[0007] This invention aims to solve the above-mentioned problems. This invention abandons the traditional independent controller and handshake protocol, and treats multi-channel audio transmission as a single deterministic time event. Based on the above, this invention discloses an audio data synchronous transmission method and transmission device to improve the efficiency of audio data transmission and reduce load requirements.
[0008] The multi-channel audio synchronous transmission wide bus system of the present invention includes a global system counter, a wide bus DMA engine, an intermediate buffer storage unit, and a unified audio transmission unit. The wide bus DMA engine is connected to the system memory and the intermediate buffer storage unit, and the intermediate buffer storage unit is connected to the unified audio transmission unit.
[0009] The global system counter is driven by the system master clock MCLK. It generates word group selection signals, transmits start signals and local clocks through the system master clock MCLK, and is used to drive other modules.
[0010] The wide bus DMA engine is configured to execute in the following mode: data transmission is initiated only when the global system counter value reaches a preset prefetch point.
[0011] The unified audio transmission unit includes a shadow buffer connected to the intermediate buffer storage unit, and a giant shift register with atomic parallel loading function connected to the shadow buffer. The giant shift register is divided into multiple equal segments with consecutive addresses, and the most significant bit of each segment is connected to a data output pin.
[0012] Preferably, the multi-channel audio synchronous transmission wide bus system further includes a deadline monitor, which is connected to the intermediate buffer storage unit.
[0013] This invention discloses a multi-channel audio synchronous transmission method, based on the multi-channel audio synchronous transmission wide bus system, comprising the following steps:
[0014] Step 1. The global system counter is driven by the system master clock MCLK. It generates a unified count value across the entire domain, transmits the start signal ST, the word group selection signal WS, and the local clock BCLK through the system master clock MCLK.
[0015] Step 2. The wide bus DMA engine monitors the output count value of the global system counter. When the count value enters the preset time trigger interval, it executes the burst read mode and writes the multi-channel data block to the intermediate buffer storage unit.
[0016] Step 3. The data from the intermediate buffer storage unit is temporarily stored in the shadow temporary storage area of the unified audio transmission unit;
[0017] Step 4. At the edge of the end of a single cycle of the word group selection signal WS, all channel data in the shadow buffer is simultaneously loaded into the giant shift register within one clock cycle through the atomic parallel load path.
[0018] Step 5. Driven by the local clock, each segment of the giant shift register synchronously performs a left shift operation and simultaneously sends data out through its respective connected data transmission pin.
[0019] Preferably, the word group selection signal is a periodic pulse signal, with different levels representing whether the audio channel being transmitted is the left or right channel.
[0020] Preferably, the transmission start signal includes at least one or more complete word group selection signal cycles during the data transmission period.
[0021] Preferably, in step 1, multi-channel audio is pre-stored in the system memory in an alternating manner with left and right channels, and the wide bus DMA engine reads the data through a single wide bus transaction.
[0022] Preferably, in step 5, the data in the shadow buffer is atomically and in parallel loaded into the giant shift buffer of the unified audio transmission unit.
[0023] Compared with the prior art, the present invention has the following advantages:
[0024] 1. By utilizing a global clock signal locked to the sampling rate for data transmission and signal generation triggering, the system no longer relies on buffer status flags, reducing the possibility of FIFO underrun or data jitter. Zero relative skew is achieved, maximizing bandwidth utilization and significantly reducing CPU interrupt load.
[0025] 2. By using a giant shift register, the audio data of multiple channels can be treated as a single wide data, and a unified parallel input / output logic can be used to drive all I2S data transmission channels simultaneously under a single clock domain, thus eliminating the logic skew between channels at the physical level.
[0026] 3. Based on the prediction of the global system counter, wide data is actively pushed into the shadow buffer area before the deadline, eliminating the need for request signals from peripheral devices and thus eliminating handshake delay. Attached Figure Description
[0027] Figure 1 is a schematic diagram of a specific embodiment of the multi-channel audio synchronous transmission system of the present invention;
[0028] Figure 2 is a schematic diagram of a specific embodiment of the giant shift register of the present invention;
[0029] Figure 3 is a waveform diagram comparing the present invention and the prior art;
[0030] The attached figures are labeled as follows: 101. Global System Counter, 102. Wide Bus DMA Engine, 103. Intermediate Buffer Storage Unit, 104. Unified Audio Transmission Unit, 105. System Memory, 106. Deadline Monitor, 201. Giant Shift Register, 202. Shadow Shift Register. Detailed Implementation
[0031] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0032] This invention relates to the field of integrated circuit (IC) design and processing technology, and in particular to a precise phase synchronization architecture and data transmission architecture for multi-channel integrated circuits with built-in audio bus I2S (Inter-ICSound) or time division multiplexing (TDM) interface in system-on-chip (SoC) or application-specific integrated circuit (ASIC). This invention discloses a multi-channel audio synchronous transmission wide bus system and method.
[0033] Referring to Figure 1, a multi-channel audio synchronous transmission system according to the present invention is shown, which includes a global system counter 101, a wide bus DMA engine 102, an intermediate buffer storage unit 103, and a unified audio transmission unit 104. The wide bus DMA engine is also connected to a system memory 105.
[0034] The global system counter 101 is driven by an externally generated system master clock MCLK, which generates the word selection signal WS and the local clock BCLK. Since all signals originate from the same global system counter, the phase relationship between the word selection signal WS and the local clock BCLK is constant.
[0035] The word selection signal WS is a periodic pulse signal used to indicate whether the transmitted audio channel is the left or right channel. For example, a high level indicates the left channel and a low level indicates the right channel. The word selection signal WS is usually formed by dividing the system master clock MCLK, and the local clock BCLK is used as the clock for the transmission device.
[0036] At the same time, the global system counter 101 also generates a periodic transmission start signal ST, which is used to control the wide bus DMA engine 102 to start the data transmission process.
[0037] The system memory stores multi-channel audio data arranged in an alternating pattern, such as (L1, R1), (L2, R2), (L3, R3), (L4, R4)... arranged consecutively. L1 and R1 represent the left and right channel data of the first audio data, and so on.
[0038] The staggered arrangement allows the transmission of the left channel data L1 and right channel data R1 of the first audio data to be transmitted first, followed by the transmission of the left channel data (L2, R2), (L3, R3), and (L4, R4) of the second, third, and fourth audio data. This staggered arrangement enables the wide bus DMA to acquire the entire audio data segment through a single burst transaction.
[0039] In this embodiment, the wide bus DMA engine 102 is configured in 256-bit transmission mode. The wide bus DMA engine does not wait for the I2S bus request, but actively reads data blocks from the system memory in 256-bit size according to the transmission start signal ST issued by the global system counter, and temporarily stores them in the intermediate buffer storage unit.
[0040] Based on the multi-channel audio synchronous transmission system described in this invention, this invention discloses a multi-channel audio synchronous transmission method, comprising the following steps:
[0041] Step 1. The global system counter 101 is driven by the system master clock MCLK. It generates a unified count value across the entire domain, transmits the start signal ST, the word group selection signal WS, and the local clock BCLK through the system master clock MCLK.
[0042] Step 2. The wide bus DMA engine 102 monitors the count value output by the global system counter. When the count value enters the preset time trigger interval, it executes the burst read mode to continuously read data blocks from the system memory and writes the multi-channel data blocks into the intermediate buffer storage unit.
[0043] Step 3. The data in the intermediate buffer storage unit 103 is temporarily stored in the shadow temporary storage area of the unified audio transmission unit;
[0044] Step 4. Set the shadow buffer 202 data atomically and in parallel to the giant shift buffer 201 of the unified audio transmission unit at the edge of the end of a single cycle of the word group selection signal WS.
[0045] Step 5. After receiving data from the shadow buffer 202 and filling it, each segment of the giant shift buffer 201 performs a left shift operation synchronously under the drive of the local clock, and sends data out simultaneously through their respective connected data transmission pins, thus eliminating the phase skew between channels at the physical level.
[0046] The Global System Counter is driven by the system master clock MCLK. It generates the transmission start signal ST, the word group selection signal WS, and the local clock BCLK, which are phase-locked with the audio data sampling rate, through the system master clock MCLK.
[0047] When the transmission start signal ST sends a rising edge, the wide bus DMA engine 102 starts to continuously read data from the system memory and stores it in the intermediate buffer storage unit. The function of the buffer is to temporarily store the continuously read data within a certain period of time. After the data in the buffer is full, it is sent to the unified audio transmission unit 104 all at once.
[0048] In one specific implementation, the period of the transmission start signal ST is proportional to the size of the intermediate buffer storage unit 103. The larger the intermediate buffer storage unit 103 is, the larger the amount of data it can hold, and the longer the period of a single transmission start signal can be, so as to transmit more data in a single cycle.
[0049] In one specific implementation, the transmission start signal, during the data transmission period, such as the high-level interval formed by a pair of closest rising and falling edges, includes at least one, typically multiple, complete word group selection signal WS cycles, so that one or more data transmissions of the left and right channels can be completed simultaneously within the effective time period.
[0050] The edge of the transmission start signal is also generated by the system master clock MCLK through internal logic circuits such as counters, so that the phase of the transmission start signal ST and the word group selection signal WS is constant.
[0051] The intermediate buffer storage unit 103 is automatically pushed to the shadow buffer area 202 of the unified audio transmission unit 104 according to the preset value of the global system counter 101. The data is first temporarily stored in the shadow buffer area 202 of the unified audio transmission unit 104 and is in a standby state until a specific edge of the word selection signal WS, such as a falling edge, arrives. At this time, the 256 bits of data in the shadow buffer area 202 are atomically and parallelly loaded into the giant shift register 201 of the unified audio transmission unit through the atomic parallel load path.
[0052] In multi-channel audio systems, such as a 32-channel microphone array, phase skew is prone to occur in conventional non-atomic configurations. Suppose the system needs to load data from 32 channels into an output buffer for transmission. If the system loads this data one after another, for example, sequentially loading channels 1 through 32, even if the process is very fast, there will be a tiny difference, such as a few nanoseconds, in the time it takes for channels 1 and 32 to be loaded. This tiny time difference causes the output audio signals to be not perfectly aligned in time, i.e., phase skew occurs. For high-precision beamforming or noise reduction algorithms, this skew is an unacceptable defect.
[0053] This invention utilizes atomic parallel load to eliminate the aforementioned phase offset. When data is transferred from the shadow buffer 202 to the giant shift register 201, the data for all channels must be loaded simultaneously on the same clock edge. The loading action is a unified and indivisible unit; that is, either all channels' data are successfully loaded together, or none are loaded. There will be no intermediate state, such as channel 1 being loaded while channel 32 is not yet loaded.
[0054] The giant shift register 201 is 256 bits, the same size as the set data of the transfer mode, and is divided into multiple equal segments with consecutive addresses. The most significant bits of the multiple segments are connected to multiple I2S data output pins respectively.
[0055] For example, it is divided into four 64-bit segments. The four segments store a complete 256-bit data. After receiving data from the shadow buffer and filling it, each segment, driven by the local clock BCLK, performs a left shift operation synchronously on all four segments of the entire 256-bit giant shifter. The data is then sent out simultaneously through the four data transmission pins SD0, SD1, SD2, and SD3.
[0056] Figure 3 shows a comparison waveform diagram of the present invention and the prior art. The horizontal axis represents time. In the prior art, different channels are controlled by their own independent modules, requiring system arbitration to determine whether data transmission should occur. Therefore, the startup times of different modules cannot be guaranteed to be on the same clock cycle.
[0057] Within a period, random phase errors occur between channels. For example, in the prior art waveform in the upper half of Figure 3, there is an inter-channel delay between channel 1 and channel 2, and also a phase delay with the local clock BCLK. This invention employs synchronous transmission, where the local clock, the word selection signal used for arbitration, and the transmission start signal are all signals with identical phase. There is no phase error between the channel transmission and the local clock. Furthermore, the parallel transmission method eliminates inter-channel delays between different channels 1 and channel 2.
[0058] In the specific implementation shown in Figure 1, the system may also include a deadline monitor 106 to identify whether the wide bus DMA engine is blocked. If the word selection signal WS output by the global system counter 101 has reached the start edge, and the data inside the intermediate buffer storage unit 103 has not been updated and the shadow buffer area has not been written, the intermediate buffer storage unit 103 will output an empty signal EMPTY to the deadline monitor 106. This indicates that the wide bus DMA engine 102 is blocked due to a large amount of data and has not transmitted the data to the intermediate buffer storage unit, triggering a timing violation interrupt, thus ensuring that the system can accurately identify congestion problems.
[0059] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a prerequisite for a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the scope of patent protection of the present invention. The scope of patent protection of the present invention shall still be determined by its claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention shall also be included within the scope of protection of the present invention.
Claims
1. A multi-channel audio synchronous transmission wide bus system, characterized in that, It includes a global system counter (101), a wide bus DMA engine (102), an intermediate buffer storage unit (103), and a unified audio transmission unit (104). The wide bus DMA engine (102) is connected to the system memory (105) and the intermediate buffer storage unit (103). The intermediate buffer storage unit (103) is connected to the unified audio transmission unit (104). The global system counter is driven by the system master clock MCLK. It generates a word group selection signal, transmits a start signal, and uses the system master clock MCLK to drive other modules. The wide bus DMA engine is configured to execute in the following mode: data transmission is only initiated when the global system counter value reaches a preset prefetch point; The unified audio transmission unit (104) includes a shadow buffer (202) connected to the intermediate buffer storage unit (103), and a giant shift register (201) with atomic parallel loading function connected to the shadow buffer. The giant shift register (201) is divided into multiple equal segments with consecutive addresses, and the most significant bit of each segment is connected to a data output pin.
2. The multi-channel audio synchronous transmission wide bus system as described in claim 1, characterized in that, The multi-channel audio synchronous transmission wide bus system also includes a deadline monitor (106), which is connected to the intermediate buffer storage unit (103). The deadline monitor (106) is used to identify whether the wide bus DMA engine (102) is blocked.
3. A method for multi-channel audio synchronous transmission, characterized in that, The multi-channel audio synchronous transmission wide bus system as described in claim 1 includes the following steps: Step 1. The global system counter (101) is driven by the system master clock MCLK. It generates a unified count value across the entire domain, transmits the start signal ST, the word group selection signal WS, and the local clock BCLK through the system master clock MCLK. Step 2. The wide bus DMA engine (102) monitors the global system counter (101) and outputs the count value. When the count value enters the preset time trigger interval, it executes the burst read mode and writes the multi-channel data block into the intermediate buffer storage unit. Step 3. The data in the intermediate buffer storage unit (103) is temporarily stored in the shadow temporary storage area (202) of the unified audio transmission unit (104). Step 4. At the edge of the end of a single cycle of the word group selection signal WS, all channel data in the shadow buffer (202) are simultaneously loaded into the giant shift buffer (201) through the atomic parallel load path within one clock cycle. Step 5. Under the drive of the local clock, each segment of the giant shift register (201) performs a left shift operation synchronously and sends data out simultaneously through its respective connected data transmission pin.
4. The multi-channel audio synchronous transmission method as described in claim 3, characterized in that, The word selection signal is a periodic pulse signal, with different levels indicating whether the audio channel being transmitted is the left or right channel.
5. The multi-channel audio synchronous transmission method as described in claim 3, characterized in that, The transmission start signal, during the data transmission period, includes at least one or more complete word group selection signal cycles.
6. The multi-channel audio synchronous transmission method as described in claim 3, characterized in that, In step 1, multi-channel audio is stored in the system memory in advance in an alternating manner with left and right channels, and the wide bus DMA engine (102) reads the data through a single wide bus transaction.
7. The multi-channel audio synchronous transmission method as described in claim 3, characterized in that, In step 5, the data in the shadow storage area (202) is atomically and in parallel loaded into the giant shift register (201) of the unified audio transmission unit (104).