Instruction prefetch method, processor and electronic device

Abstract

Embodiments of the present application disclose an instruction prefetching method, a processor, an electronic device and a computer readable storage medium. The method comprises the following steps: generating a fetch block of a target instruction based on a branch prediction unit and sending the fetch block into a fetch target queue; if the fetch block does not carry first group index information and first path information of the target instruction, sending a prefetch request to an instruction cache unit based on the fetch target queue to cache the target instruction into the instruction cache unit; reading the fetch block from the fetch target queue based on an instruction fetch unit to read the target instruction from the instruction cache unit; if the fetch block carries the first group index information and the first path information, reading the fetch block from the fetch target queue based on the instruction fetch unit to obtain the first group index information and the first path information, and reading the target instruction from the instruction cache unit according to the first group index information and the first path information, so that the redundant prefetch request is reduced and the power consumption of the processor is reduced.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to an instruction prefetching method, a processor, an electronic device, and a computer-readable storage medium. Background Technology

[0002] The instruction fetch module in the processor front end typically employs a decoupled instruction fetch design architecture. The branch prediction unit predicts and generates fixed- or variable-size consecutive instruction blocks (fetch blocks) based on jump instructions, which are then stored in the fetch target queue. Simultaneously, prefetching is used to facilitate reading instructions from the instruction cache. However, using prefetching to read instructions from the instruction cache results in higher processor power consumption. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this application provides an instruction prefetching method, processor, electronic device, and computer-readable storage medium, which can reduce redundant prefetch requests and lower processor power consumption.

[0004] In a first aspect, this application provides an instruction prefetching method applied to the front end of a processor. The front end of the processor includes a branch prediction unit, an instruction fetch target queue, an instruction fetch unit, and an instruction cache unit. The method includes:

[0005] Based on the branch prediction unit, the fetch block of the target instruction is predicted and generated, and the fetch block is sent to the fetch target queue;

[0006] If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit;

[0007] Based on the instruction fetch unit, the instruction fetch block is read from the instruction fetch target queue, and the target instruction is read from the instruction cache unit;

[0008] If the fetch block carries the first set of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first set of index information and the first path information.

[0009] Secondly, this application also provides a processor, the front end of which is provided with a branch prediction unit, an instruction fetch target queue, an instruction fetch unit and an instruction cache unit;

[0010] The branch prediction unit is used to predict the fetch block that generates the target instruction and send the fetch block into the fetch target queue;

[0011] The instruction fetch target queue is used to send a prefetch request to the instruction cache unit if the instruction fetch block does not carry the first set of index information and the first path information of the target instruction, so as to cache the target instruction in the instruction cache unit;

[0012] The instruction fetch unit is used to read instruction blocks from the instruction fetch target queue in order to read the target instruction from the instruction cache unit;

[0013] The instruction fetch unit is also used to read the instruction fetch block from the instruction fetch target queue to obtain the first set of index information and the first path information if the instruction fetch block carries the first set of index information and the first path information, and to read the target instruction from the instruction cache unit according to the first set of index information and the first path information.

[0014] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the instruction prefetching method provided in the first aspect above.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to execute the instruction prefetching method provided in the first aspect.

[0016] Fifthly, embodiments of this application also provide a computer program product, including a computer program or instructions, wherein the computer program or instructions are executed by a processor using the instruction prefetching method provided in the first aspect.

[0017] The instruction prefetching method provided in this application predicts and generates the fetch block of the target instruction based on the branch prediction unit and sends the fetch block to the fetch target queue. If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit. Based on the instruction fetch unit, the fetch block is read from the fetch target queue to read the target instruction from the instruction cache unit. If the fetch block carries the first set of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first set of index information and the first path information. This achieves prefetching only when the fetch block does not carry index and path information, thereby effectively distinguishing between valid and invalid prediction information, avoiding redundant operations, reducing redundant prefetch requests, and reducing processor power consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A first schematic block diagram of the processor provided in this application;

[0020] Figure 2 A first flowchart illustrating the instruction prefetching method provided in this application;

[0021] Figure 3 A second flowchart illustrating the instruction prefetching method provided in this application;

[0022] Figure 4 A second schematic block diagram of the processor provided in this application;

[0023] Figure 5 A schematic block diagram of the electronic device provided in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] Furthermore, in this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0029] For ease of understanding, some key terms in this embodiment are explained below.

[0030] The processor front end is the module in the processor responsible for instruction fetching. It typically contains core components such as the branch prediction unit, the instruction fetch target queue, the instruction fetch unit, and the instruction cache unit, which work together to achieve instruction stream processing.

[0031] A branch prediction unit (BPU) is a piece of hardware logic used to predict the branch path of a program. Its main function is to determine the execution path of a branch instruction in advance, thereby generating the fetch address or fetch block for subsequent instructions to reduce pipeline stalls.

[0032] The Fetch Target Queue (FTQ) is a buffer that receives and temporarily stores fetch blocks generated by the branch prediction unit. It serves as the interface between the branch prediction unit and the instruction fetch unit, ensuring the stability of instruction stream transmission.

[0033] The Instruction Fetch Unit (Fetch) is responsible for retrieving instruction blocks from the instruction fetch target queue and, based on the information contained therein, initiating an instruction read request to the instruction cache unit, thereby sending the instruction to the subsequent decoding and execution stages.

[0034] The Instruction Cache (ICache) is a high-speed cache used to store frequently accessed instructions by the processor. By preloading instructions into the Instruction Cache, instruction access time can be reduced, thus improving processor performance.

[0035] A fetch block is a continuous group of instructions of fixed or variable size. During instruction prefetching, the fetch block can be processed and transmitted as the basic unit.

[0036] A set index can be understood as a collection of cache lines (or blocks) in an instruction cache unit.

[0037] A path can be understood as a cached single column or a single partition that runs through all group indexes.

[0038] In related technologies, the instruction fetch module of the processor front end usually adopts a decoupled instruction fetch design architecture. The branch prediction unit predicts the jump instruction and generates an instruction fetch block in each cycle. At the same time, the generated instruction fetch block is stored in the instruction fetch target queue. The instruction fetch unit retrieves the instruction fetch block from the instruction fetch target queue and initiates a read request to the instruction cache unit. Then, the read instruction is sent to subsequent pipeline stages such as decoding for processing.

[0039] Meanwhile, in the decoupled instruction fetch design, in order to further improve the performance of fetching instructions from the instruction cache unit and reduce the power consumption of fetching, the processor usually performs group index and path prediction. Specifically, the prediction of group index and path is implemented in the branch prediction unit. When the branch prediction unit generates the fetch block, if the group index and path prediction is successful, it will carry the predicted group index and path information in it. After the instruction fetch unit obtains the fetch block, if the fetch block carries a valid group index and path, it will use the group index and path to request instruction data from the instruction cache unit, thereby improving the access speed of the instruction cache unit and reducing power consumption.

[0040] Since the branch prediction unit typically covers a wider range of instructions than the instruction cache unit, data conflicts and replacements within the instruction cache unit can render the group indexes and paths predicted by the branch prediction unit ineffective.

[0041] Therefore, prefetching is usually used for further optimization, such as Figure 1 As shown, after the branch prediction unit generates the fetch block, the fetch block is sent to the fetch target queue. The fetch target queue then sends a prefetch request to the instruction cache unit. When the instruction fetch unit retrieves the fetch block from the fetch target queue, due to the prefetch, the invalid group indexes and paths of the fetch blocks in the previous fetch target queue are corrected in advance. This avoids introducing bubbles into the pipeline due to invalid group indexes and paths.

[0042] However, while prefetching can correct invalid group indexes and paths in advance, it requires a prefetch request for each fetch block, which can lead to duplicate readings of tags in the instruction cache unit, wasting power. Meanwhile, the branch prediction unit has relatively high prediction accuracy. Therefore, how to avoid invalid prefetch requests is a technical problem that urgently needs to be solved.

[0043] To address this, this application provides an instruction prefetching method. Based on a branch prediction unit, the method predicts and generates a fetch block for the target instruction and sends the fetch block to the fetch target queue. If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit. Based on the instruction fetch unit, the method reads the fetch block from the fetch target queue to read the target instruction from the instruction cache unit. If the fetch block carries the first set of index information and the first path information, the method reads the fetch block from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and then reads the target instruction from the instruction cache unit according to the first set of index information and the first path information. This method achieves prefetching only when the fetch block does not carry index and path information, effectively distinguishing between valid and invalid prediction information, avoiding redundant operations, reducing redundant prefetch requests, and lowering processor power consumption.

[0044] The instruction prefetching method provided in this application will be described in detail below.

[0045] like Figure 2 As shown, the method includes the following steps S210~S240.

[0046] S210. Based on the branch prediction unit, predict and generate the fetch block of the target instruction, and send the fetch block into the fetch target queue;

[0047] S220. If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit.

[0048] S230. Based on the instruction fetch unit, read the fetch block from the fetch target queue to read the target instruction from the instruction cache unit;

[0049] S240. If the fetch block carries the first set of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first set of index information and the first path information.

[0050] In this embodiment, the first set of index information is used to indicate the location of a specific group in the instruction cache unit. The instruction cache unit can be organized into multiple groups, each group containing multiple paths. The first set of index information can be used to locate the group where the target instruction may be located.

[0051] The first path information is used to indicate the location of a specific path in the instruction cache unit. After determining the group where the target instruction belongs, this application can further locate the specific cache line or block where the target instruction is located using the first path information.

[0052] The branch prediction unit is responsible for predicting the fetch block of the target instruction. For example, the branch prediction unit can predict the address of the next instruction based on the current value of the program counter (PC) and encapsulate it into a fetch block.

[0053] Alternatively, the branch prediction unit can maintain a simple branch history table, predict the target address of the branch jump based on the historical records, and generate the instruction region corresponding to the target address as an instruction fetch block.

[0054] Then, the instruction fetch block can be sent to the instruction fetch target queue, waiting for processing by the instruction fetch unit.

[0055] Specifically, when an instruction fetch block is sent to the fetch target queue, the fetch target queue can check the instruction fetch block. If it detects that the instruction fetch block does not contain the first set of index information and the first path information of the target instruction, it indicates that it may not be possible to directly access the instruction cache through accurate prediction. In this case, the fetch target queue will proactively send a prefetch request to the instruction cache unit, thereby loading and caching the target instruction from main memory or other storage levels into the instruction cache unit in advance before the instruction fetch unit actually needs the instruction, for subsequent fast access. The instruction fetch unit can periodically read the instruction fetch blocks to be processed from the fetch target queue. After obtaining the instruction fetch block, the instruction fetch unit can initiate a read operation from the instruction cache unit according to the instruction address information contained in the instruction fetch block.

[0056] If the instruction fetch unit reads an instruction block from the instruction fetch target queue that carries the first set of index information and the first path information of the target instruction, the instruction fetch unit will directly extract the first set of index information and the first path information from the instruction fetch block, and use the first set of index information and the first path information to directly initiate a read request to the instruction cache unit to quickly obtain the target instruction, thus avoiding the overhead of tag matching for the entire cache.

[0057] In this application, by conditionally initiating prefetch requests—that is, only performing prefetching when the fetch block does not carry the first set of index information and the first path information—unnecessary prefetching operations on fetch blocks that already carry prediction information are avoided. This reduces repeated readings of instruction cache tags and lowers the power consumption of the processor front end. Simultaneously, even when prediction information is missing, the target instruction is still ensured to be cached in a timely manner, guaranteeing the reliability and efficiency of instruction fetching.

[0058] In some embodiments, predicting and generating a fetch block for a target instruction based on a branch prediction unit includes: predicting the fetch address of the target instruction based on a jump using the branch prediction unit, and generating the fetch block based on the fetch address.

[0059] In this embodiment, the branch prediction unit can predict the direction of branch instructions (such as jumps, calls, and returns) in the program execution flow and determine the fetch address of the next instruction in advance. Specifically, the branch prediction unit can predict the jump direction of the branch by combining the branch history register and the mode history table, and calculate the fetch address based on the predicted direction and the current instruction address. When the branch prediction unit successfully predicts the fetch address of the target instruction, it can package a continuous block of instructions starting from the fetch address into a fetch block. For example, the branch prediction unit can predict whether a conditional branch will jump; if a jump is predicted, it calculates the fetch address based on the offset of the branch instruction.

[0060] In this application, jump prediction is performed through a branch prediction unit, which can effectively identify branch instructions in the program execution flow and accurately determine the starting address of the next instruction. The fetch block is generated based on the fetch address, ensuring that the instructions contained in the fetch block are a valid instruction sequence that the processor is about to execute. This significantly improves the accuracy of instruction prefetching, reduces invalid instruction fetching and cache access caused by prediction errors, thereby effectively reducing the power consumption of the processor front end, improving instruction prefetching efficiency, and avoiding unnecessary pipeline bubbles.

[0061] In some embodiments, generating an instruction fetch block based on the address includes: obtaining the identification information of the address; if the identification information is a preset first information, packaging the address to generate an instruction fetch block; if the identification information is a preset second information, predicting a first set of index information and a first path information based on the predictor of the branch prediction unit, and packaging the address, the first set of index information and the first path information to generate an instruction fetch block.

[0062] In this embodiment, during the generation of the instruction fetch block, the identification information of the address can be obtained to determine whether group indexing and path prediction are needed using the address. When the identification information is a preset first piece of information, it indicates that group indexing and path prediction are not needed using the address; when the identification information is a second piece of information, it indicates that group indexing and path prediction are needed using the address. The first piece of information can be a specific bit value, such as "0", or a predefined address range or address pattern. When the address falls within this range or conforms to this pattern, it is considered to carry the first piece of information. In this case, only the address is packaged to generate the instruction fetch block. The second piece of information can be a bit value opposite to the first piece of information, such as "1", or another predefined address range or address pattern.

[0063] The predictor can be a prediction table of a set of indexes and paths, which uses a portion of the address as an index to look up the first set of index information and the first path information stored in advance; or, the predictor can use a hash function or other algorithm to calculate the predicted first set of index information and the first path information based on the address.

[0064] In some embodiments, reading an instruction fetch block from the instruction fetch target queue based on the instruction fetch unit to read a target instruction from the instruction cache unit includes: reading the instruction fetch block from the instruction fetch target queue based on the instruction fetch unit to obtain a fetch address; sending a first read request to the instruction cache unit based on the fetch address based on the instruction fetch unit, and receiving return information from the instruction cache unit in response to the first read request to obtain the target instruction from the return information.

[0065] In this embodiment, during the instruction prefetching process of the processor front end, the instruction fetch unit can read the fetch block from the fetch target queue to obtain the fetch address, and send a first read request to the instruction cache unit based on the obtained fetch address. After receiving the return information from the instruction cache unit in response to the first read request, the target instruction is obtained from the return information. After obtaining the fetch address, the instruction fetch unit can construct a standard read request that contains only the fetch address of the target instruction and does not rely on any prediction information (such as set index / path).

[0066] After receiving the first read request, the instruction cache unit will search for the corresponding instruction data in the cache according to the address, and send the return information containing the target instruction data to the instruction fetch unit. After receiving the return information, the instruction fetch unit will parse and extract the required target instruction for subsequent decoding and execution.

[0067] In this application, by directly obtaining the address and sending a standard first read request, read failures and additional correction steps caused by relying on invalid prediction information are avoided, thereby ensuring the accuracy and timeliness of instruction acquisition. This effectively solves the problem of decreased instruction read efficiency and increased power consumption when prediction information is missing or invalid. Consequently, regular instruction reads can be performed directly in scenarios where Set / Way prediction is not performed, reducing unnecessary prefetch operations and thus lowering the access power consumption of the instruction cache unit. This ensures smooth and efficient instruction flow in various prediction scenarios.

[0068] In some embodiments, reading a target instruction from an instruction cache unit based on a first set of index information and a first path information includes: sending a second read request for the target instruction to the instruction cache unit based on the fetch address, the first set of index information, and the first path information; if the instruction cache unit returns failure information for the second read request to the instruction fetch unit, sending a first read request to the instruction cache unit based on the fetch address, and receiving return information to obtain the target instruction from the return information.

[0069] In this embodiment, when using prediction information to read instructions, a second read request for the target instruction can be sent to the instruction cache unit according to the address, the first set of index information and the first path information. This allows the target instruction to be read from the instruction cache unit quickly and efficiently, avoiding the need to traverse all Way tag information in traditional instruction cache unit access, thereby improving access speed and reducing power consumption.

[0070] Specifically, the instruction fetch unit can encapsulate the fetch address, the first set of index information, and the first path information into a specific read request message, and send it to the control logic of the instruction cache unit via the internal bus or a dedicated interface. After receiving this request, the instruction cache unit directly locates the cache line based on the provided index and path information and attempts to read the data.

[0071] like Figure 3 As shown, when the instruction cache unit returns a failure message (read failure) for the second read request to the instruction fetch unit, it can be determined whether the instruction read attempt based on the predicted information (the first set of index information and the first path information) was successful. Specifically, if the predicted information is inaccurate or the corresponding cache line in the instruction cache unit has been replaced or invalidated, the instruction cache unit will return a failure message, indicating that the instruction fetch unit needs to use other methods to obtain the instruction.

[0072] Failure information can be understood as error codes or status signals generated by the instruction cache unit, which are sent back to the instruction fetch unit via the data bus or status register. The instruction fetch unit can determine whether the fetch has failed by monitoring the error codes or status signals.

[0073] Upon receiving a failure message, the instruction fetch unit will abandon the predicted first set of index information and first path information, and instead adopt a traditional, more reliable reading method. Specifically, it will send a regular read request to the instruction cache unit using the fetch address to ensure that the target instruction can be correctly obtained in the end.

[0074] Specifically, after receiving a failure message, the instruction fetch unit reconstructs a first read request that does not contain the first set of index information or the first path information. This first read request only contains the address of the target instruction and is sent to the instruction cache unit. Upon receiving the first read request, the instruction cache unit performs standard tag matching and way traversal operations to find the correct cache line, read the instruction data, and return it to the instruction fetch unit. The instruction fetch unit then captures this return information, parses the target instruction from it, and passes the instruction to the subsequent pipeline stages of the processor.

[0075] Based on efficient instruction reading using the first set of index information and the first path information, this application introduces a fallback mechanism for prediction failure. When the instruction cache unit returns failure information for the second read request, the instruction fetch unit can promptly identify the invalidity of the prediction information and quickly switch to the first read request based on the fetch address. This ensures that the target instruction can be reliably obtained, effectively avoiding instruction read interruptions and pipeline bubbles caused by prediction failure. It guarantees the continuity and stability of the processor front-end instruction supply, significantly improves the robustness of instruction reading, and still enjoys the performance and power consumption advantages brought by Set / Way prediction when the prediction is successful, achieving a balance between prediction efficiency and read reliability.

[0076] In some embodiments, after receiving the return information of the instruction cache unit in response to the first read request to obtain the target instruction from the return information, the method further includes: obtaining a second set of index information and a second path information of the target instruction from the return information based on the instruction fetch unit, so as to train the predictor.

[0077] In this embodiment, the second set of index information and the second path information can be understood as the group index information and path information extracted by the instruction fetch unit from the response data returned by the instruction cache unit, indicating that the target instruction is actually stored in the instruction cache unit. The second set of index information and the second path information represent the actual physical location of the target instruction in the instruction cache unit.

[0078] Specifically, this application utilizes the accurate second set of index information and second path information actually returned by the instruction cache unit to train the predictor. This enables the predictor to learn and adjust based on the actual cache access results, thereby significantly improving the accuracy of its predicted index information and path information. Consequently, it reduces the occurrence of instruction cache unit access failures or the need to fall back to the normal read mode due to prediction errors. This not only avoids unnecessary prefetch requests and reduces repeated tag reads of the instruction cache unit, thus effectively saving power, but also reduces bubbles introduced by prediction failures in the pipeline, improves the overall instruction fetch performance of the processor, achieves continuous optimization of the predictor, and ensures the efficiency and accuracy of the instruction prefetch mechanism.

[0079] In some embodiments, based on the instruction fetch unit, obtaining a second set of index information and a second path information of the target instruction from the returned information to train a predictor includes: based on the instruction fetch unit, sending the failure information, the second set of index information and the second path information returned by the instruction cache unit to the instruction fetch unit to the branch prediction unit; and based on the branch prediction unit, training a predictor according to the failure information, the second set of index information and the second path information.

[0080] In this embodiment, as Figure 3 As shown, when the instruction fetch unit sends a read request (e.g., a first read request) to the instruction cache unit, the instruction cache unit, upon successfully locating and returning the target instruction, encapsulates the actual storage location information of the target instruction in the cache—that is, the second set of index information and the second path information—in the return information and sends it back to the instruction fetch unit. Upon receiving this return information, the instruction fetch unit can extract the required second set of index information and second path information by parsing the preset data format.

[0081] After extracting the required second set of index information and second path information, the instruction fetching unit can send the failure information, the second set of index information and the second path information to the branch prediction unit. The branch prediction unit trains the predictor based on the failure information, the second set of index information and the second path information.

[0082] The branch prediction unit contains a predictor that maintains one or more prediction tables. When it receives failure information, a second set of index information, and a second path information, the branch prediction unit identifies the corresponding prediction record based on the failure information and updates the record using the second set of index information and the second path information.

[0083] In this application, when the instruction cache unit returns failure information, the instruction fetch unit can send this failure information along with the correct second set of index information and second path information to the branch prediction unit. After receiving this key information, the branch prediction unit can perform targeted training and updates on the predictor, ensuring that the predictor can learn and correct its erroneous set index and path predictions in a timely manner. This significantly improves set index and path prediction, reduces repeated accesses to the instruction cache unit or invalid prefetch requests caused by prediction errors, thereby reducing processor power consumption and avoiding bubbles introduced into the pipeline due to invalid set indexes and paths, thus improving the overall execution efficiency of the processor.

[0084] In some embodiments, training a predictor based on a branch prediction unit, according to failure information, a second set of index information, and a second path information, includes: determining the number of times the predictor fails to predict the target instruction based on the failure information; if the number of failures is less than a preset threshold, replacing the first set of index information and the first path information predicted by the predictor according to the second set of index information and the second path information to update the prediction record of the current target instruction predicted by the predictor; if the number of failures is greater than the preset threshold, marking the fetch block to instruct the predictor of the branch prediction unit to stop predicting the fetch address.

[0085] In this embodiment, the branch prediction unit can maintain a counter associated with each fetch address or fetch block. When a failure message is received, the corresponding counter value is incremented. Alternatively, the branch prediction unit can use a lookup table or hash table to store the number of prediction failures for each fetch address, updating the count of the corresponding entry each time a prediction fails.

[0086] When the number of failures is less than a preset threshold, the first set of index information and the first path information predicted by the predictor are replaced according to the second set of index information and the second path information. This updates the prediction record of the current target instruction predicted by the predictor, corrects the predictor's errors, and improves the predictor's accuracy. Specifically, after receiving the correct second set of index information and the second path information, the branch prediction unit can directly overwrite the old first set of index information and the first path information stored in the predictor associated with the address.

[0087] When the number of failures exceeds a preset threshold, the fetch block is marked to instruct the predictor of the branch prediction unit to stop predicting the fetch address. This allows the group indexing and path prediction to be stopped when the prediction failure rate of a certain fetch address is too high, thus avoiding the power consumption and performance overhead caused by invalid predictions and switching to the conventional instruction cache access method.

[0088] In addition, the branch prediction unit can also set a specific flag bit for the corresponding fetch address in its internal prediction table, such as a "disable prediction" bit. When the flag bit is set, subsequent prediction requests for the fetch address will directly return a fetch block without carrying group index and path information.

[0089] In this application, by monitoring the number of prediction failures and making intelligent decisions based on preset thresholds, the problem of frequent prediction failures is effectively solved, continuous invalid predictions are avoided, and unnecessary power consumption and latency are reduced. This enables the processor to manage group indexing and path prediction more intelligently. For instructions with high prediction accuracy, group indexing and path prediction are continued to be used to improve performance and reduce power consumption, while for instructions with low prediction accuracy, prediction is stopped in time to avoid the waste of resources caused by invalid predictions. Thus, while ensuring instruction prefetching efficiency, overall power consumption and performance are optimized.

[0090] In the instruction prefetching method provided in this embodiment of the invention, a fetch block for the target instruction is predicted and generated based on a branch prediction unit, and the fetch block is sent to the fetch target queue. If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit. Based on the instruction fetch unit, the fetch block is read from the fetch target queue to read the target instruction from the instruction cache unit. If the fetch block carries the first set of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first set of index information and the first path information. This achieves prefetching only when the fetch block does not carry index and path information, thereby effectively distinguishing between valid and invalid prediction information, avoiding redundant operations, reducing redundant prefetch requests, and reducing processor power consumption.

[0091] In some embodiments, the present invention also provides a processor 110, which is used to execute any embodiment of the aforementioned instruction prefetching method.

[0092] Specifically, please refer to Figure 4 , Figure 4 This is a schematic block diagram of the processor 110 provided by the present invention.

[0093] like Figure 4 As shown, the processor 110 provided in this application has a branch prediction unit 111, an instruction fetch target queue 112, an instruction fetch unit 113 and an instruction cache unit 114 at its front end.

[0094] Branch prediction unit 111 is used to predict and generate the fetch block of the target instruction and send the fetch block to the fetch target queue 112; fetch target queue 112 is used to send a prefetch request to instruction cache unit 114 to cache the target instruction if the fetch block does not carry the first set of index information and the first path information of the target instruction; instruction fetch unit 113 is used to read the fetch block from fetch target queue 112 to read the target instruction from instruction cache unit 114; instruction fetch unit 113 is also used to read the fetch block from fetch target queue 112 to obtain the first set of index information and the first path information if the fetch block carries the first set of index information and the first path information, and read the target instruction from instruction cache unit 114 according to the first set of index information and the first path information.

[0095] The processor 110 provided in this application embodiment can predict and generate the fetch block of the target instruction based on the branch prediction unit and send the fetch block to the fetch target queue. If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit. Based on the instruction fetch unit, the fetch block is read from the fetch target queue to read the target instruction from the instruction cache unit. If the fetch block carries the first set of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first set of index information and the first path information. This realizes that prefetching is only performed when the fetch block does not carry index and path information, thereby effectively distinguishing between the valid and invalid prediction information, avoiding redundant operations, reducing redundant prefetch requests, and reducing the power consumption of the processor.

[0096] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the processor 110 and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0097] The instruction prefetching method provided in this application can be implemented as a computer program, which can, for example, Figure 5 It runs on the electronic device shown.

[0098] Please see Figure 5 , Figure 5 This is a schematic block diagram of the electronic device 100 provided by the present invention.

[0099] See Figure 5The electronic device 100 includes a processor 110, a memory, and a network interface 105 connected via a system bus 101. The memory may include a storage medium 103 and internal memory 104.

[0100] The storage medium 103 may store an operating system 1031 and a computer program 1032. When the computer program 1032 is executed, it causes the processor 110 to perform an instruction prefetching method.

[0101] The processor 110 provides computing and control capabilities to support the operation of the entire electronic device 100.

[0102] The internal memory 104 provides an environment for the execution of the computer program 1032 in the non-volatile storage medium 103. When the computer program 1032 is executed by the processor 110, the processor 110 can execute the instruction prefetching method.

[0103] The network interface 105 is used for network communication, such as providing data transmission. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the electronic device 100 to which the present invention is applied. The specific electronic device 100 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0104] The processor 110 is used to run a computer program 1032 stored in memory to perform the following functions: predicting and generating a fetch block of the target instruction based on the branch prediction unit, and sending the fetch block to the fetch target queue; if the fetch block does not carry the first set of index information and the first path information of the target instruction, sending a prefetch request to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit; reading the fetch block from the fetch target queue based on the instruction fetch unit to read the target instruction from the instruction cache unit; if the fetch block carries the first set of index information and the first path information, reading the fetch block from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and reading the target instruction from the instruction cache unit according to the first set of index information and the first path information.

[0105] Those skilled in the art will understand that Figure 5The embodiments of the electronic device 100 shown do not constitute a limitation on the specific configuration of the electronic device 100. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, in some embodiments, the electronic device 100 may include only a memory and a processor 110. In such embodiments, the structure and function of the memory and processor 110 are different from those shown. Figure 5 The embodiments shown are consistent and will not be described again here.

[0106] It should be understood that, in this embodiment of the invention, the processor 110 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor 110 may be a microprocessor or any conventional processor 110, etc.

[0107] According to one aspect of this application, a computer program product or computer program is also provided, comprising computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the following steps: predicting and generating a fetch block of a target instruction based on a branch prediction unit, and sending the fetch block to a fetch target queue; if the fetch block does not carry a first set of index information and a first path information of the target instruction, sending a prefetch request to an instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit; reading the fetch block from the fetch target queue based on the instruction fetch unit to read the target instruction from the instruction cache unit; if the fetch block carries the first set of index information and the first path information, reading the fetch block from the fetch target queue based on the instruction fetch unit to obtain the first set of index information and the first path information, and reading the target instruction from the instruction cache unit according to the first set of index information and the first path information.

[0108] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0109] In another embodiment of the present invention, a computer storage medium is provided. This storage medium can be a non-volatile computer-readable storage medium or a volatile storage medium. The storage medium stores a computer program 1032, which, when executed by a processor 110, performs the following steps: based on a branch prediction unit, predicting and generating a fetch block for a target instruction, and sending the fetch block to a fetch target queue; if the fetch block does not carry the first set of index information and the first path information of the target instruction, sending a prefetch request to an instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit; based on an instruction fetch unit, reading the fetch block from the fetch target queue to read the target instruction from the instruction cache unit; if the fetch block carries the first set of index information and the first path information, based on the instruction fetch unit, reading the fetch block from the fetch target queue to obtain the first set of index information and the first path information, and reading the target instruction from the instruction cache unit according to the first set of index information and the first path information.

[0110] The storage medium can be any computer-readable storage medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0111] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0112] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0113] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0114] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods provided in the various embodiments of this application.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An instruction prefetching method, characterized in that, The method is applied to the front end of a processor, wherein the front end of the processor includes a branch prediction unit, an instruction fetch target queue, an instruction fetch unit, and an instruction cache unit, and includes: Based on the branch prediction unit, the fetch block of the target instruction is predicted and generated, and the fetch block is sent to the fetch target queue; the fetch block is a continuous group of instructions of fixed or variable size; If the fetch block does not carry the first set of index information and the first path information of the target instruction, a prefetch request is sent to the instruction cache unit based on the fetch target queue to cache the target instruction in the instruction cache unit; Based on the instruction fetch unit, the instruction fetch block is read from the instruction fetch target queue to obtain the fetch address of the target instruction, so as to read the target instruction from the instruction cache unit; If the instruction fetch block carries the first set of index information and the first path information, the instruction fetch unit reads the instruction fetch block from the instruction fetch target queue to obtain the first set of index information and the first path information, and reads the target instruction from the instruction cache unit according to the first set of index information and the first path information.

2. The instruction prefetching method according to claim 1, characterized in that, The step of predicting and generating the fetch block for the target instruction based on the branch prediction unit includes: Based on the branch prediction unit, the address of the target instruction is predicted by jumping, and the instruction fetch block is generated according to the address.

3. The instruction prefetching method according to claim 2, characterized in that, The step of generating the fetch block based on the address includes: Obtain the identification information of the address being retrieved; If the identification information is the preset first information, the address is packaged to generate the fetch block; If the identification information is the preset second information, the predictor of the branch prediction unit predicts the first set of index information and the first path information according to the address, and packages the address, the first set of index information and the first path information to generate the index block.

4. The instruction prefetching method according to claim 3, characterized in that, The step of reading the instruction fetch block from the instruction fetch target queue based on the instruction fetch unit, and then reading the target instruction from the instruction cache unit, includes: Based on the instruction fetch unit, the instruction fetch block is read from the instruction fetch target queue to obtain the fetch address; Based on the instruction fetching unit, a first read request is sent to the instruction cache unit according to the fetch address, and the return information of the instruction cache unit in response to the first read request is received, so as to obtain the target instruction from the return information.

5. The instruction prefetching method according to claim 4, characterized in that, The step of reading the target instruction from the instruction cache unit according to the first set of index information and the first path information includes: Based on the address, the first set of index information, and the first path information, a second read request for the target instruction is sent to the instruction cache unit. If the instruction cache unit returns failure information for the second read request to the instruction fetch unit, the instruction fetch unit sends the first read request to the instruction cache unit based on the fetch address, and receives the return information to obtain the target instruction from the return information.

6. The instruction prefetching method according to claim 4 or 5, characterized in that, After the instruction buffer unit receives the return information in response to the first read request to obtain the target instruction from the return information, the method further includes: Based on the instruction fetching unit, the second set of index information and the second path information of the target instruction are obtained from the returned information to train the predictor.

7. The instruction prefetching method according to claim 6, characterized in that, The step of obtaining the second set of index information and the second path information of the target instruction from the returned information based on the instruction fetching unit to train the predictor includes: Based on the instruction fetching unit, the failure information returned by the instruction cache unit to the instruction fetching unit, the second set of index information, and the second path information are sent to the branch prediction unit; Based on the branch prediction unit, the predictor is trained according to the failure information, the second set of index information, and the second path information.

8. The instruction prefetching method according to claim 7, characterized in that, The step of training the predictor based on the branch prediction unit, according to the failure information, the second set of index information, and the second path information, includes: Based on the branch prediction unit, and according to the failure information, the number of times the predictor fails to predict the target instruction is determined; If the number of failures is less than a preset threshold, the first set of index information and the first path information predicted by the predictor are replaced according to the second set of index information and the second path information, so as to update the prediction record of the predictor currently predicting the target instruction. If the number of failures exceeds the preset threshold, the fetch block is identified to instruct the predictor of the branch prediction unit to stop predicting the fetch address.

9. A processor, characterized in that, The processor's front end includes a branch prediction unit, an instruction fetch target queue, an instruction fetch unit, and an instruction cache unit; The branch prediction unit is used to predict and generate the fetch block of the target instruction and send the fetch block into the fetch target queue; the fetch block is a continuous group of instructions of fixed or variable size; The instruction fetch target queue is used to send a prefetch request to the instruction cache unit if the instruction fetch block does not carry the first set of index information and the first path information of the target instruction, so as to cache the target instruction in the instruction cache unit; The instruction fetch unit is used to read the instruction fetch block from the instruction fetch target queue to obtain the fetch address of the target instruction, so as to read the target instruction from the instruction cache unit; The instruction fetching unit is further configured to, if the instruction fetching block carries the first set of index information and the first path information, read the instruction fetching block from the instruction fetching target queue to obtain the first set of index information and the first path information, and read the target instruction from the instruction cache unit according to the first set of index information and the first path information.

10. An electronic device, characterized in that, The system includes a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the instruction prefetching method according to any one of claims 1 to 8.

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