Cache hit rate determination method, electronic device, and computer-readable storage medium

Abstract

This application discloses a cache hit rate determination method, an electronic device, and a computer-readable storage medium. The method includes: in response to receiving a cache hit rate determination instruction, obtaining accessed data according to the cache hit rate determination instruction; determining a target hit rate statistical method for the accessed data based on the current access frequency of the accessed data; and calculating the hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data. This can avoid unnecessary resource consumption.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method for determining cache hit rate, an electronic device, and a computer-readable storage medium. Background Technology

[0002] Cache hit rate refers to the percentage of accessed data that is successfully retrieved from the cache. By obtaining the cache hit rate, one can gain a comprehensive understanding of the cache's performance during data access and measure its current capabilities.

[0003] However, with the rapid increase in accessed data, and the need to calculate cache hit rates for a large amount of data, using the traditional method of uniformly calculating all accessed data would consume a significant amount of memory and resources. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a cache hit rate determination method, electronic device, and computer-readable storage medium that can reduce resource consumption during the cache hit rate determination process.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a cache hit rate determination method, the cache hit rate determination method comprising: in response to receiving a cache hit rate determination instruction, obtaining access data according to the cache hit rate determination instruction; determining a target hit rate statistical method for the access data according to the current access frequency of the access data; calculating the hit rate of the access data using the target hit rate statistical method of the access data, and obtaining the cache hit rate of the access data.

[0006] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, including a memory and a processor, wherein the memory stores program instructions, and the processor retrieves the program instructions from the memory to execute the above-mentioned cache hit rate determination method.

[0007] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a computer-readable storage medium including program data, wherein the program data is used to implement the above-mentioned cache hit rate determination method when executed by a processor.

[0008] The cache hit rate determination method of this application responds to a cache hit rate determination instruction by obtaining accessed data according to the instruction; determining a target hit rate statistical method for the accessed data based on the current access frequency of the accessed data; and calculating the cache hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data. Thus, by using the current access frequency of the accessed data, a target hit rate statistical method more suitable for the accessed data can be obtained, avoiding unnecessary resource consumption. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a flowchart illustrating an exemplary embodiment of the cache hit rate determination method shown in this application; Figure 2 yes Figure 1 A flowchart illustrating an exemplary embodiment of step S120 in the cache hit rate determination method is shown. Figure 3 This is a schematic diagram of a framework of an exemplary embodiment of the second statistical method shown in this application; Figure 4 yes Figure 1 A flowchart illustrating an exemplary embodiment of the cache hit rate determination method after step S130 is shown. Figure 5 This is a flowchart illustrating another exemplary embodiment of the cache hit rate determination method shown in this application; Figure 6 This is a schematic diagram of an exemplary embodiment of the cache hit rate determination device shown in this application; Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application; Figure 8 This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0011] First, it's important to note that in distributed caching systems, performance is monitored and optimized by obtaining the cache hit rate. Current methods for determining the cache hit rate primarily involve storing cache call records in internal or external caches to update the hit rate in real time. However, with the rapid increase in data volume, this approach consumes a significant amount of memory and results in unnecessary resource waste.

[0012] Based on this, embodiments of this application propose a cache hit rate determination method, an electronic device, and a computer-readable storage medium. Different target hit rate statistical methods are determined according to the current access frequency of the accessed data, reducing unnecessary resource waste. For details, please refer to [reference needed]. Figure 1 , Figure 1 This is a flowchart illustrating an exemplary embodiment of the cache hit rate determination method shown in this application.

[0013] The execution entity of the cache hit rate determination method can be a terminal device, a server, or other processing device. The terminal device can be a user equipment (UE), computer, mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The execution entity of the cache hit rate determination method can also be a cache hit rate determination device. In some possible implementations, the cache hit rate determination method can be implemented by the processor calling computer-readable instructions stored in memory.

[0014] Specifically, the cache hit rate determination method in this embodiment includes the following steps: S110: In response to receiving a cache hit rate determination instruction, retrieve the access data according to the cache hit rate determination instruction.

[0015] A cache hit rate determination command is used to instruct a cache hit rate determination device to obtain the cache hit rate of accessed data. For example, the cache hit rate determination command can be initiated to the cache hit rate determination device when performance optimization, troubleshooting, or cost optimization is needed. Alternatively, the cache hit rate can be integrated as a core metric into a monitoring system for continuous monitoring. The cache hit rate determination command can be initiated by the user to the cache hit rate determination device, or it can be automatically initiated by the cache hit rate determination device when necessary.

[0016] Access data refers to data that needs to be retrieved from the cache. For example, the cache hit rate determination device can obtain access data from the access records of the cache system. These access records include current access records and / or historical access records. For instance, after receiving a cache hit rate determination instruction, the device can count several access records over a subsequent period starting from the current time point to obtain access data; alternatively, it can use the current time point as the termination node to count several access records over a period of time backwards to obtain access data, etc. The cache hit rate determination instruction includes the cache system to be detected. After receiving the instruction, the device retrieves the cache system to be detected from the instruction and obtains access data from it in real time.

[0017] After receiving a cache hit rate determination instruction, the cache hit rate determination device obtains the cache system to be detected from the cache hit rate determination instruction and obtains the corresponding access data from the cache system to be detected.

[0018] S120: Determine the target hit rate statistical method for accessed data based on the current access frequency of the accessed data.

[0019] The current access frequency refers to the frequency with which data is requested from the cache system within a certain period of time. For example, after acquiring accessed data, the cache hit rate determination device determines the current access frequency of the accessed data based on the number of requests for the accessed data within a certain period. In some embodiments, the number of times the accessed data is accessed within a certain period can be determined as the current access frequency of the accessed data. In other embodiments, the current access frequency of the accessed data can be selected from a preset category based on the number of times the accessed data is accessed within a certain period. The preset category can be divided into low-frequency access and high-frequency access, or it can be divided into low-frequency access, low-to-medium frequency access, medium-to-high frequency access, and high-frequency access, etc. The number of times the accessed data is requested within a certain period can be obtained using a counting algorithm, such as Count-Min Sketch (CMS) or a Bloom filter.

[0020] The target hit rate statistics method refers to the method used to calculate the cache hit rate of accessed data. In this embodiment, the target hit rate statistics method is determined based on the current access frequency of the accessed data. For example, the current access frequency can be set to be directly proportional to the real-time performance of the target hit rate statistics method; the higher the current access frequency, the higher the real-time performance of the target hit rate statistics method.

[0021] The cache hit rate determination device acquires access data and counts the current access frequency of the access data, and determines the corresponding target hit rate calculation method based on the current access frequency of the access data.

[0022] S130: Calculate the cache hit rate of accessed data by using the target hit rate statistics method.

[0023] Cache hit rate refers to the percentage of accessed data that is successfully retrieved from the cache. For example, after determining the target hit rate statistical method for the accessed data, the cache hit rate determining device obtains the cache hit rate of the accessed data by analyzing the access results using the target hit rate statistical method.

[0024] As can be seen, the cache hit rate determination method in this embodiment responds to receiving a cache hit rate determination instruction by obtaining accessed data according to the instruction; determining a target hit rate statistical method for the accessed data based on the current access frequency of the accessed data; and calculating the hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data. Thus, by using the current access frequency of the accessed data, a target hit rate statistical method more suited to the accessed data can be obtained, avoiding unnecessary resource consumption.

[0025] Based on the above embodiments, the embodiments of this application adopt... Figure 2 The flowchart details how to determine the target hit rate of access data based on the current access frequency. Please refer to [link / reference]. Figure 2 , Figure 2 yes Figure 1 The illustrated flowchart shows an exemplary embodiment of step S120 in the cache hit rate determination method. Specifically, step S120 further includes the following steps: S210: In response to the current access frequency of the accessed data indicating that the accessed data is high-frequency accessed data, the first statistical method is determined as the target hit rate statistical method of the accessed data.

[0026] In this embodiment, the cache hit rate determination device categorizes accessed data into high-frequency access data and low-frequency access data, where high-frequency access data can also be referred to as hot keys, and low-frequency access data can also be referred to as cold keys. For example, the current access frequency of accessed data can be used to determine whether it is high-frequency or low-frequency access data. In some embodiments, when the current access frequency of accessed data is greater than a preset access frequency threshold, the accessed data is determined to be high-frequency access data; when the current access frequency of accessed data is less than or equal to the preset access frequency threshold, the accessed data is determined to be low-frequency access data. In other embodiments, when the current access frequency of accessed data is high-frequency, the accessed data is considered high-frequency access data; when the current access frequency of accessed data is low-frequency, the accessed data is considered low-frequency access data.

[0027] In other embodiments, the cache hit rate determination device may further obtain a second total number of requests for accessing data; calculate the standard deviation of the number of requests for accessing data within a third preset time period to obtain the standard deviation value within the third preset time period; and determine the current access frequency of the accessed data based on the second total number of requests and the standard deviation value. Therefore, combining the second total number of requests and the standard deviation value to determine the current access frequency can reduce the error of the current access frequency.

[0028] The second total request count can be the total number of times the cache system has been accessed since the system started. Alternatively, it can be obtained based on a window, the length of which can be set as needed, for example, to 5 minutes. Furthermore, an exponential decay mechanism can be introduced to reduce the second total request count for older data. As an example, the CMS algorithm can be used to quickly determine the second total request count. The CMS algorithm can be a hash matrix with 4 columns wide and 8 rows deep, with a fixed memory consumption, such as 256KB.

[0029] The third preset time period can be set according to actual needs. To obtain high-frequency access data with sudden increases in access counts, the standard deviation of access data within the third preset time period can be obtained to determine whether there are strong fluctuations in access data within that time period, thus obtaining accurate high-frequency access data. The third preset time period can be any value between 0.5 seconds and 1 second.

[0030] Standard deviation is a statistic used to measure the dispersion of data, reflecting how well a set of data is distributed relative to its mean. The cache hit rate determination device can calculate the standard deviation of the number of requests to access data within a third preset time period to determine the degree of fluctuation in the number of requests within that period. The higher the fluctuation in the number of requests to access data within the third preset time period, the more likely the accessed data is to be frequently accessed.

[0031] In some embodiments, the cache hit rate determination device can determine the current access frequency of the accessed data based on the second total number of requests to access the data. For example, when the second total number of requests to access the data is greater than a preset number of requests, the current access frequency of the accessed data is determined to be high-frequency access, and the accessed data is high-frequency access data; when the second total number of requests to access the data is less than or equal to the preset number of requests, the current access frequency of the accessed data is determined to be low-frequency access, and the accessed data is low-frequency access data.

[0032] In other embodiments, the cache hit rate determination device can determine the current access frequency of the accessed data based on the standard deviation of the number of requests for accessed data within a third preset time period. For example, when the absolute value of the standard deviation of the accessed data within the third preset time period is greater than a preset fluctuation threshold, the current access frequency of the accessed data is determined to be high-frequency access, and the accessed data is high-frequency accessed data; when the absolute value of the standard deviation of the accessed data within the third preset time period is less than or equal to the preset fluctuation threshold, the current access frequency of the accessed data is determined to be low-frequency access, and the accessed data is low-frequency accessed data.

[0033] In other embodiments, the cache hit rate determination device can determine the current access frequency of the accessed data based on the second total number of requests and the standard deviation. For example, when the second total number of requests is greater than a preset number of requests and the absolute value of the standard deviation is greater than a preset fluctuation threshold, the current access frequency of the accessed data is determined to be high-frequency access, and the accessed data is high-frequency access data; when the second total number of requests is less than or equal to the preset number of requests or the absolute value of the standard deviation is less than or equal to the preset fluctuation threshold, the current access frequency of the accessed data is determined to be low-frequency access, and the accessed data is low-frequency access data.

[0034] It should be noted that when obtaining the current access frequency of access data by acquiring the second total request count and standard deviation mutation through the CMS algorithm, a two-dimensional linear compensation algorithm can be used to control the error rate to be less than 0.1%. Specifically, the root cause of hash collisions in CMS is determined to be that when multiple keys hash to the same bucket in a traditional CMS, the count accumulates too high, resulting in the count of hot keys being basically accurate, while the count of cold keys is too high due to collision issues. This embodiment modifies the data structure of CMS to a 4×8 matrix, with rows representing hash functions and columns representing buckets. Each bucket stores two fields: the original count and the compensation offset. When key K is written, its position in the 4 rows is calculated, and the count of the corresponding bucket in each row is incremented by 1. If the original key set of the bucket is not equal to {K}, a compensation flag is triggered, and a collision compensation value is obtained. When reading the count of key K, a two-dimensional correction is performed, including inter-row linear correction, taking the second smallest value in the 4 rows, and inter-column compensation correction, subtracting the average compensation offset of the 4 rows. Let the single-bucket collision probability be p. After double correction, the theoretical error ≈ p² × average collision offset. When p = 5% (reasonable hash distribution): error ≈ (0.05)² × 10 (assuming average offset) = 0.0025, which is further compressed to <0.1% by dynamic weight α.

[0035] When the cache hit rate determination device determines that the current access frequency of accessed data indicates that the accessed data is high-frequency accessed data, it sets the first statistical method as the target hit rate statistical method for the accessed data. In response to the target hit rate statistical method being the first statistical method, it acquires the number of hits and misses of the accessed data within a first preset time period. A hit indicates that the accessed data has been successfully retrieved from the cache; the cache hit rate of the accessed data is determined based on the number of hits and misses. This real-time statistical analysis of the accessed data within the first preset time period yields a cache hit rate with stronger real-time performance and higher accuracy.

[0036] For example, the first statistical method can be precise real-time statistics, and the first preset time period can be in the millisecond range, such as any value between 10 and 15 milliseconds. It should be noted that the first preset time period can be the time period closest to the current time to improve the real-time performance of the cache hit rate. The cache hit rate determination device counts the number of hits and misses of accessed data within the first preset time period, and determines the cache hit rate of the accessed data based on the number of hits and misses. For example, the ratio between the number of hits and the sum of the number of hits and misses can be determined as the cache hit rate of the accessed data.

[0037] Specifically, when the cache hit rate determination device determines that the accessed data is frequently accessed, it can store the access results of the accessed data in a sliding window circular buffer. If the access result indicates that the data was successfully retrieved from the cache, the hit count is incremented by 1; if the access result indicates that the data was not successfully retrieved from the cache, the miss count is incremented by 1. The sliding window circular buffer can have 128 time slots, each slot recording the number of hits and misses within 10 milliseconds. The cache hit rate of the accessed data is obtained by counting the number of hits and misses within the window. The window size can be determined according to actual needs, for example, it can be 10 milliseconds. As an example, the cache hit rate determination device can determine the cache hit rate based on the data from the 10 most recent slots at the pointer position. For example, if the number of hits in the last 10 slots is 20 and the number of misses is 5, then the cache hit rate is 20 / (20+5)*100%=80%.

[0038] S220: In response to the current access frequency of the access data indicating that the access data is low-frequency access data, the second statistical method is determined as the target hit rate statistical method for the access data.

[0039] When the cache hit rate determination device determines that the current access frequency of accessed data indicates that the accessed data is low-frequency access data, it selects the second statistical method as the target hit rate statistical method for the accessed data. In response to the target hit rate statistical method being the second statistical method, it obtains the first total number of requests for the accessed data within a second preset time period; within the second preset time period, it performs probability sampling on the requests for the accessed data using a preset sampling probability to obtain the sampled hit count; and it determines the cache hit rate of the accessed data based on the first total number of requests and the sampled hit count. This solves the problem of low statistical value but high resource consumption of low-frequency accessed data by statistically analyzing its cache hit rate through probability sampling.

[0040] For example, the second statistical method can be probability sampling statistics. The cache hit rate determination device can obtain the first total number of requests and the sampled hit count within the second preset time period, and determine the cache hit rate of the accessed data based on the first total number of requests and the sampled hit count.

[0041] The first total number of requests can be estimated using a probability cardinality estimation algorithm on the access data within a second preset time period. The probability counting estimation algorithm can be the HyperLogLog (HLL) algorithm. Specifically, the cache hit rate determination device hashes the key and ID of each request to obtain a hash value; then it performs bucketing, with each bucket recording the longest leading zero count of the hash value. The first total number of requests is then estimated using the number of leading zeros across all buckets. As an example, HLL calculates the first total number of requests for a single access to data as 100,000.

[0042] The sampled hit count refers to the number of hits obtained from requests accessing data through probability sampling. The cache hit rate determination device no longer stores all requests accessing data within a second preset time period, but instead obtains a subset of requests from all requests accessing data within the second preset time period through probability sampling. This method can reduce resource requirements. The algorithm for obtaining the sampled hit count can be the Theta Sketch algorithm. Specifically, the cache hit rate determination device sets a preset sampling probability to perform probability sampling on requests accessing data and records the access result of each request, indicating whether the request to access data was hit. The sampled access results are hashed to obtain a hash value. The sampled access results are then counted as the number of successful data retrieval hits. After obtaining the sampled hit count, the sampled hit rate can be determined based on the total number of samples and the sampled hit count. Furthermore, a weighted amplification can be applied based on a preset sampling probability. For example, if the preset sampling probability is 0.01 and the total number of samples is 1000 requests, with 20 requests being successfully sampled, then the sampling hit rate can be [(20 / 1000) / 0.01]*(20 / 1000), which is approximately 4%, amplified by 2 times.

[0043] After obtaining the first total number of requests and the sampled hit count for accessing data, the cache hit rate determination device determines the cache hit rate of the accessed data based on the first total number of requests and the sampled hit count. In some embodiments, the cache hit rate determination device may determine the cache hit rate of the accessed data as the ratio between the sampled hit count and the first total number of requests.

[0044] In other embodiments, the cache hit rate determination device can obtain the total number of samplings of requests for accessing data with a preset sampling probability within a second preset time period; determine the initial hit rate based on the total number of samplings, the number of sample hits, and the preset sampling probability; and adjust the initial hit rate based on the first total number of requests to obtain the cache hit rate of the accessed data.

[0045] The total number of samples refers to the total number of requests that access data through probability sampling. For example, the cache hit rate determination device can increment by 1 for each data access request sampled to obtain the final total number of samples.

[0046] After obtaining the total number of samples and the number of sample hits, the cache hit rate determination device can first perform a weighted amplification process on the total number of samples according to a preset sampling probability to obtain the sampling coverage; then, it will determine the initial hit rate based on the number of sample hits and the sampling coverage. For example, the ratio between the total number of samples and the preset sampling probability can be determined as the sampling coverage. The ratio between the number of sample hits and the sampling coverage is then determined as the initial hit rate. In other embodiments, the ratio between the number of sample hits and the total number of samples can be calculated first; then, it can be weighted and amplified using a preset sampling probability comparison value to obtain the initial hit rate. In some embodiments, the cache hit rate determination device can determine the initial hit rate as the cache hit rate of the accessed data.

[0047] In other embodiments, after obtaining the initial hit rate, it can be adjusted based on the first total number of requests to obtain the cache hit rate for accessed data. For example, the product of the first total number of requests and the initial hit rate can be used as the cache hit rate. As an example, if the first total number of requests is 100,000 as estimated by the HLL algorithm, the total number of samples is 8,000, the number of hits is 200, and the preset sampling probability is 0.01, then the cache hit rate is calculated as follows: Cache hit rate = Total number of first requests × (Number of sampled hits / (Total number of samples / Preset sampling probability)) = 100000 × (200 / (8000 / 0.01)) = 25%.

[0048] As an example, please refer to Figure 3 , Figure 3 This is a schematic diagram of an exemplary embodiment of the second statistical method shown in this application. The cache hit rate determination device can perform cardinality estimation using the HLL algorithm to obtain the first total number of requests, perform distributed sampling using the Theta Sketch algorithm to obtain the total number of samples and the number of sample hits, and then input the first total number of requests output by the HLL algorithm, the total number of samples output by the Theta Sketch algorithm, the number of sample hits, and the preset sampling probability into a weighted fusion processor for weighted fusion processing to obtain the cache hit rate of low-frequency access data.

[0049] It should be noted that the probability counting estimation algorithm used in this embodiment to obtain the first total number of requests and the number of sample hits can significantly reduce resource consumption compared to traditional estimation algorithms. Specifically, in the traditional method: assuming there are 10 billion requestIDs, and each data is stored using 8 bytes, the storage space for 10 billion data is 80 billion bytes, approximately 74.5GB. In practical scenarios, to remove duplicates and perform statistics, a HashSet can be used to store unique IDs. However, because a HashSet needs to store pointers, hash tables, and other metadata, its memory overhead is approximately 5-10 times that of the data, so the storage space is approximately 400GB.

[0050] This embodiment employs a probability cardinality estimation algorithm, such as the HyperLogLog (HLL) algorithm. The HLL algorithm is a fast deduplication counting algorithm, and its memory usage mainly depends on the number of buckets. The memory calculation formula is as follows: Memory ≈ m × log2(log2(N)) bits Where m represents the number of buckets (usually taken as 2). b For example, if b=14, then m=16384 buckets), N represents the upper limit of the possible base (e.g., 10 billion).

[0051] If each bucket uses 6 bits, then the total memory = 16384 buckets × 6 bits = 98,304 bits, which is converted to bytes (1 byte = 8 bits): 98,304 bits ÷ 8 = 12,288 bytes ≈ 12KB.

[0052] Theta Sketch sampling method is used to obtain the sampling hit count. Assuming a preset sampling probability of 1%, only 1% of the data (100 million out of 10 billion data entries) is stored. A more compact storage structure can be used; for example, instead of storing the original ID, hash values ​​can be stored. The original ID requires 8 bytes, while the hash value is typically a 4-byte int or uint32_t. The hash value itself also contains linked list pointers, so each data entry is approximately 12 bytes. For 100 million data entries, the total memory is the product of 100 million and 12 bytes, approximately 1.2GB. In practical engineering, Theta Sketch can be divided into two layers, such as a Bloom filter and exact storage, to further reduce collisions. A buffer can be reserved to prevent data accumulation due to hash collisions, allocating 2-3 times more space. Space can also be reserved for other metadata such as sampling rate markers and timestamps. Therefore, three times 1.2GB can be used as the final memory space, approximately 4GB.

[0053] Therefore, the traditional solution requires 400GB of space to store all data. This embodiment includes 12KB of space for HLL and 4GB for Theta Sketch; the 12KB is negligible. The saving ratio is approximately (400-4) / 400 = 99%.

[0054] Based on the above embodiments, the embodiments of this application adopt... Figure 4 The flowchart illustrates in detail how dynamic memory management is performed on accessed data. Please refer to [link / reference]. Figure 4 , Figure 4 yes Figure 1 The illustrated flowchart shows an exemplary embodiment of the cache hit rate determination method after step S130. Specifically, after step S130, the method further includes the following steps: S410: Store the access data, which is characterized by the current access frequency as high-frequency access data, into the high-frequency access database, and obtain the entropy value of each access data in the high-frequency access database.

[0055] The cache hit rate determination device may also include a memory management module for managing the device's memory. The device memory contains a high-frequency access database to store frequently accessed data and related information, such as the number of requests and timestamps. The cache hit rate determination device obtains the current access frequency of the accessed data and stores the high-frequency access data in the high-frequency access database. The device memory may also contain a low-frequency access database to store low-frequency access data and related information.

[0056] Entropy is used to quantify the dispersion of access frequency for frequently accessed data in a high-frequency access database. A high entropy value indicates that the access frequency of each frequently accessed data point is evenly distributed, meaning there are no significant hotspots. A low entropy value indicates that the access frequency of each frequently accessed data point is relatively concentrated, meaning that the traffic of a few frequently accessed data points is highly concentrated. For example, the formula for calculating the entropy value of a high-frequency access database is as follows:

[0057] Where E represents the entropy value, Indicates the first The proportion of requests for frequently accessed data to the total number of requests for frequently accessed databases. Used to measure the amount of information contained in a single frequently accessed data point.

[0058] The cache hit rate determination device can call the entropy model at preset time intervals to calculate the entropy value of frequently accessed databases. The preset time interval can be set according to actual needs, for example, it can be any value between 3 and 10 seconds. Hardware acceleration of entropy calculation can also be implemented based on an FPGA chip, ensuring a throughput of 100,000 keys / second.

[0059] S420: In response to the entropy value being less than the preset entropy value, the access data in the high-frequency access database is filtered out to obtain the high-frequency access database after filtering.

[0060] When the calculated entropy value in the high-frequency access database is less than the preset entropy value, it indicates that the request frequency of each high-frequency access data in the high-frequency access database is too concentrated, and the traffic is highly concentrated on a few high-frequency access data. The preset entropy value can be set according to the actual application scenario; for example, any value between 0.2 and 0.4 can be selected as the preset entropy value. When the entropy value in the high-frequency access database is greater than or equal to the preset entropy value, there is no need to filter the access data in the high-frequency access database.

[0061] Furthermore, when the entropy value of the high-frequency access database is determined to be less than a preset entropy value, the cache hit rate determination device can filter out high-frequency access data with fewer than a preset threshold number of requests from the high-frequency access database, and retain high-frequency access data with more than or equal to the preset threshold number of requests, thus obtaining a filtered high-frequency access database. For example, high-frequency access data with fewer than the preset threshold number of requests can be transferred to a low-frequency access database.

[0062] In other embodiments, when the number of high-frequency access data in the high-frequency access database is greater than a preset threshold, the cache hit rate determination device sorts the access data in the high-frequency access database from high to low according to the current access frequency of the access data to obtain sorted access data. The high-frequency access database is used to store access data whose current access frequency is characterized as high-frequency access data. Access data is then filtered out from the end of the sorted access data according to a preset ratio to obtain a filtered high-frequency access database.

[0063] When the number of frequently accessed data in the high-frequency access database exceeds a preset threshold, it indicates that the memory occupied by the high-frequency access database has reached the memory allocation threshold. At this point, the high-frequency access database needs to be cleaned up to free up space. For example, the cache hit rate determination device can filter out access data with lower current access frequency, thereby achieving space release. Specifically, the access data can be sorted from high to low according to its current access frequency, and then the access data can be filtered out starting from the end until the number of frequently accessed data in the high-frequency access database is less than or equal to the preset threshold. In other embodiments, the cache hit rate determination device can also select access data from the end of the sorted access data according to a preset ratio and filter this access data out of the high-frequency access database. For example, this access data can be transferred from the high-frequency access database to the low-frequency access database. The preset ratio can be 20%. A preset ratio of access data at the end can be filtered out using an LRU strategy.

[0064] The data transfer process further includes data degradation and statistical degradation: data degradation can involve converting the accessed data to compressed storage, such as Snappy compression, or degrading the accessed data to a probabilistic structure, such as a Bloom filter; statistical degradation includes stopping real-time counting of accessed data and instead using HLL+Theta Sketch for probabilistic sampling. If the accessed data is subsequently requested again, a mechanism can be triggered to migrate the low-frequency access database back to the high-frequency access database.

[0065] In other embodiments, the cache hit rate determination device can determine whether it is necessary to migrate the high-frequency access data in the high-frequency access database to the low-frequency access database by performing migration judgment on the high-frequency access database by the entropy value and by performing migration judgment on the quantity of high-frequency access data in the high-frequency access database.

[0066] To elaborate on the cache hit rate determination method of this application, Figure 5 The flowchart shown below provides further explanation, as detailed below: In response to receiving a cache hit rate determination instruction, the system retrieves access data from the instruction; and identifies high-frequency access data in real time using the Count-Min Sketch algorithm and standard deviation mutation detection. When the accessed data is frequently accessed, precise real-time statistics can be used. For example, a sliding window circular buffer can be used to achieve millisecond-level real-time statistics to obtain the cache hit rate. The sliding window circular buffer supports lock-free writing, and the database can be Redis TimeSeries. When the accessed data is infrequently accessed, probability sampling statistics can be used. For example, HyperLogLog + Theta Sketch can be used for combined sampling to obtain the cache hit rate, and the database can be Apache DataSketches. Alternatively, a hierarchical page table structure can be used, such as 4KB base pages + 2MB large pages, to allocate memory for high-frequency and low-frequency access databases, which can reduce TLB misses. The cache hit rate determination device calls the entropy model to calculate the entropy value of the high-frequency access database every preset time interval, and performs data migration when the entropy value is less than the preset entropy value; or it can detect in real time whether the memory of the high-frequency access database has reached the memory allocation threshold, and if so, filter out the access data of the tail preset proportion according to the LRU strategy.

[0067] Please see Figure 6 , Figure 6 This is a schematic diagram of an exemplary embodiment of the cache hit rate determination device shown in this application. The cache hit rate determination device 600 includes an acquisition module 610, a determination module 620, and a statistics module 630. The acquisition module 610 is used to acquire access data according to the cache hit rate determination instruction received. The determination module 620 is used to determine the target hit rate statistical method of the access data according to the current access frequency of the access data. The statistics module 630 is used to calculate the hit rate of the access data according to the target hit rate statistical method of the access data to obtain the cache hit rate of the access data.

[0068] In the above scheme, the cache hit rate determination device responds to a received cache hit rate determination instruction by obtaining the accessed data according to the instruction; determining the target hit rate statistical method for the accessed data based on the current access frequency; and calculating the cache hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data. Thus, by using the current access frequency of the accessed data, a target hit rate statistical method more suitable for the accessed data can be obtained, avoiding unnecessary resource consumption.

[0069] The functions of each module can be found in the implementation example of the cache hit rate determination method, and will not be repeated here.

[0070] To implement the cache hit rate determination method of the above embodiments, this application proposes another electronic device, please refer to [link to details]. Figure 7 , Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application.

[0071] Electronic device 700 includes memory 710 and processor 720, wherein memory 710 and processor 720 are coupled together.

[0072] The memory 710 is used to store program data, and the processor 720 is used to execute the program data to implement the cache hit rate determination method of the above embodiment.

[0073] In this embodiment, processor 720 can also be referred to as CPU (Central Processing Unit). Processor 720 may be an integrated circuit chip with signal processing capabilities. Processor 720 can also be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The general-purpose processor can be a microprocessor, or processor 720 can be any conventional processor.

[0074] This application also provides a computer-readable storage medium, such as Figure 8 As shown, the computer-readable storage medium 800 is used to store program data 810, which, when executed by the processor, is used to implement the cache hit rate determination method as described in the method embodiment of this application.

[0075] The methods involved in the cache hit rate determination method embodiments of this application, when implemented as software functional units and sold or used as independent products, can be stored in a device, such as a computer-readable storage medium. Based on this understanding, the technical solution of this application, essentially, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0076] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for determining cache hit rate, characterized in that, The cache hit rate determination method includes: In response to receiving a cache hit rate determination instruction, the access data is obtained according to the cache hit rate determination instruction; The target hit rate statistical method for the access data is determined based on the current access frequency of the access data. The cache hit rate of the accessed data is obtained by calculating the hit rate of the accessed data using the target hit rate statistical method. The step of determining the target hit rate statistical method of the access data based on the current access frequency of the access data includes: In response to the fact that the current access frequency of the access data indicates that the access data is high-frequency access data, the first statistical method is determined as the target hit rate statistical method for the access data; If the current access frequency of the access data indicates that the access data is low-frequency access data, then the second statistical method is determined as the target hit rate statistical method for the access data.

2. The cache hit rate determination method according to claim 1, characterized in that, The step of calculating the cache hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data includes: In response to the target hit rate statistics method being the first statistics method, the number of hits and the number of misses of the access data within a first preset time period are obtained, wherein the hit indicates that the access data is successfully retrieved from the cache; The cache hit rate of the accessed data is determined based on the number of hits and the number of misses.

3. The cache hit rate determination method according to claim 1, characterized in that, The step of calculating the cache hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data includes: If the target hit rate statistics method is the second statistics method, then the first total number of requests within the second preset time period is obtained; Within the second preset time period, the requests for accessing the data are sampled with a preset sampling probability to obtain the number of sampling hits. The cache hit rate of the accessed data is determined based on the first total number of requests and the number of sampled hits.

4. The cache hit rate determination method according to claim 3, characterized in that, The step of determining the cache hit rate of the accessed data based on the first total number of requests and the number of sampled hits includes: Obtain the total number of samplings performed on requests for accessing the data with the preset sampling probability within the second preset time period; The initial hit rate is determined based on the total number of samples, the number of successful samples, and the preset sampling probability. The initial hit rate is adjusted based on the first total number of requests to obtain the cache hit rate of the accessed data.

5. The cache hit rate determination method according to claim 1, characterized in that, Before the step of determining the target hit rate statistical method of the access data based on the current access frequency of the access data, the method further includes: The second total number of requests to obtain the access data; The standard deviation of the number of requests for the accessed data within the third preset time period is calculated to obtain the standard deviation value within the third preset time period. The current access frequency of the accessed data is determined based on the second total number of requests and the standard deviation.

6. The cache hit rate determination method according to claim 1, characterized in that, After the step of calculating the hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data, the method further includes: The access data, which represents the current access frequency as high-frequency access data, is stored in the high-frequency access database, and the entropy value of each access data in the high-frequency access database is obtained. If the entropy value is less than a preset entropy value, the access data in the high-frequency access database is filtered out to obtain a filtered high-frequency access database.

7. The cache hit rate determination method according to claim 1, characterized in that, After the step of calculating the hit rate of the accessed data using the target hit rate statistical method to obtain the cache hit rate of the accessed data, the method further includes: If the number of high-frequency access data in the high-frequency access database exceeds a preset threshold, the access data in the high-frequency access database is sorted from high to low according to the current access frequency of the access data to obtain sorted access data. The high-frequency access database is used to store access data whose current access frequency is characterized as high-frequency access data. According to a preset ratio, the access data is filtered out starting from the end of the sorted access data to obtain the high-frequency access database after filtering.

8. An electronic device, characterized in that, include: A memory and a processor, wherein the memory stores program instructions, and the processor retrieves the program instructions from the memory to perform the method as claimed in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, include: The system stores program data, which, when executed by a processor, is used to implement the method as described in any one of claims 1-7.

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