An interface conversion device and method

Abstract

This application provides an interface conversion device and method, relating to the field of interface conversion technology. The device includes an FPGA chip, an SDIO interface, and a D-PHY interface. The FPGA chip includes an SDIO protocol receiving module, a data processing module, and a D-PHY protocol transmitting module. The SDIO protocol receiving module receives and parses SDIO protocol data transmitted by the SDIO interface to obtain valid SDIO protocol data, which is then sent to the data processing module. The data processing module buffers and synchronizes the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface. The D-PHY protocol transmitting module encodes and encapsulates the processed data according to the D-PHY protocol to obtain D-PHY protocol data, which is then sent to the D-PHY interface. This device improves the transmission performance of SDIO to D-PHY interface conversion and reduces cost and size.

Description

Technical Field

[0001] This application relates to the field of interface conversion technology, and more specifically, to an interface conversion device and method. Background Technology

[0002] With the increasing demand for high-speed data transmission, the conversion from SDIO (Secure Digital Input Output) interfaces to D-PHY interfaces faces multiple challenges in terms of performance, flexibility, cost, and size. Currently, the industry mainly adopts the following two solutions: (1) Dedicated chip solution: Protocol conversion is achieved through ASIC (Application-Specific Integrated Circuit). This solution has high integration and good stability, but its development cost is high, the cycle is long, and the flexibility is poor (the function of the chip cannot be modified after tape-out). It is difficult to adapt to different versions of SDIO or D-PHY protocols, and it is difficult to customize development for some special application requirements.

[0003] (2) General-purpose processor combined with software solution: This solution uses a general-purpose processor in conjunction with software to parse the protocol stack for conversion. While it offers high flexibility, it is limited by processor performance due to its reliance on software to process the protocol, making it prone to introducing data transmission delays and unable to meet the requirements of high real-time scenarios. In addition, this solution typically requires more than three peripheral chips, resulting in a significant increase in system cost, size, and power consumption.

[0004] In summary, overcoming the shortcomings of existing SDIO interface to D-PHY interface conversion schemes is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide an interface conversion device and method to overcome the defects of existing SDIO interface to D-PHY interface conversion schemes.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows: On one hand, this application provides an interface conversion device, including: an FPGA chip, an SDIO interface, and a D-PHY interface; the FPGA chip includes: an SDIO protocol receiving module, a data processing module, and a D-PHY protocol transmitting module; The SDIO interface, SDIO protocol receiving module, data processing module, D-PHY protocol sending module, and D-PHY interface are connected in sequence. The SDIO protocol receiving module is used to receive and parse the SDIO protocol data sent by the SDIO interface, obtain valid SDIO protocol data, and send it to the data processing module; The data processing module is used to buffer and synchronize the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, and obtain the processed data. The D-PHY protocol sending module is used to encode and encapsulate the processed data according to the D-PHY protocol to obtain D-PHY protocol data and send it to the D-PHY interface.

[0007] Furthermore, the SDIO protocol data includes SDIO command frames and SDIO data frames; the SDIO protocol receiving module includes: a command parsing unit, a data extraction unit, and a data verification unit; the command parsing unit and the data extraction unit are both connected to the SDIO interface, the command parsing unit is also connected to the data extraction unit and the data verification unit respectively, the data extraction unit is also connected to the data verification unit, and the data verification unit is also connected to the data processing module; The command parsing unit is used to parse SDIO command frames through a hardware state machine to extract key control information and send it to the data extraction unit and the data verification unit. The data extraction unit is used to extract valid SDIO protocol data from the SDIO data frame based on the key control information and send it to the data verification unit. The data verification unit is used to perform cyclic redundancy check (CRUD) of SDIO command frames and SDIO data frames through hardware. When the verification fails, the data verification unit automatically triggers a retransmission request mechanism to re-receive and verify the erroneous SDIO data frame until the verification is successful or the number of retransmission requests reaches a set value. When the verification is successful, the data verification unit sends the valid SDIO protocol data to the data processing module.

[0008] Furthermore, the data processing module includes: a cache control unit and a cache synchronization unit; The cache synchronization unit is connected to both the SDIO protocol receiving module and the D-PHY protocol sending module; the cache control unit is connected to both the cache synchronization unit and the SDIO protocol receiving module. The cache control unit is used to monitor the cache occupancy rate of the asynchronous first-in-first-out cache in the cache synchronization unit in real time, and send a pause reception signal or a resume reception signal to the SDIO protocol receiving module according to the cache occupancy rate; The cache synchronization unit is used to buffer and synchronize the valid SDIO protocol data, and eliminates the rate and clock domain differences between the SDIO interface and the D-PHY interface through the asynchronous first-in-first-out buffer.

[0009] Furthermore, the D-PHY protocol transmission module includes: a low-speed signal unit, a high-speed signal unit, and a physical layer unit; Both the low-speed signal unit and the high-speed signal unit are connected to the data processing module, and both the low-speed signal unit and the high-speed signal unit are also connected to the physical layer unit, which is also connected to the D-PHY interface. The low-speed signal unit is used to receive low-speed data from the data processing module, construct a low-speed request signal and send it to the physical layer unit; when a response is received from the physical layer unit, low-speed data is sent to the physical layer unit until all low-speed data is sent. The high-speed signal unit is used to receive high-speed data from the data processing module, construct a high-speed request signal and send it to the physical layer unit; when a response is received from the physical layer unit, high-speed data is sent to the physical layer unit until all high-speed data is sent. The physical layer unit is used to convert the data sent by the low-speed signal unit and / or the high-speed signal unit into D-PHY protocol data conforming to the MIPI D-PHY specification, and send it to the D-PHY interface.

[0010] Furthermore, the FPGA chip also includes: a configuration control module; The configuration control module is connected to the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The configuration control module is used to receive configuration instructions sent by the host computer through an external interface, and dynamically adjust the parameters of the SDIO protocol receiving module, the data processing module and the D-PHY protocol sending module according to the configuration instructions.

[0011] Furthermore, the configuration control module includes: a serial port transceiver unit and a parameter configuration unit; The parameter configuration unit is connected to the serial port transceiver unit, the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The serial port transceiver unit is used to receive the configuration command sent by the host computer through the external interface, and send the configuration command to the parameter configuration unit; The parameter configuration unit is used to parse the received configuration instructions and update the parameters of the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module according to the parsed configuration instructions.

[0012] Furthermore, the configuration control module also includes: a status monitoring unit; The status monitoring unit is connected to the serial port transceiver unit, the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The status monitoring unit is used to collect the operating status data of the SDIO protocol receiving module, the data processing module and the D-PHY protocol sending module in real time, and send the operating status data of each module to the serial port transceiver unit. The serial transceiver unit is also used to convert the operating status data of each module into serial signals and send them to the host computer through the external interface.

[0013] Furthermore, the number of both the SDIO interface and the D-PHY interface is n; where n≥1; All n SDIO interfaces and n D-PHY interfaces are connected to the FPGA chip; The FPGA chip is used to simultaneously perform protocol conversion on the data sent by the n SDIO interfaces, and output the converted data to the corresponding D-PHY interface.

[0014] Furthermore, the interface conversion device also includes: a clock circuit and a power management circuit; The clock circuit is connected to the FPGA chip and is used to provide a reference clock; The power management circuit is connected to the FPGA chip, the SDIO interface and the D-PHY interface respectively, and is used to supply power to the FPGA chip, the SDIO interface and the D-PHY interface.

[0015] On the other hand, this application also provides an interface conversion method, applied to the interface conversion apparatus as described in any of the foregoing embodiments, the method comprising: The SDIO protocol receiving module receives and parses the SDIO protocol data sent by the SDIO interface, obtains valid SDIO protocol data, and sends it to the data processing module; The data processing module buffers and synchronizes the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, thereby obtaining the processed data. The D-PHY protocol sending module encodes and encapsulates the processed data according to the D-PHY protocol to obtain D-PHY protocol data and sends it to the D-PHY interface.

[0016] Compared with the prior art, this application has the following advantages: The interface conversion device provided in this application includes an FPGA chip, an SDIO interface, and a D-PHY interface. The FPGA chip includes an SDIO protocol receiving module, a data processing module, and a D-PHY protocol transmitting module. The SDIO interface, SDIO protocol receiving module, data processing module, D-PHY protocol transmitting module, and D-PHY interface are connected sequentially. The SDIO protocol receiving module receives and parses the SDIO protocol data transmitted by the SDIO interface to obtain valid SDIO protocol data, which is then sent to the data processing module. The data processing module buffers and synchronizes the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, obtaining processed data. The D-PHY protocol transmitting module encodes and encapsulates the processed data according to the D-PHY protocol to obtain D-PHY protocol data, which is then sent to the D-PHY interface.

[0017] In terms of flexibility: The programmable nature of FPGAs allows for flexible protocol configuration without modifying the hardware circuitry. When adapting to new SDIO or D-PHY protocol versions, functional upgrades can be achieved simply by programming the FPGA's bitstream file, without redesigning the hardware or performing chip fabrication, thus improving flexibility and scalability. In terms of transmission performance: The FPGA-based all-hardware parallel processing architecture fundamentally eliminates the additional latency caused by software parsing. Both SDIO protocol reception and D-PHY protocol transmission are implemented through FPGA hardware logic, greatly reducing data processing latency and eliminating data packet loss under full load, thereby improving transmission performance. In terms of cost and size: A single FPGA integrates all functions, eliminating the need for external processors and D-PHY chips, reducing hardware costs and PCB area, making it suitable for consumer electronics, industrial control, and other scenarios with high requirements for miniaturization and low cost. In terms of reliability: FPGA hardware logic has superior stability compared to software parsing, with no risk of software crashes during long-term operation, resulting in higher reliability. Attached Figure Description

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] Figure 1 This is one of the structural schematic diagrams of an interface conversion device provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the structure of an interface conversion device provided in an embodiment of this application; Figure 3 This is the third schematic diagram of an interface conversion device provided in an embodiment of this application; Figure 4 This is the fourth schematic diagram of an interface conversion device provided in an embodiment of this application; Figure 5 A flowchart illustrating the operation of an interface conversion device provided in this application embodiment; Figure 6 This is a flowchart illustrating an interface conversion method provided in an embodiment of this application.

[0020] Icons: 10 - Interface conversion device; 100 - SDIO interface; 200 - FPGA chip; 210 - SDIO protocol receiving module; 211 - Command parsing unit; 212 - Data extraction unit; 213 - Data verification unit; 220 - Data processing module; 221 - Buffer control unit; 222 - Buffer synchronization unit; 230 - D-PHY protocol sending module; 231 - Low-speed signal unit; 232 - High-speed signal unit; 233 - Physical layer unit; 240 - Configuration control module; 241 - Serial port transceiver unit; 242 - Parameter configuration unit; 243 - Status monitoring unit; 300 - D-PHY interface. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0023] To better understand, the key terms mentioned in this application will be explained below.

[0024] SDIO (Secure Digital Input Output): A secure digital input / output interface, a general-purpose interface protocol based on the SD card standard extension. It was initially used for SD card storage and later extended to wireless communication (WiFi, Bluetooth), sensors, and other devices. It supports command transmission (such as device initialization and data requests) and data reading and writing. It is divided into versions such as SDIO 1.0, 2.0, and 3.0, with the speed increasing with each version upgrade.

[0025] D-PHY: The full name is MIPI D-PHY (Mobile Industry Processor Interface D-PHY), a high-speed serial interface protocol developed by the MIPI Alliance. It is mainly used for image and video transmission in consumer electronics and automotive electronics (such as displays and cameras). It uses differential signal transmission and supports multi-lane (channel) parallel transmission to improve bandwidth.

[0026] Interface standards are a series of specifications and protocols designed to ensure normal communication and data transmission between different devices. They include provisions regarding electrical characteristics, signal formats, and communication timing.

[0027] ASIC (Application-Specific Integrated Circuit): A non-reconfigurable chip designed for a specific function.

[0028] FPGA (Field-Programmable Gate Array): A type of programmable integrated circuit that allows users to configure its internal logic circuitry through programming to achieve specific functions. Unlike traditional fixed-function integrated circuits, FPGAs offer advantages such as high flexibility and short development cycles, and can be customized to meet different application requirements.

[0029] As described in the background section, there are currently two main approaches to converting SDIO interfaces to D-PHY interfaces: dedicated ASIC solutions and general-purpose processor-based software solutions. However, both face multi-dimensional technical bottlenecks and limitations. On the one hand, ASIC solutions dominate the consumer electronics mass production market due to their high integration and stability. However, their hardware logic is fixed, supporting only specific protocol versions and unable to adapt to rapidly iterating protocol standards. Furthermore, the development cycle from requirement definition to chip mass production can take more than a year, resulting in high development costs and a long development period. On the other hand, while software solutions using general-purpose processors in conjunction with peripheral chips offer some flexibility, they typically require multiple peripheral chips, leading to high system size and power consumption. Moreover, the latency introduced by software parsing often exceeds 100 milliseconds, failing to meet the needs of some application scenarios with high real-time requirements.

[0030] Meanwhile, industry applications are evolving towards diversification and higher performance: consumer electronics continue to pursue miniaturization and low power consumption; automotive electronics, on the other hand, are placing stringent demands on high reliability and low latency. Existing solutions are struggling to simultaneously meet these ever-evolving industry requirements.

[0031] In view of this, this application provides an FPGA-based interface conversion device to address the problems of insufficient flexibility, performance bottlenecks, and excessive cost and size in existing SDIO interface to D-PHY interface conversion schemes. This interface conversion device is particularly suitable for consumer electronics, industrial control, and automotive electronics scenarios, overcoming the trade-off between customization and flexibility in existing solutions, optimizing data transmission performance, reducing system cost and physical size, and enabling high-speed data interaction between SDIO protocol devices and D-PHY protocol devices.

[0032] Specifically, please refer to Figure 1 The interface conversion device 10 provided in this application embodiment includes: an FPGA chip 200, an SDIO interface 100, and a D-PHY interface 300. Both the SDIO interface 100 and the D-PHY interface 300 are connected to the FPGA chip 200.

[0033] The FPGA chip 200 includes an SDIO protocol receiving module 210, a data processing module 220, and a D-PHY protocol transmitting module 230. The SDIO interface 100, SDIO protocol receiving module 210, data processing module 220, D-PHY protocol transmitting module 230, and D-PHY interface 300 are connected sequentially.

[0034] The SDIO interface 100 is used to connect to SDIO devices (such as system-on-a-chip SOC).

[0035] The SDIO protocol receiving module 210 is used to receive and parse the SDIO protocol data sent by the SDIO interface 100, obtain valid SDIO protocol data, and send it to the data processing module 220.

[0036] The data processing module 220 is used to buffer and synchronize valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface 100 and the D-PHY interface 300, and obtain the processed data.

[0037] The D-PHY protocol sending module 230 is used to encode and encapsulate the processed data according to the D-PHY protocol, obtain D-PHY protocol data, and send it to the D-PHY interface 300.

[0038] The D-PHY interface 300 is used to connect D-PHY devices (such as displays).

[0039] Therefore, compared with existing ASIC solutions and general-purpose processor solutions, the FPGA-based interface conversion device 10 provided in this application has the following significant advantages: (1) High flexibility and scalability: The programmable nature of FPGAs allows for flexible protocol configuration without modifying the hardware circuitry. When it is necessary to adapt to a new SDIO or D-PHY protocol version, the function upgrade can be achieved simply by burning the bitstream file of the FPGA, without redesigning the hardware or tape-out. This solution can significantly shorten the protocol adaptation cycle from several months in traditional ASIC solutions to several hours, thereby effectively meeting the market demand for rapid technology iteration.

[0040] (2) Significantly improved transmission performance: The FPGA-based all-hardware parallel processing architecture can fundamentally eliminate the additional latency caused by software parsing. Both SDIO protocol reception and D-PHY protocol transmission are implemented through FPGA hardware logic, with data processing latency of less than 100us and no data packet loss under full load. Compared with general processor solutions (latency is usually higher than 100ms and packet loss rate is >5% under full load), the performance is improved by more than 10 times.

[0041] (3) Significant cost and size advantages: A single FPGA integrates all functions, eliminating the need for external processors and D-PHY chips, reducing hardware costs by more than 40% (saving tape-out costs compared to ASIC solutions, and saving external chip costs compared to general-purpose processor solutions combined with peripheral chips), and reducing PCB area to 1 / 2 of traditional solutions (e.g., from 200mm² to 100mm²), making it suitable for consumer electronics, industrial control, and other scenarios with high requirements for miniaturization and low cost.

[0042] (4) Higher reliability: FPGA hardware logic stability is better than software analysis, and there is no risk of software crash during long-term operation.

[0043] Furthermore, industrial scenarios commonly face compatibility challenges arising from the coexistence of devices with multiple protocols. Existing conversion solutions, due to limitations in fixed functionality, often only support specific rates or partial protocol versions, making it difficult to adapt to the mixed protocol communication needs in complex industrial environments.

[0044] To further improve the compatibility and flexibility of interface conversion, please refer to [link / reference]. Figure 2 In an alternative implementation, the FPGA chip 200 further includes a configuration control module 240.

[0045] The configuration control module 240 is connected to the SDIO protocol receiving module 210, the data processing module 220, and the D-PHY protocol sending module 230, respectively.

[0046] The configuration control module 240 is used to receive configuration instructions sent by the host computer through an external interface (such as a UART interface), and dynamically adjust the parameters (such as SDIO rate, number of D-PHY channels, buffer depth, etc.) of the SDIO protocol receiving module 210, data processing module 220 and D-PHY protocol sending module 230 according to the configuration instructions, so as to achieve flexible adaptation to multiple protocol versions.

[0047] For example, using general UART serial port software, users can send specific configuration commands through the software interface. These configuration commands are transmitted to the configuration control module 240 inside the FPGA chip 200 via the UART interface, thereby realizing the real-time updating and dynamic configuration of the parameters of each functional module inside the FPGA chip 200, further improving the flexibility and compatibility of protocol adaptation.

[0048] Therefore, by integrating the configuration control module 240 into the FPGA chip 200, comprehensive compatibility with multiple protocol versions and various types of devices is achieved. This configuration control module 240 supports dynamic configuration of key parameters including SDIO clock frequency (100kHz-200MHz), number of D-PHY channels (1-4 lanes), and data bit width (8 / 16 bits), thus enabling it to adapt to SDIO devices (such as various SOCs, WiFi modules, and Bluetooth modules) and D-PHY receiving terminals (such as smartphone displays, industrial cameras, and automotive display systems), covering all scenarios from low-speed control to high-speed data transmission.

[0049] Further, please refer to Figure 3 In one optional implementation, the configuration control module 240 includes a serial port transceiver unit 241 and a parameter configuration unit 242.

[0050] The parameter configuration unit 242 is connected to the serial port transceiver unit 241, the SDIO protocol receiving module 210, the data processing module 220, and the D-PHY protocol sending module 230, respectively.

[0051] The serial transceiver unit 241 is used to receive configuration commands sent by the host computer through an external interface and send the configuration commands to the parameter configuration unit 242.

[0052] The parameter configuration unit 242 is used to parse the received configuration instructions and update the parameters of the SDIO protocol receiving module 210, the data processing module 220 and the D-PHY protocol sending module 230 according to the parsed configuration instructions.

[0053] In another optional implementation, the configuration control module 240 further includes a status monitoring unit 243. The status monitoring unit 243 is connected to the serial transceiver unit 241, the SDIO protocol receiving module 210, the data processing module 220, and the D-PHY protocol sending module 230, respectively.

[0054] The status monitoring unit 243 is used to collect the operating status data (such as SDIO connection status, D-PHY transmission status, buffer occupancy rate, and number of verification errors) of the SDIO protocol receiving module 210, data processing module 220 and D-PHY protocol transmitting module 230 in real time, and send the operating status data of each module to the serial port transceiver unit 241.

[0055] The serial transceiver unit 241 is also used to convert the operating status data of each module into serial port signals and send them to the host computer through an external interface.

[0056] That is, in this embodiment, the serial transceiver unit 241 interacts with the host computer through an external interface, receives configuration commands from the host computer and transmits them to the parameter configuration unit 242, and also receives information reported by the status monitoring unit 243, converts it into serial signals and sends them to the host computer. The status monitoring unit 243 can monitor the operating status of each functional module inside the FPGA chip 200 in real time. Users can view the operating logs through the host computer, reducing fault location time to minutes, greatly improving maintenance efficiency, reliability, and maintainability.

[0057] Based on the above design, this application uses FPGA chip 200 as the core processing unit. By integrating SDIO protocol receiving module 210, data processing module 220, D-PHY protocol transmitting module 230, and configuration control module 240 within FPGA chip 200, and in conjunction with external interface circuits (i.e., SDIO interface 100 and D-PHY interface 300), a full hardware conversion from SDIO interface to D-PHY interface is achieved, specifically solving the following key requirements: (1) It solves the contradiction between customization and flexibility: existing ASIC solutions cannot quickly adapt to the requirements of protocol version upgrades or rate adjustment. This application needs to be based on the programmable characteristics of FPGA to realize flexible configuration of protocol parameters, and can be compatible with different versions of SDIO (1.0-3.0) and D-PHY (1.1-2.0) protocols without hardware reconstruction.

[0058] (2) Solved the “compatibility shortcoming”: Existing solutions only support some rates or protocol versions. This application integrates a configuration control module 240 inside the FPGA chip 200, and adapts different types of SDIO devices (such as SD cards, WiFi modules) and D-PHY receivers (such as displays, image sensors) through parameter configuration (such as SDIO clock frequency, number of D-PHY channels, data bit width).

[0059] (3) Breakthrough of “performance bottleneck”: Existing general-purpose processor solutions suffer from data delay and packet loss due to software parsing. This application achieves full hardware acceleration of SDIO protocol reception and D-PHY protocol transmission through the hardware parallel processing capability of FPGA chip 200, eliminating the delay caused by software intervention and eliminating data packet loss.

[0060] (4) Reduced “cost and size”: Existing solutions require additional processors and peripheral chips. This application integrates all functions based on a single FPGA chip 200, without the need for other external chips, greatly reducing the hardware size (which can be reduced to 1 / 2 of the traditional solution), while reducing R&D costs (no ASIC tape-out required, reducing early R&D costs by more than 80%), and is suitable for small and medium batch and rapid iteration scenarios.

[0061] To better understand the conversion process from SDIO to D-PHY, the following will combine... Figure 4 The SDIO protocol receiving module 210, data processing module 220 and D-PHY protocol transmitting module 230 inside the FPGA chip 200 will be described in turn.

[0062] In one optional implementation, the SDIO protocol data transmitted by the SDIO device through the SDIO interface 100 includes SDIO command frames and SDIO data frames. The SDIO command frames are used for device control and status management, such as sending initialization commands, read / write requests, device parameter configurations (e.g., clock frequency, data bit width), and status queries. The SDIO data frames are used for the transmission of actual data content, such as carrying stored data or network data packets transmitted by the wireless module during read / write operations, supporting single-block or multi-block data transmission.

[0063] like Figure 4 As shown, the SDIO protocol receiving module 210 includes a command parsing unit 211, a data extraction unit 212, and a data verification unit 213. Both the command parsing unit 211 and the data extraction unit 212 are connected to the SDIO interface 100. The command parsing unit 211 is also connected to both the data extraction unit 212 and the data verification unit 213. The data extraction unit 212 is also connected to the data verification unit 213, and the data verification unit 213 is also connected to the data processing module 220.

[0064] The command parsing unit 211 is used to parse SDIO command frames (such as CMD52 and CMD53) through a hardware state machine to extract key control information, and then send the key control information to the data extraction unit 212 and the data verification unit 213. The key control information includes, but is not limited to, command type, address, and data length.

[0065] Optionally, the state machine includes four states: IDLE (idle state), CMD_RECEIVE (command receiving state), CMD_DECODE (command decoding state), and CMD_RESPONSE (command response state).

[0066] Understandably, the command parsing unit 211 interprets the command frames on the SDIO bus through the hardware state machine in the digital circuit design, and extracts key control information such as command type, address, and data length from them. This information will guide subsequent data transmission.

[0067] The data extraction unit 212 is used to extract valid SDIO protocol data from the SDIO data frame based on key control information and send it to the data verification unit 213.

[0068] Understandably, the data extraction unit 212 locates and captures the corresponding data block on the SDIO data line based on the address and data length information provided by the command parsing unit 211, completes data bit alignment and format conversion, and provides raw data input for subsequent data verification and protocol conversion.

[0069] The data verification unit 213 is used to perform cyclic redundancy check (CRUD) of SDIO command frames and SDIO data frames through hardware. When the verification fails, the data verification unit 213 automatically triggers a retransmission request mechanism to re-receive and verify the erroneous SDIO data frame until the verification is successful or the number of retransmission requests reaches a set value. When the verification is successful, the data verification unit 213 sends the valid SDIO protocol data to the data processing module 220.

[0070] Understandably, to ensure the correctness and reliability of data transmission, the data verification unit 213 performs CRC (Cyclic Redundancy Check) verification on both SDIO command frames and SDIO data frames via hardware. For example, CRC7 verification is performed on SDIO command frames, and CRC16 verification is performed on SDIO data frames. CRC is an error detection code; the sender calculates a fixed-bit checksum based on the data content and appends it to the command or data frame. Upon receiving the data, the receiver also performs CRC calculation and compares it with the received checksum. If the two are inconsistent, it indicates that an error occurred during frame transmission.

[0071] When verification fails, the data verification unit 213 sends an error flag and a retransmission request signal to the upstream module (such as the SDIO protocol receiving module 210), triggering the SDIO device to retransmit the corresponding frame for re-reception and verification, until verification succeeds or the number of retransmission requests reaches a set value. This set value can be configured via the configuration control module 240, with a default retransmission request count of 3. When verification succeeds, the data verification unit 213 sends valid SDIO protocol data to the data processing module 220. When the number of retransmission requests reaches the set value, the data verification unit 213 reports an error status, and the system performs subsequent processing according to a preset strategy (such as interrupting transmission or logging).

[0072] Therefore, the SDIO protocol receiving module 210, through the collaborative work of its internal command parsing unit 211, data extraction unit 212, and data verification unit 213, achieves complete hardware-level protocol parsing and error control of the SDIO bus signals. This ensures that the received commands and data meet the protocol requirements in terms of accuracy, integrity, and reliability, preparing for subsequent data processing and protocol conversion. The SDIO protocol receiving module 210 uses hardware methods (such as a state machine) to parse the SDIO protocol (such as CMD52 / CMD53 commands and CRC7 / CRC16 checks), which is the core step in converting SDIO interface 100 data into "processable raw data." This design effectively solves the performance bottleneck problem—by replacing traditional software parsing with hardware parsing, the processing latency is shortened to within two clock cycles; at the same time, it enhances compatibility, flexibly adapting to different versions of the SDIO protocol.

[0073] Further, in an optional embodiment, the data processing module 220 includes a cache control unit 221 and a cache synchronization unit 222. The cache synchronization unit 222 is connected to both the SDIO protocol receiving module 210 and the D-PHY protocol transmitting module 230. The cache control unit 221 is connected to both the cache synchronization unit 222 and the SDIO protocol receiving module 210.

[0074] The cache control unit 221 is used to monitor the cache occupancy rate of the asynchronous first-in-first-out (FIFO) cache in the cache synchronization unit 222 in real time, and send a pause reception signal or a resume reception signal to the SDIO protocol receiving module 210 according to the cache occupancy rate.

[0075] For example, when the cache occupancy rate is detected to exceed the preset maximum threshold (which can be configured to 70% by the configuration control module 240), the cache control unit 221 sends a pause reception signal to the SDIO receiving module; when the cache occupancy rate is detected to be lower than the preset minimum threshold (which can be configured to 50% by the configuration control module 240), the cache control unit 221 sends a resume reception signal to the SDIO receiving module, thereby avoiding cache overflow or data interruption.

[0076] The buffer synchronization unit 222 is used to buffer and synchronize valid SDIO protocol data, and eliminates the rate and clock domain differences between the SDIO interface 100 and the D-PHY interface 300 through an asynchronous first-in-first-out buffer.

[0077] Understandably, the cache synchronization unit 222 uses the internal block RAM of the FPGA chip 200 to construct an asynchronous FIFO buffer with a configurable cache depth (the cache depth ranges from 128 to 8192, dynamically adjusted by the configuration control module 240, and is typically designed to store the capacity of 2 rows of image pixels). The data bit width of this asynchronous FIFO buffer is consistent with that of the SDIO protocol receiving module 210 (8-bit / 16-bit), and it supports full / empty status signal output to avoid data overflow or empty reads. Since the SDIO receiving clock and the D-PHY transmitting clock belong to different clock domains, cross-clock domain data synchronous transmission can be achieved through the asynchronous FIFO buffer.

[0078] Therefore, the data processing module 220, through the coordinated operation of its internal cache control unit 221 and cache synchronization unit 222, achieves adaptive rate matching and reliable cross-clock domain synchronization of the data stream between SDIO and D-PHY. This not only solves the data overflow or interruption problems that may be caused by interface rate mismatch, but also ensures stable data transmission in heterogeneous clock systems, providing continuous, complete, and timing-correct data input for the subsequent D-PHY protocol transmission module 230. The data processing module 220 uses hardware methods (such as an asynchronous FIFO buffer) to eliminate the rate difference and clock domain difference between SDIO (up to 200MHz) and D-PHY (up to 2.5GHz), avoiding data overflow or empty reads, solving the performance bottleneck problem (no data packet loss), and also improving reliability.

[0079] Furthermore, in an optional implementation, the D-PHY protocol transmission module 230 includes: a low-speed signal unit 231, a high-speed signal unit 232, and a physical layer unit 233. Both the low-speed signal unit 231 and the high-speed signal unit 232 are connected to the data processing module 220, and both are also connected to the physical layer unit 233, which in turn is connected to the D-PHY interface 300.

[0080] The low-speed signal unit 231 is used to receive low-speed data from the data processing module 220, construct a low-speed request signal and send it to the physical layer unit 233; when it receives a response from the physical layer unit 233, it sends low-speed data to the physical layer unit 233 until all low-speed data is sent.

[0081] Understandably, the low-speed signal unit 231 reads the low-speed data in the data processing module 220 (i.e., asynchronous FIFO), constructs an LP (Low Power) request signal (i.e., low-speed request signal) and sends it to the physical layer unit 233 for transmission. When a response is received, it starts sending low-speed data until all data transmission is completed.

[0082] The high-speed signal unit 232 is used to receive high-speed data from the data processing module 220, construct a high-speed request signal and send it to the physical layer unit 233; when it receives a response from the physical layer unit 233, it sends high-speed data to the physical layer unit 233 until all high-speed data is sent.

[0083] Understandably, the high-speed signal unit 232 takes high-speed data from the data processing module 220 (i.e., asynchronous FIFO), constructs an HS (High Speed) request signal (i.e., high-speed request signal) and sends it to the physical layer unit 233 for transmission. When a response is received, it starts sending high-speed data until all data transmission is completed.

[0084] Physical layer unit 233 is used to convert the data sent by low-speed signal unit 231 and / or high-speed signal unit 232 into D-PHY protocol data conforming to the MIPI D-PHY specification, and send it to D-PHY interface 300.

[0085] Understandably, the hard-core D-PHY module built into the FPGA chip 200 is used as the physical layer unit 233. Some models of the FPGA chip 200 may contain two D-PHY modules, each containing one clock channel and four data channels, with each channel having a data rate of up to 2.5 Gbps. Optionally, for application scenarios with rates lower than 1.5 Gbps, the soft-core D-PHY of the FPGA chip 200 can also be used as the physical layer unit 233. After the FPGA chip 200 is powered on, it provides the D-PHY core with the clock, reset, and control signals required for operation. The D-PHY module (i.e., physical layer unit 233) continuously receives data from the low-speed signal unit 231 and / or the high-speed signal unit 232, converts it into D-PHY protocol data conforming to the MIPI D-PHY specification, and sends it to the D-PHY interface 300.

[0086] Therefore, the D-PHY protocol transmission module 230, through the coordinated operation of its internal low-speed signal unit 231, high-speed signal unit 232, and physical layer unit 233, achieves full hardware real-time conversion and high-speed output of SDIO data to the MIPI D-PHY protocol format. This module can intelligently identify and process low-speed and high-speed data from the data processing module 220. By constructing corresponding low-speed / high-speed request signals, it calls the hard-core or soft-core D-PHY module (i.e., physical layer unit 233) in the FPGA chip 200 to complete protocol encapsulation and physical layer driving, ultimately outputting a compliant high-speed serial differential signal to the D-PHY interface 300, ensuring low-latency and highly reliable data transmission. In other words, the D-PHY protocol transmission module 230 reads data from the data processing module 220 and completes data encoding, channel mapping, and high-speed serial transmission operations according to the D-PHY protocol requirements. This module implements the D-PHY protocol (high-speed serial transmission) in hardware and is the core component for converting "raw data" into a D-PHY-compatible format. It effectively solves the performance bottleneck problem (supports a transmission rate of up to 2.5Gbps per channel) and also improves system compatibility (it can be adapted to multiple versions of the D-PHY protocol).

[0087] Based on the above design, the following is combined with Figure 5 The internal workflow of the FPGA is explained.

[0088] After the FPGA is powered on, it undergoes initialization operations, including presetting various parameters and initializing each state machine. Optionally, an additional EEPROM chip can be added to store the parameters, ensuring that the parameters are retained even after the FPGA is powered off.

[0089] After the FPGA initialization is completed, the SDIO device connected to the SDIO interface 100 can start SDIO initialization. It interacts by sending various command frames (CMD0, CMD3, CMD5 and CMD7, etc.) to complete device identification, parameter configuration and state switching. Initially, a 400k clock is used, and after negotiation is completed, a 50MHz or higher clock is used to ensure that the communication protocol between the host and the device is consistent.

[0090] After SDIO initialization is complete, it enters an idle state, during which it monitors three transactions: receiving SDIO data frames, receiving commands via the serial port, and periodically reporting status. These three transactions can be executed independently and in parallel without blocking each other, as detailed below: Transaction 1: Upon receiving an SDIO data frame, it is buffered in the data processing module 220. The module determines whether the data frame is high-speed data (corresponding to a MIPI HS frame) or low-speed data (corresponding to a MIPI LP frame). The determination can be based on CMD52 for low-speed data and CMD53 for high-speed data. If it is high-speed data, an HS (High Speed) request signal is constructed and sent to the physical layer unit 233. Upon receiving a response, high-speed data transmission begins until all data transmission is complete, then the module returns to an idle state and continues monitoring for new data frames. If it is low-speed data, an LP (Low Power) request signal is constructed and sent to the physical layer unit 233. Upon receiving a response, low-speed data transmission begins until all data transmission is complete.

[0091] Transaction 2: After receiving the configuration command, the serial port transceiver unit 241 extracts the parameters in the command frame and updates them to the parameter configuration unit 242.

[0092] Transaction 3: Status monitoring unit 243 periodically reports the status, with a default reporting time of once every 500ms via serial port. The status is then sent to an external interface (such as a UART interface) via serial transceiver unit 241 and uploaded to the host computer. The host computer monitors the status information of each module inside the FPGA in real time.

[0093] Furthermore, in another alternative embodiment, the interface conversion device 10 further includes a clock circuit and a power management circuit.

[0094] The clock circuit is connected to the FPGA chip 200 to provide a reference clock.

[0095] The power management circuit is connected to the FPGA chip 200, the SDIO interface 100 and the D-PHY interface 300 respectively, and is used to supply power to the FPGA chip 200, the SDIO interface 100 and the D-PHY interface 300.

[0096] To better understand, the various hardware circuits used in this application are described below.

[0097] The FPGA chip 200, as the core carrier of all-hardware parallel processing, integrates four core modules: an SDIO protocol receiving module 210, a data processing module 220, a D-PHY protocol transmitting module 230, and a configuration control module 240. It is the only carrier that solves the "performance bottleneck" (hardware acceleration replacing software parsing) and the "insufficient flexibility" (programmable protocol adaptation). Optionally, a low-power FPGA chip 200 can be used because, in some power-sensitive applications, such as mobile devices or portable systems, a low-power FPGA chip can reduce the power consumption of the entire conversion device and extend the device's battery life. At the same time, low-power chips generate less heat, which helps improve system stability and reliability, and reduces the cost and difficulty of heat dissipation design.

[0098] The SDIO Interface 100 circuit (including the physical interface and basic signal conditioning) provides a physical connection channel for SDIO devices (such as SD cards and WiFi modules), enabling the reception of SDIO commands and data. Specifically, the SDIO Interface 100 uses a standard 4-wire system (CLK, CMD, DAT0-DAT3); the interface circuit is designed for ESD protection, with a 22Ω matching resistor in series on the CLK pin (to reduce signal reflection), and 33pF filter capacitors in parallel on the CMD and DAT pins (to suppress noise). It can be connected via a ribbon cable or directly routed on the PCB to connect to SDIO devices. This SDIO Interface 100 circuit is the sole data input entry point, fundamentally solving the problem of poor compatibility (connecting different SDIO devices).

[0099] The D-PHY Interface 300 circuit (including the physical interface and differential signal transmission) provides a physical connection channel for D-PHY receivers (such as displays and industrial cameras), enabling high-speed serial data transmission via D-PHY. Specifically, the D-PHY interface adopts a 1-4 lane configurable design, with each lane containing one pair of differential signal lines (DP / DM). The differential signal lines employ impedance matching (50Ω±10%), supporting a maximum rate of 2.5Gbps / lane. This D-PHY Interface 300 circuit is the sole data output outlet, fundamentally resolving the issue of poor compatibility (connecting different D-PHY devices).

[0100] The clock circuit (including the reference clock source and the FPGA's internal phase-locked loop) uses a temperature-compensated crystal oscillator (TCXO) to provide a stable clock for the SDIO protocol receiving module 210 and the D-PHY protocol transmitting module 230. Specifically, the SDIO clock is generated by the FPGA's internal PLL (phase-locked loop) from a 25MHz reference crystal oscillator through frequency division / multiplication (configurable to 100kHz-200MHz), and the D-PHY clock is generated by another PLL from a 25MHz crystal oscillator. This clock circuit serves as the "time reference" for protocol parsing and data transmission, and is key to solving the "performance bottleneck" (unstable clock leading to insufficient data rate) and "poor compatibility" (adapting to different clock rates). Optionally, a high-precision clock source circuit can be used because both the SDIO interface 100 and the D-PHY interface 300 have high requirements for clock signals, and a high-precision clock source can provide a stable and accurate clock signal. For the SDIO protocol receiving module 210, a stable clock signal helps to accurately recover the data clock and improve the accuracy of data decoding; for the D-PHY protocol transmitting module 230, a precise clock signal can ensure that the encoded and encapsulated data signal meets the timing requirements of the D-PHY interface 300 and avoid data transmission errors.

[0101] The power management circuit (including core voltage and I / O voltage power supply) provides a stable and compliant power supply (such as 1.0V for FPGA core and 3.3V for I / O) for the FPGA chip 200 and interface circuits. It is the energy foundation for the normal operation of all modules and avoids hardware failure due to unstable power supply, which would affect "reliability" and "performance stability".

[0102] Furthermore, in another optional implementation, the number of SDIO interfaces 100 and D-PHY interfaces 300 is n; where n≥2.

[0103] All n SDIO interfaces 100 and n D-PHY interfaces 300 are connected to the FPGA chip 200. The FPGA chip 200 is used to simultaneously perform protocol conversion on the data sent by the n SDIO interfaces 100, and output the converted data to the corresponding D-PHY interfaces 300.

[0104] Understandably, by setting up multiple SDIO interfaces 100 and D-PHY interfaces 300 and designing multi-channel data processing logic in the FPGA chip 200, the data from multiple SDIO interfaces 100 can be processed independently or collaboratively simultaneously, and the processed data can be output to the corresponding D-PHY interfaces. This multi-channel data processing design is suitable for application scenarios that require simultaneous processing of data from multiple SDIO interfaces 100 and output to multiple display devices, such as multi-screen display systems for smart devices, multi-camera data display in security monitoring systems, and multi-screen displays in large-scale exhibitions, greatly improving the system's integration and data processing capabilities.

[0105] Therefore, the FPGA-based interface conversion device 10 provided in this application aims to achieve efficient adaptation between SDIO protocol data sources (e.g., storage, wireless communication modules) and D-PHY protocol outputs (e.g., display devices, image sensors). This solution combines advantages such as high flexibility, excellent performance, compact size, and low cost, and has broad application prospects in multiple fields such as consumer electronics, industrial control, and automotive electronics.

[0106] In the consumer electronics field, smartphones, tablets, and portable cameras commonly require connectivity between SDIO storage / wireless modules and D-PHY displays / image sensors. This solution effectively addresses the issues of large size and high power consumption associated with traditional conversion solutions. Taking a portable camera as an example, its SD card (based on the SDIO protocol) is used to store high-definition images or videos, while the viewfinder (such as an OLED screen using the D-PHY protocol) needs to display the contents of the SD card or the currently captured image in real time. Traditional solutions rely on a processor to parse SDIO data before forwarding it to the D-PHY display, typically resulting in a delay of over 100ms, causing stuttering in the preview. This solution achieves data transmission latency of less than 100 microseconds through full hardware acceleration using FPGA, supporting smooth real-time preview of 4K video. Simultaneously, by integrating all functions into a single FPGA chip, the hardware size is reduced to half that of traditional solutions, better aligning with the trend towards thinner and lighter cameras. Furthermore, its power consumption is reduced by approximately 40% compared to the traditional "processor + peripheral chip" solution, significantly extending the device's battery life.

[0107] In the field of industrial control, this solution is particularly suitable for device interconnection scenarios with high reliability requirements and multi-protocol compatibility, such as production line visual inspection and industrial sensor data acquisition applications. In these scenarios, the SDIO protocol is often used for low-cost storage or sensor modules, while the D-PHY protocol is used to connect high-speed industrial cameras or display terminals. Traditional ASIC solutions typically only support fixed SDIO / D-PHY protocol versions, requiring chip replacement when sensors or displays are upgraded, resulting in high maintenance costs. This solution utilizes the programmable characteristics of FPGAs, supporting one-click switching between SDIO 1.0-3.0 and D-PHY 1.1-2.0 protocol versions by programming bitstream files, adapting to device upgrades without hardware replacement. Simultaneously, the device's built-in configuration and control module can monitor transmission status in real time (such as buffer occupancy and checksum errors), reducing fault location time to minutes, meeting the stringent high availability requirements of industrial scenarios.

[0108] Based on the above device design, in one optional embodiment, this application also provides an interface conversion method, which is applied to the interface conversion device 10 as described in any of the foregoing embodiments. Specifically, please refer to... Figure 6 The interface conversion method includes the following steps: In step S100, the SDIO protocol receiving module receives and parses the SDIO protocol data sent by the SDIO interface, obtains valid SDIO protocol data, and sends it to the data processing module.

[0109] In step S200, the data processing module buffers and synchronizes the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, thereby obtaining the processed data.

[0110] In step S300, the D-PHY protocol sending module encodes and encapsulates the processed data according to the D-PHY protocol to obtain D-PHY protocol data and sends it to the D-PHY interface.

[0111] In summary, the embodiments of this application provide an interface conversion device and method. This application makes a structural breakthrough in addressing the core shortcomings of existing technologies in terms of "flexibility, compatibility, cost, and size." By reconstructing the hardware architecture and design mechanism, this application achieves multi-dimensional advantages that traditional solutions struggle to balance, thereby expanding the application scope of SDIO to D-PHY conversion technology.

[0112] In terms of architectural design, existing ASIC or general-purpose processor solutions typically rely on fixed hardware circuits or processor-based software parsing, making it difficult to simultaneously achieve flexibility and high performance. This application adopts a parallel processing architecture based on programmable FPGA hardware, which balances the flexibility of protocol configuration and the high performance of data transmission, can adapt to the iteration of different protocol versions, and significantly reduces transmission latency.

[0113] In terms of compatibility, existing technologies typically only support a single protocol version and a fixed rate, limiting their applicability. This application achieves full-dimensional compatibility in terms of protocol, rate, and device type, covering various application scenarios from low-speed control to high-speed transmission, supporting the reuse of a single device in different scenarios, and effectively reducing the overall cost of multi-scenario deployment.

[0114] At the hardware integration level, existing ASIC solutions incur high tape-out costs, while general-purpose processor solutions often require multiple peripheral chips, resulting in large system size and high overall cost. This application integrates all functions using a single FPGA chip, eliminating the need for redundant peripheral chips, significantly reducing hardware costs while drastically shrinking the device size. Its core value lies in its suitability for applications requiring small to medium batch production and rapid iteration, and its support for highly integrated, miniaturized installation.

[0115] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0116] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. An interface conversion device, characterized in that, include: An FPGA chip, an SDIO interface, and a D-PHY interface; the FPGA chip includes: an SDIO protocol receiving module, a data processing module, and a D-PHY protocol transmitting module; The SDIO interface, SDIO protocol receiving module, data processing module, D-PHY protocol sending module, and D-PHY interface are connected in sequence. The SDIO protocol receiving module is used to receive and parse the SDIO protocol data sent by the SDIO interface, obtain valid SDIO protocol data, and send it to the data processing module; The data processing module is used to buffer and synchronize the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, and obtain the processed data. The D-PHY protocol sending module is used to encode and encapsulate the processed data according to the D-PHY protocol to obtain D-PHY protocol data and send it to the D-PHY interface. The data processing module includes: a cache control unit and a cache synchronization unit; The cache synchronization unit is connected to both the SDIO protocol receiving module and the D-PHY protocol sending module; the cache control unit is connected to both the cache synchronization unit and the SDIO protocol receiving module. The cache control unit is used to monitor the cache occupancy rate of the asynchronous first-in-first-out cache in the cache synchronization unit in real time, and send a pause reception signal or a resume reception signal to the SDIO protocol receiving module according to the cache occupancy rate; The cache synchronization unit is used to buffer and synchronize the valid SDIO protocol data, and eliminates the rate and clock domain differences between the SDIO interface and the D-PHY interface through the asynchronous first-in-first-out buffer. The D-PHY protocol transmission module includes: a low-speed signal unit, a high-speed signal unit, and a physical layer unit; Both the low-speed signal unit and the high-speed signal unit are connected to the data processing module, and both the low-speed signal unit and the high-speed signal unit are also connected to the physical layer unit, which is also connected to the D-PHY interface. The low-speed signal unit is used to receive low-speed data from the data processing module, construct a low-speed request signal and send it to the physical layer unit; when a response is received from the physical layer unit, low-speed data is sent to the physical layer unit until all low-speed data is sent. The high-speed signal unit is used to receive high-speed data from the data processing module, construct a high-speed request signal and send it to the physical layer unit; when a response is received from the physical layer unit, high-speed data is sent to the physical layer unit until all high-speed data is sent. The physical layer unit is used to convert the data sent by the low-speed signal unit and / or the high-speed signal unit into D-PHY protocol data conforming to the MIPI D-PHY specification, and send it to the D-PHY interface.

2. The interface conversion device according to claim 1, characterized in that, The SDIO protocol data includes SDIO command frames and SDIO data frames; the SDIO protocol receiving module includes: a command parsing unit, a data extraction unit, and a data verification unit; the command parsing unit and the data extraction unit are both connected to the SDIO interface, the command parsing unit is also connected to the data extraction unit and the data verification unit respectively, the data extraction unit is also connected to the data verification unit, and the data verification unit is also connected to the data processing module; The command parsing unit is used to parse SDIO command frames through a hardware state machine to extract key control information and send it to the data extraction unit and the data verification unit. The data extraction unit is used to extract valid SDIO protocol data from the SDIO data frame based on the key control information and send it to the data verification unit. The data verification unit is used to perform cyclic redundancy check (CRUD) of SDIO command frames and SDIO data frames through hardware. When the verification fails, the data verification unit automatically triggers a retransmission request mechanism to re-receive and verify the erroneous SDIO data frame until the verification is successful or the number of retransmission requests reaches a set value. When the verification is successful, the data verification unit sends the valid SDIO protocol data to the data processing module.

3. The interface conversion device according to claim 1, characterized in that, The FPGA chip also includes: a configuration control module; The configuration control module is connected to the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The configuration control module is used to receive configuration instructions sent by the host computer through an external interface, and dynamically adjust the parameters of the SDIO protocol receiving module, the data processing module and the D-PHY protocol sending module according to the configuration instructions.

4. The interface conversion device according to claim 3, characterized in that, The configuration control module includes: a serial port transceiver unit and a parameter configuration unit; The parameter configuration unit is connected to the serial port transceiver unit, the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The serial port transceiver unit is used to receive the configuration command sent by the host computer through the external interface, and send the configuration command to the parameter configuration unit; The parameter configuration unit is used to parse the received configuration instructions and update the parameters of the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module according to the parsed configuration instructions.

5. The interface conversion device according to claim 4, characterized in that, The configuration control module further includes: a status monitoring unit; The status monitoring unit is connected to the serial port transceiver unit, the SDIO protocol receiving module, the data processing module, and the D-PHY protocol sending module, respectively. The status monitoring unit is used to collect the operating status data of the SDIO protocol receiving module, the data processing module and the D-PHY protocol sending module in real time, and send the operating status data of each module to the serial port transceiver unit. The serial transceiver unit is also used to convert the operating status data of each module into serial signals and send them to the host computer through the external interface.

6. The interface conversion device according to claim 1, characterized in that, The number of SDIO interfaces and D-PHY interfaces is n; where n≥1; All n SDIO interfaces and n D-PHY interfaces are connected to the FPGA chip; The FPGA chip is used to simultaneously perform protocol conversion on the data sent by the n SDIO interfaces, and output the converted data to the corresponding D-PHY interface.

7. The interface conversion device according to claim 1, characterized in that, The interface conversion device further includes: a clock circuit and a power management circuit; The clock circuit is connected to the FPGA chip and is used to provide a reference clock; The power management circuit is connected to the FPGA chip, the SDIO interface and the D-PHY interface respectively, and is used to supply power to the FPGA chip, the SDIO interface and the D-PHY interface.

8. An interface conversion method, characterized in that, Applied to the interface conversion apparatus as described in any one of claims 1-7, the method comprises: The SDIO protocol receiving module receives and parses the SDIO protocol data sent by the SDIO interface, obtains valid SDIO protocol data, and sends it to the data processing module; The data processing module buffers and synchronizes the valid SDIO protocol data to eliminate the rate and clock domain differences between the SDIO interface and the D-PHY interface, thereby obtaining the processed data. The D-PHY protocol sending module encodes and encapsulates the processed data according to the D-PHY protocol to obtain D-PHY protocol data and sends it to the D-PHY interface.

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