Chip resistant to solder overflow and packaging method thereof

Abstract

The present application relates to a kind of anti-solder overflow chip and its packaging method.The chip back has pattern structure, the pattern structure includes sunken platform, embankment, dense slot array, sparse slot array and non-wetting area;The sunken platform is located in the middle of chip back, the sunken platform is formed with embankment around, and the surface of the sunken platform is lower than the surface of embankment;There are several sparse slots in the middle of the sunken platform to form sparse slot array;There are several dense slots at both ends of the sunken platform to form dense slot array;The upper surface of the embankment is covered with non-wetting material to form non-wetting area.The chip of the present application combines embankment, dense slot array and non-wetting area, and constitutes a multi-level cooperative defense system, realizes solder multi-level anti-overflow, and the anti-overflow effect is extremely remarkable.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging technology, specifically relating to a chip resistant to solder overflow and its packaging method. Background Technology

[0002] In semiconductor packaging processes, chips are typically soldered to heat sinks using reflow soldering technology, which effectively improves heat dissipation efficiency and thus extends chip lifespan. The higher the power of the chip or solder pad, the more demanding the soldering requirements become. A common technical challenge in this process is solder overflow. During reflow soldering, molten solder may overflow from the soldering area due to capillary action, pressure, or uneven heating. Overflowing solder can cause short circuits between adjacent solder joints or bridge to nearby chip circuitry, leading to chip malfunction or even damage. Traditional solutions include using solder resist or reducing solder volume, but solder resist has limited positioning accuracy and is ineffective at the micrometer scale, while reducing solder volume may affect the mechanical strength of the solder joints and the reliability of electrical connections. Therefore, optimizing the chip structure is the preferred approach to solve the solder overflow problem.

[0003] Chinese patent document CN211238214U proposes a chip for controlling solder overflow. The chip's positive electrode has trenches, solving the technical problem of excessive solder overflow from the side during the reflow soldering process, which affects chip performance. However, during chip or bar packaging, the negative electrode, lacking a patterned structure, is more prone to solder overflow. Chinese patent document CN218632785U discloses a chip for controlling solder overflow, proposing a chip structure with soldering grooves and drainage grooves on the bottom sidewall of the chip body. The space of the soldering grooves and multiple drainage grooves limits the height of solder overflow, thereby reducing the solder overflow area and preventing it from climbing to the side of the chip. This solution only reduces solder overflow to a certain extent but does not consider heat dissipation. Therefore, how to effectively confine molten solder and fundamentally prevent solder overflow during reflow soldering remains a technical challenge. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a chip resistant to solder overflow and its packaging method.

[0005] The main objectives of this invention include how to effectively prevent solder overflow during chip packaging while improving heat dissipation.

[0006] Terminology Explanation: SiNx: refers to silicon nitride with a non-fixed stoichiometric ratio, where x is a variable representing that the atomic ratio of nitrogen to silicon is not fixed.

[0007] This invention proposes a multi-level confinement barrier chip structure on the chip surface, which can effectively confine molten solder and fundamentally prevent solder from overflowing during reflow soldering.

[0008] The technical solution of the present invention is as follows: A chip resistant to solder overflow, the back of the chip having a patterned structure, the patterned structure including a sunken platform, a embankment, a dense trench array, a sparse trench array, and a non-wetting area; The sinking platform is located in the middle of the back of the chip, and a embankment is formed around the sinking platform. The surface of the sinking platform is lower than the surface of the embankment. There are several sparse grooves in the middle of the sinking platform to form a sparse groove array. There are several dense grooves at both ends of the sinking platform to form a dense groove array. The upper surface of the embankment is covered with a non-wetting material to form a non-wetting area.

[0009] According to a preferred embodiment of the present invention, the sparse slot array is located in the ridge region corresponding to the P-surface light emission in the middle of the sunken platform.

[0010] According to a preferred embodiment of the present invention, the dense groove array is disposed on both sides of the sinking platform near the front and rear cavity surfaces.

[0011] The present invention also provides a method for preparing the above-mentioned anti-solder overflow chip.

[0012] A method for fabricating a chip resistant to solder overflow includes the following steps: (1) Constructing the sunken platform and embankment A sunken platform is fabricated on the back of the chip, and a raised embankment is formed around the sunken platform; the sunken platform is used to contain the main volume of solder; the embankment serves as the first physical barrier to prevent the solder from overflowing.

[0013] (2) Fabrication of slot array A sparse trench array is fabricated in the ridge region corresponding to the P-side light emission in the middle of the sunken platform. The sparse trench array ensures solder filling and stress release, while avoiding weakening the mechanical strength and thermal conductivity of the chip's heat-generating area due to excessively dense trenches.

[0014] A dense groove array is fabricated on both sides of the sinking platform near the front and rear cavity surfaces. The dense groove array acts as a flow resistance barrier to prevent the solder from overflowing outwards. It can greatly increase the capillary resistance and flow resistance of the molten solder flowing towards the embankment, effectively adsorbing and anchoring the solder, making it difficult for it to cross.

[0015] (3) Preparation of non-wetting area A non-wetting material film is deposited on the top surface of the embankment to form a non-wetting zone. This film has extremely low adhesion to solder, so that even if a small amount of solder approaches or contacts the outside of the embankment, it will retract due to surface tension, thus forming a chemical barrier.

[0016] According to a preferred embodiment of the present invention, in step (1), the sinking platform is fabricated by wet corrosion.

[0017] According to a preferred embodiment of the present invention, in step (2), sparse trench arrays and dense trench arrays are fabricated by dry etching.

[0018] According to a preferred embodiment of the present invention, in step (2), the sparse slot array has a slot width of 0.1X-0.2X and a slot length of 0.1Y-0.3Y, where X is the chip ridge width and Y is the chip cavity length.

[0019] According to a preferred embodiment of the present invention, in step (2), the sparse slot array is positioned laterally with the starting slots on both sides corresponding to the edges of the ridge, and the slot spacing is 0.2X-0.3X, where X is the width of the chip ridge; the sparse slot array is positioned longitudinally with the distance between the front and rear cavity surfaces being 0.1Y-0.2Y, and the spacing between two rows of slots is 0.3Y-0.4Y, where Y is the chip cavity length.

[0020] According to a preferred embodiment of the present invention, in step (2), the slot spacing of the dense slot array is 0.01Z-0.1Z, where Z is the chip width, the slot width is 0.01Z-0.05Z, and the slot length is 0.01Y-0.05Y.

[0021] According to a preferred embodiment of the present invention, in step (2), the depths of both the sparse trench array and the dense trench array are less than the height of the embankment.

[0022] According to a preferred embodiment of the present invention, in step (3), the non-wetting material is SiO2 or SiNx.

[0023] Secondly, the present invention also provides a packaging method for the above-mentioned anti-solder overflow chip.

[0024] A chip packaging method to prevent solder overflow includes the following steps: The chip is mounted upright on a heat sink, with solder pads placed between the heat sink and the back of the chip. Then, a reflow soldering process is performed, where molten solder fills the sparse and dense grooves on the sinking platform. The solder is confined within the sinking platform, and the sparse groove array, dense groove array, embankment, and non-wetting area form a multi-level solder confinement system, resulting in a good sintering interface.

[0025] Technical features and beneficial effects of the present invention: 1. The chip of this invention combines physical barriers (embankments), flow resistance barriers (dense trench arrays) and chemical barriers (non-wetting areas) to form a multi-layered collaborative defense system, achieving multi-level solder overflow prevention with extremely significant overflow prevention effect.

[0026] 2. The pattern structure of the chip of the present invention is integrated during the chip manufacturing process, without the need to change the subsequent packaging process, and has strong compatibility.

[0027] 3. The chip of the present invention has a sparse slot array in the ridge area corresponding to the chip light emission. When the chip is working, the ridge area is a heat accumulation area. The sparse slot array design ensures the performance and life of the chip's critical areas. Effective solder restriction ensures the uniformity of the solder joint shape and height, and improves the mechanical and electrical reliability of the package.

[0028] 4. The chip of this invention fundamentally eliminates product failure caused by solder short circuits, and greatly improves the yield of packaging production. Attached Figure Description

[0029] Figure 1 This is a bottom view of the chip structure of the present invention; Figure 2 For along Figure 1 A schematic diagram of the cross-sectional structure of line AB in the middle section; Figure 3 This is a schematic diagram of the chip structure after packaging according to the present invention.

[0030] Explanation of reference numerals in the attached figures: 1. Chip body, 2. Sinking platform, 3. Embankment, 4. Chip ridge, 5. Sparse trench array, 6. Dense trench array, 7. Front cavity surface cross-section, 8. Rear cavity surface cross-section, 9. Non-wetting area, 10. Heat sink, 11. Solder; X, ridge width, Y, chip cavity length, Z, chip width. Detailed Implementation

[0031] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto. The described embodiments are some embodiments of the present invention. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and should not be construed as limiting the invention. In this embodiment, the back side of the chip is the bottom surface of the chip substrate.

[0033] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. Unless otherwise specified in the embodiments of the present invention, all techniques existing in the art can be used.

[0034] Example 1 like Figure 1-2As shown, a chip that prevents solder 11 from overflowing has a patterned structure on the back of the chip body 1. The patterned structure includes a sunken platform 2, a embankment 3, a dense trench array 6, a sparse trench array 5, and a non-wetting area 9. The sinking platform 2 is located in the middle of the back of the chip body 1. A embankment 3 is formed around the sinking platform 2, and the surface of the sinking platform 2 is lower than the surface of the embankment 3. There are several sparse grooves in the middle of the sinking platform 2 corresponding to the ridge 4 of the P-side light emission, forming a sparse groove array. There are several dense grooves on both sides of the sinking platform 2 near the front and rear cavity surfaces, forming a dense groove array 6. The upper surface of the embankment 3 is covered with a non-wetting material to form a non-wetting area 9.

[0035] The above-mentioned method for fabricating a chip resistant to solder overflow includes the following steps: (1) Constructing the sunken platform and embankment A sunken platform 2 is fabricated on the back of the chip body 1 by wet etching, and a raised embankment 3 is formed around the sunken platform 2. The sunken platform is used to contain the solder of the main volume. The embankment serves as the first physical barrier to prevent the solder from overflowing.

[0036] (2) Fabrication of slot array A sparse trench array 5 is fabricated in the region of the ridge 4 corresponding to the P-side light emission in the middle of the sunken platform 2 using dry etching. The trench width is 0.15X and the trench length is 0.2Y. In the horizontal direction, the starting trench positions on both sides of the sparse trench array 5 correspond to the two edges of the ridge 4, and the trench spacing is 0.25X, where X is the width of the chip ridge 4. In the vertical direction, the distance between the sparse trench array 5 and the front and rear cavity surfaces is 0.15Y, and the spacing between two rows of trenches is 0.35Y, where Y is the chip cavity length. The depth of the trench array is less than the height of the embankment 3. The sparse trench array ensures solder filling and stress release while avoiding weakening the mechanical strength and thermal conductivity of the chip's heat-generating area due to excessively dense trenches.

[0037] A dense trench array 6 is fabricated on both sides of the sunken platform 2 near the front and rear cavity surfaces using dry etching. The trench spacing is 0.05Z, where Z is the chip width, the trench width is 0.03Z, and the trench length is 0.03Y. The depth of the trench array is less than the height of the embankment 3. The dense trench array acts as a flow resistance barrier to prevent solder from overflowing, greatly increasing the capillary resistance and flow resistance of the molten solder flowing towards the embankment, effectively adsorbing and anchoring the solder, making it difficult for it to cross.

[0038] (3) Preparation of non-wetting area A SiO2 thin film is deposited on the upper surface of the embankment 3 to form a non-wetting zone 9. This film has extremely low adhesion to solder, so that even if a small amount of solder approaches or contacts the outside of the embankment, it will retract due to surface tension, thus forming a chemical barrier.

[0039] The above-mentioned chip packaging method for preventing solder overflow, such as Figure 3As shown, the steps include: The chip body 1 is mounted upright on the heat sink 10. A solder pad is placed between the heat sink 10 and the back of the chip body 1. Then, a reflow soldering process is performed. The molten solder 11 fills the dense and sparse grooves of the sinking platform 2. The solder is confined within the sinking platform 2. The sparse groove array 5, the dense groove array 6, the embankment 3, and the non-wetting area 9 prevent it from overflowing, forming a reliable solder joint.

[0040] In the encapsulation method of the present invention, the solder, when in a molten state, is subjected to heat sink compression and will preferentially fill the sinking platform, dense groove and sparse groove. Furthermore, the embankment 3 and the non-wetting area 9 can prevent the solder from climbing upward along the side of the sinking platform. The sinking platform, embankment, dense groove, sparse groove and non-wetting area are combined to form a multi-layered collaborative defense system, achieving multi-level solder overflow prevention and the overflow prevention effect is extremely significant.

[0041] Example 2 As described in Example 1, the difference is: In step (2), the sparse slot array 5 has a slot width of 0.2X, a slot length of 0.1Y, a slot spacing of 0.2X in the horizontal direction, and a spacing of 0.4Y between two rows of slots in the vertical direction; the dense slot array 6 has a slot spacing of 0.08Z, a slot width of 0.04Z, and a slot length of 0.05Y.

[0042] In step (3), a SiNx thin film is deposited on the top surface of the embankment 3 to form a non-wetting region 9.

[0043] The other steps and conditions are the same as in Example 1.

Claims

1. A chip resistant to solder overflow, characterized in that, The back of the chip has a patterned structure, which includes a sunken platform, a embankment, a dense trench array, a sparse trench array, and a non-wetting area. The sinking platform is located in the middle of the back of the chip, and a embankment is formed around the sinking platform. The surface of the sinking platform is lower than the surface of the embankment. A sparse groove array is formed in the middle of the sinking platform, and the sparse groove array is located in the middle of the sinking platform corresponding to the ridge area of ​​the P-side light emission. A dense groove array is formed at both ends of the sinking platform, and the dense groove array is set on both sides of the sinking platform near the front and rear cavity surfaces. The upper surface of the embankment is covered with a non-wetting material to form a non-wetting area. The sparse slot array has a slot width of 0.1X-0.2X and a slot length of 0.1Y-0.3Y. In the horizontal direction, the starting slots on both sides of the sparse slot array correspond to the edges of the ridges on both sides, with a slot spacing of 0.2X-0.3X, where X is the width of the chip ridge. In the vertical direction, the sparse slot array is 0.1Y-0.2Y away from both the front and rear cavity surfaces, and the spacing between two rows of slots is 0.3Y-0.4Y, where Y is the chip cavity length. The dense slot array has a slot pitch of 0.01Z-0.1Z, where Z is the chip width, the slot width is 0.01Z-0.05Z, and the slot length is 0.01Y-0.05Y.

2. A method for fabricating a solder overflow resistant chip as described in claim 1, characterized in that, Including the following steps: (1) Constructing the sunken platform and embankment A sunken platform is created on the back of the chip, and a raised embankment is formed around the sunken platform; (2) Fabrication of slot array A sparse slot array is fabricated in the ridge region corresponding to the P-surface light emission in the middle of the sunken platform; A dense array of grooves is fabricated on both sides of the sinking platform near the front and rear cavity surfaces; (3) Preparation of non-wetting area A thin film of non-wetting material is deposited on the top surface of the embankment to form a non-wetting zone.

3. The method for fabricating a solder overflow resistant chip according to claim 2, characterized in that, In step (1), the sinking platform is fabricated by wet corrosion.

4. The method for fabricating a solder overflow resistant chip according to claim 2, characterized in that, In step (2), sparse trench arrays and dense trench arrays are fabricated by dry etching.

5. The method for fabricating a solder overflow resistant chip according to claim 2, characterized in that, In step (3), the non-wetting material is SiO2 or SiNx.

6. A chip packaging method for resisting solder overflow as described in claim 1, characterized in that, Including the following steps: The chip is mounted upright on a heat sink, with solder pads placed between the heat sink and the back of the chip. Then, a reflow soldering process is performed, where molten solder fills the sparse and dense grooves on the sinking platform. The solder is confined within the sinking platform, and the sparse groove array, dense groove array, embankment, and non-wetting area form a multi-level solder confinement system, resulting in a good sintering interface.

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