Integrated electronic device initiating circuit of initiating explosive capable of suppressing power-on spike voltage

Abstract

This invention relates to an ignition circuit for pyrotechnic devices, specifically an integrated electronic device ignition circuit capable of suppressing power-on spike voltage. Its purpose is to solve the problem that existing pyrotechnic ignition circuits generate microsecond-level power-on spike voltages at the output during operation, easily causing false activation of pyrotechnic devices and thus posing a hazard to products and personnel. This invention incorporates a power-on spike voltage suppression module between the PMOS transistors and the VCC power supply. This module contains two PMOS transistors, both with their sources connected to the VCC power supply. The gate of PMOS transistor V3 is connected to ground via resistors R5 and R108, and the gate of PMOS transistor V4 is connected to ground via resistors R6 and R108. A soft-start time control resistor is connected in series between resistors R5, R6, and R108. A first delay capacitor bank is connected in parallel between the sources of PMOS transistors V3 and V4 and resistors R5 and R6, thereby delaying the conduction time of PMOS transistor V1 after the VCC power supply is powered on, thus suppressing the power-on spike voltage.

Description

Technical Field

[0001] This invention relates to an ignition circuit for pyrotechnic devices, specifically to an integrated electronic device ignition circuit capable of suppressing power-on spike voltage. Background Technology

[0002] In the aerospace and defense fields, with the development trends of integration, intelligence, and cost reduction, the demand for integrated electronic equipment is increasing. Integrated electronic equipment mainly includes functional units such as information management and scheduling, integrator, satellite navigation, data link, electronic control, telemetry, information processing, and power management. Each unit cooperates with the others, with different divisions of labor, to ensure that the integrated electronic equipment operates according to the correct working sequence.

[0003] In integrated electronic equipment, the ignition circuit for pyrotechnic devices is responsible for completing the ignition operation of pyrotechnic devices under the control of the electronic control module. Pyrotechnic devices are a general term for small, sensitive explosive elements or devices made of explosives. They ignite or explode upon exposure to external stimuli, performing functions such as power activation, engine deactivation and ignition, and interstage separation ignition.

[0004] The commonly used ignition circuits for pyrotechnics are as follows: Figure 1 , Figure 2 As shown, the device includes an ignition circuit 01 and a VCC power supply 02. The ignition circuit 01 includes optocouplers D1 and D2, and MOSFETs V1 and V2. The semiconductor devices inside optocouplers D1 and D2 have parasitic capacitances. MOSFETs V1 and V2 have parasitic capacitances Cgs between their gate and source, Cgd between their gate and drain, and Cds between their drain and source. When the ignition circuit is powered on and a control command is simultaneously input to optocouplers D1 and D2, the VCC power supply 02 charges the parasitic capacitances through resistor R11 and Cgs through resistor R1. At this time, the gate-source voltage Ugs of MOSFETs V1 and V2 gradually increases. When Ugs reaches the threshold voltage, current begins to flow through MOSFETs V1 and V2, generating a voltage difference at the output of the ignition circuit 01. The current then flows through the pyrotechnic device, igniting it.

[0005] However, during the above process, a tiny current has already flowed through the MOSFET before Ugs reaches the threshold voltage. At this time, the output of the ignition circuit 01 will generate a microsecond-level power-on spike voltage, causing a metastable state at the moment of power-on. If the energy reaches a certain threshold, it will cause false activation of the pyrotechnic device, which may easily cause harm to the product and personnel. Summary of the Invention

[0006] The main objective of this invention is to solve the problem that existing pyrotechnic ignition circuits generate microsecond-level power-on spike voltages at the output terminal during operation, which can easily cause false activation of pyrotechnics and thus endanger products and personnel. The invention provides a comprehensive electronic device pyrotechnic ignition circuit that can suppress power-on spike voltages.

[0007] The concept of this invention is:

[0008] Adjust the power-on time of the MOSFET power supply and conduct a MOSFET conduction experiment. The results are as follows: Figure 3 , Figure 4 As shown, when the power-on time is set to 0.1μs, the maximum gate-source voltage difference of the PMOS transistor during the experiment is 3.4V, which is greater than the turn-on voltage of 2V, indicating that the PMOS transistor is fully turned on. However, the maximum gate-source voltage difference of the NMOS transistor is 1.8V, which is less than the turn-on voltage of 2V, indicating that it is not fully turned on. When the power-on time is set to 100μs, the gate-source voltage difference of both the PMOS and NMOS transistors is close to 0V, indicating that both are in the off state.

[0009] Therefore, it can be concluded that when the power-on time is greater than the charging time of the gate-source parasitic capacitance Cgs of the PMOS transistor, short-term conduction during the power-on process of the PMOS transistor can be avoided, thereby effectively suppressing the power-on voltage spike and avoiding the risk of false activation of pyrotechnic devices.

[0010] To achieve the above-mentioned objectives and complete the above-mentioned inventive concept, the present invention provides the following technical solution:

[0011] An integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage includes an ignition circuit and a VCC power supply. The output of the ignition circuit generates a voltage difference for igniting the pyrotechnic device. Its unique feature is that:

[0012] It also includes a power-on spike voltage suppression module located between the VCC power supply and the ignition circuit;

[0013] The ignition circuit includes optocoupler D1, optocoupler D2, PMOS transistor V1, and NMOS transistor V2;

[0014] The positive terminal of the VCC power supply is connected to the input terminal of the power-on spike voltage suppression module, and the negative terminal is grounded. The output terminal of the power-on spike voltage suppression module is simultaneously connected to the source of PMOS transistor V1 and the high-side output of optocoupler D1, and is also connected to the high-side output of optocoupler D1 through resistor R11. The high-side output of optocoupler D1 is connected to the gate of PMOS transistor V1 through resistor R1, and the low-side output is grounded. The drain of PMOS transistor V1 is the positive output of the ignition circuit.

[0015] The low-end output of the optocoupler D2 is grounded in sequence through resistors R13 and R14, and connected to the gate of NMOS transistor V2 through resistor R2. The source of NMOS transistor V2 is grounded, and the drain is the negative output of the ignition circuit.

[0016] The high-end inputs of optocouplers D1 and D2 are used to connect to an external 5V power supply, while the low-end inputs receive control commands to control the ignition circuit.

[0017] The power-on spike voltage suppression module includes PMOS transistors V3 and V4, resistors R106 and R108. One end of resistor R106 is connected to the positive terminal of the VCC power supply, and the other end is connected to one end of resistor R108. The other end of resistor R108 is grounded. The sources of PMOS transistors V3 and V4 are connected together and serve as the input terminals of the power-on spike voltage suppression module, connected to the positive terminal of the VCC power supply. The gate of PMOS transistor V3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to resistor R108. One end of resistor R4 is connected to the gate of PMOS transistor V4, and the other end of resistor R6 is connected to one end of resistor R108. A soft-start time control resistor is connected in series between the other ends of resistor R5 and resistor R6 and one end of resistor R108. A first delay capacitor group is connected in parallel between the source of PMOS transistor V3 and PMOS transistor V4 and resistors R5 and R6, respectively, for charging and discharging PMOS transistor V3 and PMOS transistor V4 before power-on, so that PMOS transistor V3 and PMOS transistor V4 are slowly turned on.

[0018] The drains of PMOS transistors V3 and V4 are connected, and the output terminal of the power-on spike voltage suppression module is connected to the source of PMOS transistor V1.

[0019] Furthermore, the soft-start time control resistor includes resistors R110* and R111* connected in parallel. The resistance values ​​of resistors R110* and R111* can be adjusted according to usage requirements to adjust the power-on time of PMOS transistors V3 and V4.

[0020] Furthermore, the first delay capacitor group includes capacitors C115* and C116* connected in parallel between the source of PMOS transistor V3 and the other end of resistor R5, and capacitors C113* and C114* connected in parallel between the source of PMOS transistor V4 and the other end of resistor R6.

[0021] Furthermore, a second delay capacitor bank is connected between the drain terminals of PMOS transistors V3 and V4 and ground, which is used to charge and discharge PMOS transistor V1 before it is powered on, thereby further delaying the power-on time of PMOS transistor V1.

[0022] Furthermore, the second delay capacitor group includes capacitors C105, C106, C107, and C108. One end of capacitor C105 is connected to one end of capacitor C106, and one end of capacitor C107 is connected to one end of capacitor C108. The other ends of capacitors C105 and C107 are both connected to the drains of PMOS transistors V3 and V4, respectively, and the other ends of capacitors C106 and C108 are both grounded.

[0023] Compared with the prior art, the beneficial effects of the present invention are:

[0024] 1. The present invention provides an integrated electronic device ignition circuit for suppressing power-on spike voltage. By setting a PMOS transistor and a capacitor to extend the power-on time, the power-on time is made longer than the charging time of the gate-source parasitic capacitance of the MOS transistor, thereby effectively suppressing the power-on spike voltage, ensuring that the pyrotechnic device is not accidentally activated, and improving the safety and reliability of the ignition circuit.

[0025] 2. The present invention provides an integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage. The power-on spike voltage suppression module achieves an ideal and effective power-on spike voltage suppression effect while having the advantages of fewer electronic components and simpler structure, and can effectively control cost and power consumption.

[0026] 3. The present invention provides an integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage. According to the usage requirements, soft-start time control resistors R110* and R111* with different resistance values ​​can be selected and connected in parallel, thereby enhancing the functional flexibility and versatility of the power-on spike voltage suppression module. Attached Figure Description

[0027] Figure 1 The circuit diagram is shown below for the ignition circuit of commonly used pyrotechnic devices in the background art.

[0028] Figure 2 This is a schematic diagram of the circuit structure of ignition circuits commonly used in pyrotechnic devices in the background art;

[0029] Explanation of reference numerals in the attached figures:

[0030] 01-Ignition circuit; 02-VCC power supply;

[0031] Figure 3 The figures show the gate voltage changes of the PMOS and NMOS transistors and the VCC power supply voltage during a power-on time of 0.1μs in this invention. The blue line represents the VCC power supply voltage change, the red line represents the PMOS transistor gate voltage change, and the green line represents the NMOS transistor gate voltage change.

[0032] Figure 4The graphs show the gate voltage changes of the PMOS and NMOS transistors and the VCC power supply voltage during a power-on time of 100μs in this invention. The blue line represents the VCC power supply voltage change curve, the red line represents the PMOS transistor gate voltage change curve, and the green line represents the NMOS transistor gate voltage change curve.

[0033] Figure 5 This is a circuit diagram of an embodiment of an integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage according to the present invention.

[0034] Figure 6 This is a schematic diagram of the circuit structure of the power-on spike voltage suppression module in an embodiment of the ignition circuit of a pyrotechnic device for an integrated electronic device capable of suppressing power-on spike voltage according to the present invention.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1-Ignition circuit; 2-VCC power supply; 3-Power-on spike voltage suppression module. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0038] An integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on voltage spikes, the circuit principle of which is as follows: Figure 5 As shown, it includes an ignition circuit 1 and a VCC power supply 2. The output terminal of the ignition circuit 1 generates a voltage difference to ignite the pyrotechnic device; the output voltage of the VCC power supply 2 is 28.5V.

[0039] A power-on spike voltage suppression module 3 is provided between the ignition circuit 1 and the VCC power supply 2. The power-on spike voltage suppression module 3 includes PMOS transistors V3 and V4, resistors R106 and R108. One end of resistor R106 is connected to the positive terminal of the VCC power supply 2, and the other end is connected to one end of resistor R108. The other end of resistor R108 is grounded. The sources of PMOS transistors V3 and V4 are connected and serve as the input terminals of the power-on spike voltage suppression module 3, which are connected to the positive terminal of the VCC power supply 2.

[0040] The gate of PMOS transistor V3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of resistor R108. The gate of PMOS transistor V4 is connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of resistor R108. A soft-start time control resistor is connected in series between the other ends of resistors R5 and R6 and one end of resistor R108. A first delay capacitor group is connected in parallel between the source of PMOS transistors V3 and V4 and resistors R5 and R6, respectively, for charging and discharging PMOS transistors V3 and V4 before power-on, so that PMOS transistors V3 and V4 are slowly turned on.

[0041] The soft-start time control resistors include resistors R110* and R111* connected in parallel. The resistance values ​​of resistors R110* and R111* can be adjusted according to usage requirements to adjust the power-on time of PMOS transistors V3 and V4. In this embodiment, the resistance values ​​of resistors R110* and R111* are both 1MΩ. Meanwhile, the first delay capacitor group includes capacitors C115* and C116* connected in parallel between the source of PMOS transistor V3 and the other end of resistor R5, and capacitors C113* and C114* connected in parallel between the source of PMOS transistor V4 and the other end of resistor R6.

[0042] A second delay capacitor bank is connected between the drain terminals of PMOS transistors V3 and V4 and ground. This bank is used to charge and discharge PMOS transistor V1 before it is powered on, thereby further delaying the power-on time of PMOS transistor V1. The second delay capacitor bank includes capacitors C105, C106, C107, and C108. One end of capacitor C105 is connected to one end of capacitor C106, and one end of capacitor C107 is connected to one end of capacitor C108. The other ends of capacitors C105 and C107 are connected to the drain terminals of PMOS transistors V3 and V4, respectively. The other ends of capacitors C106 and C108 are grounded. In this embodiment, the capacitance of capacitors C105, C106, C107, and C108 is 22μF.

[0043] In this embodiment, the resistance values ​​of resistors R5 and R6 are both 20Ω; the resistance value of resistor R108 is 20.5KΩ; and the resistance value of resistor R106 is 11KΩ.

[0044] The drains of PMOS transistors V3 and V4 serve as the output terminals of the power-on spike voltage suppression module 3, and are simultaneously connected to the source of PMOS transistor V1 and the high-end output of optocoupler D1. The high-end output of optocoupler D1 is also connected to the high-end output of optocoupler D1 through resistor R11. The high-end output of optocoupler D1 is connected to the gate of PMOS transistor V1 through resistor R1, and the low-end output is grounded. The drain of PMOS transistor V1 is the positive output of ignition circuit 1.

[0045] The low-end output of the optocoupler D2 is grounded in sequence through resistors R13 and R14, and connected to the gate of NMOS transistor V2 through resistor R2. The source of NMOS transistor V2 is grounded, and the drain is the negative output of ignition circuit 1.

[0046] The high-end inputs of optocouplers D1 and D2 are used to connect to an external 5V power supply, and the low-end inputs receive control commands to control the ignition circuit 1 to work. A resistor R59 is connected between the low-end input of optocoupler D1 and the control command source, and a resistor R60 is connected between the low-end input of optocoupler D2 and the control command source. The resistance values ​​of resistors R59 and R60 are both 332Ω.

[0047] An overcurrent protection resistor R4 with a resistance of 100KΩ is connected in parallel between the positive and negative output terminals of ignition circuit 1.

[0048] The working process of this embodiment is as follows:

[0049] When the cathodes of optocouplers D1 and D2 simultaneously receive control commands, optocouplers D1 and D2 begin to operate. The collector of optocoupler D1 transmits current to the gate of PMOS transistor V1 through resistor R1. At this time, the first delay capacitor group in the power-on spike voltage suppression module 3, namely capacitors C113*, C114*, C115*, and C116*, begins to charge. After charging is completed, PMOS transistors V3 and V4 are turned on. The second delay capacitor group, namely capacitors C105, C106, C107, and C108, begins to charge. After charging is completed, the source of PMOS transistor V1 is powered on, turning on the gate and source of PMOS transistor V1. PMOS transistor V1 slowly turns on and operates in the linear region.

[0050] The emitter of optocoupler D2 transmits current to the gate of NMOS transistor V2 through resistors R13 and R2, turning on the gate and source of NMOS transistor V2. NMOS transistor V2 then slowly turns on and operates in the linear region.

[0051] In the above process, the power-on time of PMOS transistor V1 is much longer than the charging time of the gate-source parasitic capacitance. The voltage across the overcurrent protection resistor R4 is less than 1V and the current is less than 100mA. This can suppress the power-on voltage and current spikes, avoid accidental activation of pyrotechnic devices, and significantly improve the safety and reliability of the ignition circuit, effectively ensuring the success of the test and the safety of the test personnel.

[0052] In addition, this embodiment has designed a PCB board according to the circuit design, shortened the wiring length to reduce parasitic resistance and capacitance, thereby avoiding the impact of the PCB board layout on the performance and reliability of the circuit, preventing crosstalk and latch-up effect of MOSFETs in the circuit, and preventing high-frequency changes of some devices.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. An integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage, comprising an ignition circuit (1) and a VCC power supply (2), wherein the output terminal of the ignition circuit (1) generates a voltage difference for igniting pyrotechnic items; characterized in that: It also includes a power-on spike voltage suppression module (3) located between the VCC power supply (2) and the ignition circuit (1); The ignition circuit (1) includes optocoupler D1, optocoupler D2, PMOS transistor V1 and NMOS transistor V2; The positive terminal of the VCC power supply (2) is connected to the input terminal of the power-on spike voltage suppression module (3), and the negative terminal is grounded; the output terminal of the power-on spike voltage suppression module (3) is simultaneously connected to the source of PMOS transistor V1 and the high-end output of optocoupler D1, and is connected to the high-end output of optocoupler D1 through resistor R11; the high-end output of optocoupler D1 is connected to the gate of PMOS transistor V1 through resistor R1, and the low-end output is grounded; the drain of PMOS transistor V1 is the positive output of the ignition circuit (1); The low-end output of the optocoupler D2 is grounded in sequence through resistors R13 and R14, and connected to the gate of NMOS transistor V2 through resistor R2. The source of NMOS transistor V2 is grounded, and the drain is the negative output of the ignition circuit (1). The high-end inputs of the optocouplers D1 and D2 are used to connect to an external 5V power supply, and the low-end inputs receive control commands to control the ignition circuit (1) to work. The power-on spike voltage suppression module (3) includes PMOS transistors V3 and V4, resistors R106 and R108. One end of resistor R106 is connected to the positive terminal of the VCC power supply (2), and the other end is connected to one end of resistor R108. The other end of resistor R108 is grounded. The sources of PMOS transistors V3 and V4 are connected and serve as the input terminals of the power-on spike voltage suppression module (3), which are connected to the positive terminal of the VCC power supply (2). The gate of PMOS transistor V3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to resistor R108. One end of R108 is connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of resistor R108. Soft-start time control resistors are connected in series between the other ends of resistors R5 and R6 and one end of resistor R108. A first delay capacitor bank is connected in parallel between the source of PMOS transistors V3 and V4 and the other ends of resistors R5 and R6, used to charge and discharge PMOS transistors V3 and V4 before power-on, so that PMOS transistors V3 and V4 are slowly turned on. The drains of PMOS transistors V3 and V4 are connected and connected to the source of PMOS transistor V1 as the output terminal of the power-on spike voltage suppression module (3).

2. The integrated electronic device pyrotechnic ignition circuit capable of suppressing power-on spike voltage according to claim 1, characterized in that: The soft-start time control resistor includes resistors R110* and R111* connected in parallel. The resistance values ​​of resistors R110* and R111* can be adjusted according to usage requirements to adjust the power-on time of PMOS transistors V3 and V4.

3. The ignition circuit for pyrotechnic devices in an integrated electronic device capable of suppressing power-on spike voltage, as described in claim 1, is characterized in that: The first delay capacitor group includes capacitors C115* and C116* connected in series between the source of PMOS transistor V3 and the other end of resistor R5, and capacitors C113* and C114* connected in series between the source of PMOS transistor V4 and the other end of resistor R6.

4. The ignition circuit for pyrotechnic devices in an integrated electronic device capable of suppressing power-on spike voltage as described in any one of claims 1-3, characterized in that: A second delay capacitor bank is connected between the drain terminals of PMOS transistors V3 and V4 and ground. This bank is used to charge and discharge PMOS transistor V1 before it is powered on, thereby further delaying the power-on time of PMOS transistor V1.

5. The ignition circuit for pyrotechnic devices in an integrated electronic device capable of suppressing power-on spike voltage, as described in claim 4, is characterized in that: The second delay capacitor group includes capacitors C105, C106, C107, and C108. One end of capacitor C105 is connected to one end of capacitor C106, and one end of capacitor C107 is connected to one end of capacitor C108. The other ends of capacitors C105 and C107 are connected to the drains of PMOS transistors V3 and V4, respectively. The other ends of capacitors C106 and C108 are grounded.

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