Precise synchronous control method and system for high-voltage frequency converter based on multiprocessor architecture

Abstract

The invention relates to the technical field of power electronic control, and discloses a high-voltage frequency converter precise synchronous control method and system based on a multiprocessor architecture, and the method comprises the steps: introducing a field programmable gate array with precise hardware logic in a communication link as a time base master station, and designing a global synchronous frame and delay compensation algorithm, thereby achieving the precise synchronous control of a high-voltage frequency converter. The technical effect of realizing microsecond-level phase synchronization of the PWM carrier waves of dozens of power units in a heterogeneous processor and asynchronous communication environment is achieved.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, specifically to a precise synchronous control method for a multi-processor (DSP+FPGA and STM32) architecture for a multi-unit cascaded multi-level high-voltage frequency converter. Background Technology

[0002] In a multi-unit cascaded high-voltage frequency converter, the main controller is responsible for voltage vector calculation, while multiple subordinate power unit controllers are responsible for generating pulse width modulation (PWM) drive signals. To ensure the quality of the output voltage waveform, the PWM carriers of all units must be strictly synchronized, typically requiring a phase deviation of less than 1 microsecond.

[0003] In traditional solutions, the main controller and unit controllers often use processors from the same series or with synchronized clocks (such as multiple DSPs of the same model), achieving synchronization through a shared clock source or a high-speed parallel bus (such as the DSP's XINTF and the FPGA bus). However, in scenarios with strict cost or resource constraints, the system may adopt a heterogeneous architecture. For example, the main controller might use a high-performance 150MHz digital signal processor (DSP), while the unit controller might use a lower-cost 72MHz ARM microcontroller (such as the STM32F105). Both use independent crystal oscillators, resulting in a frequency deviation of ±100ppm. Furthermore, to improve anti-interference capabilities, instructions must be transmitted via optical fiber, whose inherent transmission delay (typically approximately 200-500 nanoseconds per channel) and protocol processing time introduce uncertain delays.

[0004] The two factors mentioned above—the cumulative frequency offset of the independent clock source and the uncertain delay of the communication link—will cause the PWM carrier phase of each unit to gradually drift. At the carrier frequency (f... carrier The range is from several hundred to several kHz, and f carrier =1 / T carrier In typical applications where the system contains dozens of units, a phase deviation of several microseconds can occur within just 10 milliseconds. This loss of synchronization will directly cause distortion of the synthesized output voltage waveform, and the total harmonic distortion rate may increase by 3%-5%, which in turn will cause motor torque pulsation, additional motor heating and noise, seriously threatening the safe and stable operation of the load equipment.

[0005] Therefore, existing technologies lack effective means to achieve high-precision synchronization of multi-unit PWM carriers under low-cost heterogeneous processor architecture and asynchronous serial communication conditions, and there is an urgent need for a new control method that can simultaneously compensate for clock differences and communication delays. Summary of the Invention

[0006] The present invention aims to overcome the shortcomings of the prior art and provide a precision synchronous control method and system for high voltage frequency converters based on a multi-processor architecture. It has the technical effect of achieving microsecond-level phase synchronization of PWM carriers of dozens of power units in a heterogeneous processor and asynchronous communication environment.

[0007] The core concept of this invention lies in the global hardware synchronization mechanism and the closed-loop delay measurement and compensation mechanism, which are described below:

[0008] (1) Global hardware synchronization mechanism

[0009] Leveraging the parallel and deterministic hardware timing characteristics of the FPGA, it serves as the "time base master" for the entire system, periodically broadcasting global synchronization frames with special identifiers. Each unit controller identifies the frame through hardware input capture and uses this hardware event as a reference to forcibly reset its local PWM carrier counter, eliminating the cumulative phase drift caused by minute differences in clock frequency at its source.

[0010] The hardware triggering and initialization configuration adopts a layered and progressive modular design, strictly following the configuration sequence from the hardware layer to the software layer to ensure the correct initialization and dependencies of each module. By establishing an end-to-end direct connection architecture of fiber optic reception → edge detection → hardware triggering, coupled with a dedicated hardware trigger source and nanosecond-level edge detection mechanism, precise and exclusive responses to synchronous events are achieved. Interrupt configuration uses the highest system priority, ensuring zero-latency automatic hardware triggering while supporting precise interrupt nesting control. The timer simultaneously serves as a time base and PWM generator; all parameters are pre-configured and stored, supporting rapid startup and stable operation. This process possesses complete closed-loop verification, step-by-step fault tolerance, parallel configuration, and dynamic adjustability capabilities, realizing a fundamental shift in design paradigms from experience-based configuration to systematic configuration, from manual operation to automated processes, and from static settings to dynamic optimization. It provides a reliable, efficient, and scalable hardware configuration solution for industrial-grade embedded systems.

[0011] The interrupt triggering mechanism constructs a complete deterministic signal link from the physical layer to the logic layer. Employing a unidirectional, feedback-free forward propagation mechanism, it achieves an extremely low end-to-end latency of less than 500 nanoseconds and jitter of less than 10 nanoseconds through only three minimal hardware steps. This mechanism configures a dedicated hardware channel for synchronization signals, ensuring the exclusivity and fastest response of interrupt triggering through hardware-level event priority processing and direct mapping without arbitration. Hardware-level de-jittering and multi-event acknowledgment mechanisms guarantee trigger reliability, while the clear division of responsibilities between hardware and software fully leverages their respective advantages. This design follows the principles of hardware priority and determinism over flexibility, realizing the theoretically shortest path from event detection to interrupt response. It provides predictable performance guarantees for real-time systems and transfers complex time-sensitive tasks from software to hardware, laying a solid foundation for highly reliable real-time control.

[0012] (2) Closed-loop delay measurement and compensation mechanism

[0013] The FPGA actively measures the entire loop delay from the issuance of the master control command to the response of the unit controller, and advances the corresponding time amount when sending the duty cycle command next time, thereby compensating for communication and processing delays, ensuring that all units execute the new PWM duty cycle at the same theoretical time, and avoiding waveform distortion caused by inconsistent command execution time.

[0014] To achieve the above objectives, the present invention adopts the following technical solution: a precision synchronous control method and system for a high-voltage frequency converter based on a multi-processor architecture, applied to a high-voltage frequency converter system including a main controller, a time base master module, and at least one power unit controller; the main controller is connected to the time base master module, and the time base master module is connected to each power unit controller via a communication link; characterized in that the method includes the following steps:

[0015] Step 1: Time base synchronization. The time base master module periodically generates and broadcasts global synchronization frames; the power unit controller detects the falling edge of the global synchronization frame through the input capture function of its hardware timer and generates a hardware interrupt; in response to the interrupt, the power unit controller immediately resets its internal PWM triangular carrier counter, so that the carrier phase of all power unit controllers is zero-aligned.

[0016] Step 2: Delay Measurement and Compensation. After the main controller sends the PWM duty cycle command to the time base master module, the time base master module executes:

[0017] Step 2.1: Add a first timestamp T1 to the PWM duty cycle command and send it to the target power unit controller via the communication link.

[0018] Step 2.2: Receive an acknowledgment feedback packet from the target power unit controller for the PWM duty cycle command. This feedback packet contains a second timestamp T2, which is the local time when the power unit controller receives the command and begins processing.

[0019] Step 2.3: Based on T1, T2, and the processing delay T of the time base master module itself. fpga and the fixed transmission delay T of the communication link fiber Calculate the total response delay T of the power unit controller. delay .

[0020] Step 2.4: Based on the calculated T delay and the instruction processing delay T of the power unit controller mcu Determine the advance sending time T of the instruction. advance When sending subsequent instructions, advance the time by T. advance Time transmission ensures that the power unit controller executes at the desired theoretical execution time T. execute Receive and execute the instruction.

[0021] Preferably, the total response delay T in step S2.3 delay The calculation formula is as follows:

[0022] T delay = (T2 - T1) +T fpga + 2×T fiber

[0023] In the formula, T fiber For the unidirectional transmission delay of a single optical fiber, 2×T fiber It includes bidirectional fiber optic delay for both command issuance and confirmation feedback.

[0024] Preferably, the instruction advance sending time T in step S2.4 is... advance The calculation formula is:

[0025] T advance = T delay + T mcu

[0026] In the formula, T mcu The fixed software processing time for the power unit controller from receiving an instruction to updating it to the PWM comparator register can be obtained through offline measurement.

[0027] Building upon the aforementioned precise synchronization control, this invention further enhances system health status monitoring, fault diagnosis and classification, and adaptive synchronization strategy switching functions. When the system detects partial unit failure, fiber optic link anomalies, or clock source drift exceeding limits, it can automatically degrade from "high-precision full synchronization mode" to "high-reliability group synchronization mode" or "basic frequency synchronization mode," ensuring that the system can maintain basic synchronous operation even under fault conditions. This prevents the entire inverter from shutting down, significantly improving system availability and reliability. Specifically, the following steps are included:

[0028] Step 3.1: Real-time monitoring of system health status. This system monitors the fiber optic link (signal strength, bit error rate, and round-trip delay stability), each unit controller (operating status, memory verification, and PWM output), and the clock source (primary and backup clock frequency deviation) in real time, and comprehensively quantifies and generates a unified health score H. score (Value range: 0-100), the scoring criteria include key indicators such as bit error rate, latency jitter, and heartbeat timeliness, enabling a refined assessment of the status of the system's core components. A health score H is defined for the aforementioned objects. score (Value range: 0-100). For example, the lower the bit error rate, the smaller the latency jitter, and the more accurate the heartbeat packets, the higher the health score H. score The higher the value, the better.

[0029] Step 3.2: Fault Diagnosis and Classification. This system implements a three-level fault classification mechanism: Level 1 (mild) faults are determined to be local link interference or mild unit anomalies, manifested as excessive communication delays or abnormal heartbeats in individual units; Level 2 (moderate) faults are determined to be regional communication failures or master clock anomalies, manifested as multiple units in the same region losing connection or excessive master clock drift; Level 3 (severe) faults are determined to be central control link or time base station failures, manifested as interrupted communication between the FPGA and the main control DSP or loss of global synchronization frames.

[0030] Step 3.3: Adaptive Synchronization Strategy Switching. The system has three built-in adaptive synchronization strategies and automatically switches according to the fault level: The default strategy A (full-precision synchronization mode) performs full high-precision synchronization when the system is healthy; when a level I or II fault occurs, strategy B (group synchronization mode) is activated, the FPGA groups healthy units and assigns a sub-master station, and hardware synchronization within the group is achieved through the PWM signal of the sub-master station, while soft synchronization is maintained between groups through the FPGA, thereby isolating the fault and maintaining the synchronization of most units; when a level III severe fault occurs, strategy C (basic frequency synchronization mode) is activated, the FPGA switches to the backup clock and broadcasts a simplified frequency reference frame, each unit only calibrates the output frequency and abandons phase alignment, ensuring that the system output frequency is basically consistent when the central control fails, preventing equipment damage and buying time for safe handling.

[0031] Step 3.4: Status Reporting and Recovery. The FPGA reports the system health status, fault level, and current synchronization strategy to the top-level DSP in real time. When the fault is detected and confirmed after a stable observation period, the system automatically recovers to the high-precision synchronization mode step by step, from strategy C (basic frequency synchronization) to strategy B (group synchronization) and then to strategy A (full-precision synchronization).

[0032] The present invention also provides a control system for implementing the above method, comprising:

[0033] (1) The main controller is used to execute the voltage vector control algorithm and calculate the PWM duty cycle command required by each power unit.

[0034] (2) The time base master module is connected to the main controller and is used to receive PWM duty cycle instructions, execute time base synchronization steps and delay measurement and compensation steps, and complete the timestamp marking of instructions, synchronization frame generation, delay calculation and instruction advance transmission.

[0035] Preferably, the time base station module is implemented by an FPGA, the core of the power unit controller is implemented by an ARM microcontroller, and the core of the main controller is implemented by a DSP.

[0036] The time base station also includes a health status monitoring module, a fault diagnosis module, and a mode switching module. The health status monitoring module is used to monitor the health status of the fiber optic link, each power unit controller, and its own clock source in real time. The fault diagnosis module is used to classify and diagnose system faults based on the monitoring data. The mode switching module is used to control the system to switch between full-precision synchronization mode, group synchronization mode, and basic frequency synchronization mode based on the output of the fault diagnosis module.

[0037] (3) Multiple power unit controllers, each connected to the time base master module via an independent fiber optic link, each power unit controller including:

[0038] 1) Hardware timer, used to generate PWM triangular carrier waves.

[0039] 2) Input capture unit, whose input capture channel is directly connected to the data output pin of the fiber optic receiver chip, is used to capture the start edge of the global synchronization frame and trigger an interrupt.

[0040] 3) The PWM generator resets the hardware timer counter in the interrupt service routine to achieve carrier synchronization.

[0041] (4) Fiber optic communication network, connected between the time base station module and each power unit controller.

[0042] The beneficial effects of this invention are:

[0043] (1) Achieve hardware-level high-precision synchronization and determinism and compensation

[0044] A global frame synchronization mechanism based on FPGA hardware timing and STM32 input capture interrupts achieves nanosecond-level PWM carrier phase synchronization, fundamentally eliminating the cumulative drift of heterogeneous clock sources. Through closed-loop delay measurement and dynamic advance compensation, communication and processing delays are automatically offset, ensuring the strict simultaneous execution of control commands from multiple units. Moreover, the entire process is based on hardware event triggering, unaffected by software scheduling, and possesses extremely strong real-time performance and anti-interference capabilities.

[0045] (2) Possesses multi-level fault tolerance and adaptive reconfiguration capabilities

[0046] The system not only possesses high-precision synchronization capabilities but also implements a multi-level adaptive degradation strategy, from "full-precision synchronization" to "group synchronization" and then to "basic frequency synchronization," through health status monitoring and a three-level fault diagnosis mechanism. It can maintain basic system synchronization under various fault scenarios, including local unit anomalies, regional communication failures, and even central control failures, achieving "never completely losing synchronization" and greatly improving system availability and resilience. Faulty units are effectively isolated to prevent fault propagation and ensure the stable operation of the main system.

[0047] (3) The system has strong compatibility and supports state awareness and predictive maintenance.

[0048] This synchronous architecture does not have strong coupling requirements for the specific models and frequencies of the main control DSP and the unit MCUs, making it suitable for distributed systems composed of heterogeneous processors and enhancing the flexibility of system design. Meanwhile, comprehensive health status monitoring provides a data foundation for predictive maintenance, facilitating the early detection of potential faults and enabling a shift from reactive to proactive maintenance.

[0049] In summary, this invention not only solves the problem of precise synchronization in heterogeneous distributed systems during high-performance operation, but also ensures the survivability and continuous operation capability of the system under abnormal and fault conditions, achieving a leap from simple performance optimization to system resilience construction, and has outstanding inventiveness, practicality and reliability. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the architecture of the high-voltage frequency converter precision synchronous control system of the present invention.

[0052] Figure 2 This is a timing diagram of the global synchronization frame of the present invention.

[0053] Figure 3 This is a schematic diagram of the protocol frame format.

[0054] Figure 4 This is a schematic diagram of the delay measurement and compensation timing of the present invention.

[0055] Figure 5 This is a detailed flowchart of the delay measurement and compensation method of the present invention.

[0056] Figure 6 This is a flowchart of the main interrupt service routine for the power unit controller of the present invention.

[0057] Figure 7 This is a flowchart of the hardware triggering and initialization configuration process of the present invention.

[0058] Figure 8 This is a schematic diagram of the interrupt triggering mechanism of the present invention. Detailed Implementation

[0059] The technical solution of the present invention will now be clearly and completely described with reference to specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0060] The core highlight of this invention lies in its innovative architecture and precise implementation: it proposes a three-in-one hardware-level architecture of "centralized time base broadcasting + hardware capture + carrier reset" to specifically address the PWM carrier synchronization loss problem caused by clock differences in heterogeneous processors and fiber optic communication delays; simultaneously, by centralizing time base generation on an FPGA with deterministic timing characteristics, it eliminates the hidden dangers of inconsistency among multiple clock sources at the source, achieving source control of timing discrepancies; and it upgrades synchronization event recognition from software to hardware input capture, significantly reducing processing latency and improving synchronization response speed. Then, using hardware interrupts as a unified trigger point, it forcibly resets the PWM carrier phase of all units, ultimately achieving instantaneous and global precise alignment, fully guaranteeing synchronization accuracy.

[0061] This invention proposes three solutions, which are described below:

[0062] Method 1: FPGA-based global time base frame generation and broadcasting method

[0063] Step 1.1: Design a periodic timer inside the FPGA, the period of which is the same as the system PWM carrier period (e.g., T). carrier Maintain an integer multiple relationship.

[0064] Step 1.2: Construct a broadcast data frame containing a special synchronization header (e.g., 3 consecutive bytes of 0xFF followed by 1 byte of 0xFE). This synchronization header is designed to ensure the generation of a significant falling edge that can be used for hardware triggering.

[0065] Step 1.3: Using the parallel I / O hardware logic of the FPGA, the generated global synchronization frame is simultaneously sent to all fiber optic transmission channels to ensure that the start time of each channel is consistent.

[0066] Method 2: Synchronization signal identification method based on hardware input capture

[0067] Step 2.1: Configure the input capture channel of the advanced timer (such as TIM1) of each STM32 unit controller, and map its input source directly to the digital output pin of the fiber optic receiver chip.

[0068] Step 2.2: Set the input capture channel to falling edge trigger mode and enable the corresponding capture / interrupt events.

[0069] Step 2.3: The fiber optic received signal is directly transmitted to the timer via the hardware link without CPU intervention. The flag is automatically set and an interrupt is triggered when the falling edge arrives.

[0070] Method 3: Interrupt-triggered global reset method for PWM carrier phase

[0071] Step 3.1: In the STM32 input capture interrupt service routine, execute a single critical instruction: clear the timer counter (CNT) register.

[0072] Step 3.2: The CNT value of this timer is directly used as the time base of the PWM generation unit (such as TIM1). Clearing it will cause the PWM triangular carrier to restart instantaneously and the phase to return to zero.

[0073] Step 3.3: After receiving the falling edge of the same synchronization frame, all units complete their respective carrier resets within a few instruction cycles (microseconds), thereby achieving global phase alignment.

[0074] Therefore, this patent proposes three implementation steps:

[0075] Step 1: System Initialization

[0076] First, FPGA configuration is performed, loading the hardware description logic and initializing the periodic timer and multi-channel fiber optic transmitter. Simultaneously, STM32 configuration is carried out, including initializing the advanced timer to set the PWM carrier frequency (f...). carrier =1 / T carrierThe system configures the input capture channel and associates it with the corresponding GPIO of the optical receiver, sets edge detection, and enables the capture interrupt and sets its priority to the highest level, laying the foundation for synchronous operation of the system.

[0077] Step 2: Synchronous Operation

[0078] After entering the synchronization operation phase, the FPGA will periodically generate and broadcast synchronization frames at the frequency of each PWM cycle; each STM32 will automatically trigger an interrupt by capturing the falling edge of the synchronization header through the input hardware; subsequently, each interrupt service routine will clear the local timer CNT to restart the carrier phase of all units synchronously, thereby achieving phase alignment; in addition, after the synchronization frame is sent, the FPGA will also issue PWM duty cycle instructions (which may include timestamps for delay compensation) to each unit to ensure normal operation of the device.

[0079] Step 3: Closed-loop maintenance

[0080] The closed-loop maintenance phase includes optional enhancements. First, the FPGA dynamically calculates the loop delay by measuring the time difference between the sent command and the received unit confirmation. Then, based on the calculated delay result, subsequent commands are sent in advance by the corresponding time to ensure that all units execute actions accurately at the theoretical time, further optimizing the synchronization effect and ensuring the stable and reliable operation of the system.

[0081] For further description, the following will be explained in conjunction with the accompanying drawings and three embodiments:

[0082] like Figure 1 As shown, the high-voltage frequency converter system in this embodiment includes: a main controller (using a TI TMS320F28335 DSP, 150MHz), a time base master module (using a Lattice LFXP2-17E FPGA), 36 power unit controllers (using STM32F105 ARM MCU, 72MHz), and 36 independent fiber optic communication links. The DSP and FPGA are connected via a high-speed parallel bus, and the FPGA is connected to each STM32 via a pair of optical fibers (one for transmitting and one for receiving).

[0083] Each power unit controller receives synchronization frames and PWM commands from the FPGA and achieves carrier synchronization by capturing hardware interrupts. The FPGA simultaneously receives acknowledgment feedback packets from each unit, forming a closed loop. The final stage outputs of all power units are combined into a high-voltage multi-level PWM waveform.

[0084] Example 1: Global Time Base Synchronization Process

[0085] like Figure 2As shown, the FPGA acts as the time base master station, operating in each PWM carrier cycle (e.g., cycle T). carrier A special global synchronization frame is generated and broadcast from a starting point (with values ​​ranging from hundreds to several kHz). This frame begins with a synchronization header that lasts longer than the data bits (e.g., multiple consecutive '1's followed by a '0'). The falling edge of this '1' to '0' sequence is the synchronization trigger edge.

[0086] like Figure 3 As shown, the global synchronization frame structure consists of: First, a 3-byte synchronization header, serving as the frame's start identifier, with a fixed value of 0xFF 0xFF 0xFE. The "leading 1 + falling edge trigger" means that synchronization is achieved through a transition of consecutive high levels (0xFF) followed by a low level (0xFE). Next is a 4-byte data field, responsible for carrying the actual transmitted service data. Finally, there is a 2-byte timestamp, used to record the frame's generation or transmission time, often used in synchronization or timing management scenarios. Overall, this is a typical synchronous communication frame format, using a fixed synchronization header to identify frame boundaries, and combining the data field and timestamp to achieve effective information transmission.

[0087] On the STM32 side, the input capture channel of its advanced timers (such as TIM1) is directly connected to the data output pin of the fiber optic receiver chip. This channel is configured to be triggered by a falling edge. Once the falling edge of the sync header is captured, the hardware immediately generates a capture / interrupt event.

[0088] like Figure 6 As shown, the STM32 responds to this interrupt by performing a critical operation in its interrupt service routine: writing the counter CNT register of the timer (TIM1) to 0. Since all 36 STM32s perform this operation almost simultaneously (with differences only at the hardware circuit delay level, nanoseconds) under the same hardware event (falling edge of the same synchronization frame), it ensures strict alignment of the PWM triangular carrier start points for all units, eliminating long-term phase drift caused by individual differences in the 72MHz crystal oscillator.

[0089] The core process of global synchronization frames consists of four steps:

[0090] Step 1: Reference Provision. The FPGA 50MHz clock provides a timing reference for the system.

[0091] Step 2: Synchronization Trigger. The FPGA sends a signal with a falling edge via optical fiber to initiate synchronization and transmit frame data.

[0092] Step 3: Signal Acquisition. The STM32 captures the rising edge of the fiber optic signal, identifies the synchronization frame, and triggers reception.

[0093] Step 4: Timing calibration and output. The timer triggers an interrupt to calibrate the timing, and finally the PWM generator outputs a synchronous carrier with the same phase.

[0094] Specifically, the FPGA 50MHz clock serves as the system's fundamental clock source, providing a stable timing reference. The fiber optic transmission signal from the FPGA initiates the synchronization process via a "falling edge trigger point" (low-level transition), with subsequent high and low level changes carrying frame data. The STM32 input capture channel captures the rising edge of the fiber optic signal to identify the boundary of the synchronization frame and trigger frame reception. The timer control logic (reset signal) triggers an interrupt after the synchronization frame is received, used to reset or calibrate subsequent timing logic to ensure synchronization accuracy. The PWM generator output is the final carrier signal, and its "carrier phase zeroing" label reflects the effect of global synchronization—the PWM carriers of all devices maintain phase consistency after synchronization. The overall process is: FPGA sends synchronization frames via fiber optic cable → STM32 captures the signal and triggers synchronization → timer calibrates timing → PWM generator outputs the synchronized carrier, ultimately achieving system-level timing alignment.

[0095] From hardware event triggering to precise synchronization completion: A complete field protection mechanism and the highest priority hardware interrupt ensure nanosecond-level response and system stability. The interrupt service routine is extremely streamlined, retaining only the critical operation of clearing the counter, achieving hardware-level synchronization with zero software overhead. Based on event-driven rather than time-driven approaches, and through instantaneous forced reset rather than gradual adjustment, the atomicity and instantaneity of synchronization are ensured. The hardware path from fiber optic reception to the timer eliminates intermediate links, making interrupt latency fixed and measurable, and execution time deterministic and bounded. All power units respond to the synchronization frame equally, achieving distributed autonomous decision-making and true parallel synchronization, with inter-unit deviations less than 100 nanoseconds. This solution represents a fundamental shift in design paradigms, from software polling to hardware triggering, from complex processing to extreme simplification, from uncertainty to determinism, and from centralized control to distributed autonomy, providing a simplified, high-precision, and highly deterministic synchronization solution for high-reliability real-time control systems.

[0096] The main interrupt service routine employs strict context protection and an extremely streamlined design, completing synchronization within 5 microseconds through a single critical operation (counter reset), achieving deterministic response and zero state accumulation at the software level. The hardware triggering and initialization configuration process, through a layered, progressive, and hardware-first modular configuration strategy, ensures reliable end-to-end initialization from fiber optic reception to system readiness, supporting parallel configuration and dynamic reconfiguration, compressing configuration time to the hundreds of milliseconds level. The interrupt triggering mechanism establishes a fully deterministic hardware link from the physical layer to the logic layer, achieving direct, arbitration-free signal response with sub-microsecond latency and nanosecond jitter, and ensuring event authenticity through hardware-level jitter reduction and multiple verifications. The organic combination of these three elements forms a closed loop of hardware-triggered driving, precise real-time interrupt response, and stable system operation, fundamentally transferring time-sensitive tasks from software to hardware. The deterministic hardware advantages guarantee high-precision synchronization and long-term reliable operation of the distributed system.

[0097] Example 2: Delay Measurement and Compensation Process

[0098] like Figure 5 As shown, this process is a closed-loop measurement and prediction compensation process.

[0099] Step 1: Command Issuance and Timestamp Recording. The DSP calculates the duty cycle command and sends it to the FPGA. At time t1 (first timestamp T1), the FPGA loads the command into a transmission frame and sends it to the designated STM32 via optical fiber. The one-way fixed transmission delay of the optical fiber is T. fiber (Approximately tens to hundreds of nanoseconds, measurable).

[0100] Step 2: Instruction Reception and Feedback. At time t2 (local time, second timestamp T2), the STM32 receives the complete instruction frame via serial port. Subsequently, the STM32 does not immediately update the PWM; instead, it first packages the T2 value into an acknowledgment feedback packet and sends it back to the FPGA via another optical fiber. Simultaneously, the STM32 begins preparing to apply the instruction; its fixed software processing time (from parsing to writing to the compare register) is T. mcu .

[0101] Step 3: Delay Calculation. The FPGA receives the acknowledgment packet at time t3. The FPGA internally knows its own encoding and decoding processing time T. fpga The total loop delay T from when the FPGA issues the instruction to when the STM32 begins processing it is... delay for:

[0102] T delay = (T2 - T1) + T fpga + 2 ×T fiber

[0103] This formula takes into account the bidirectional fiber delay for command issuance and acknowledgment return.

[0104] Step 4: Send compensation in advance. Assume the DSP expects all units to execute at some theoretical future time T. execute (Typically aligned with the period or midpoint of the PWM carrier) PWM duty cycle is updated uniformly. To enable STM32 to perform T... execute The FPGA needs to send instructions in advance so that the processing is completed and the new duty cycle takes effect at the exact moment.

[0105] Considering that STM32 requires T mcu The total time T for processing, therefore instructions should be prepared in advance. advance for:

[0106] T advance = T delay + T mcu

[0107] Therefore, the FPGA will be in T execute - T advance At this moment, the duty cycle command for this unit is issued. After T delay After the time transmission and processing delay, the STM32 happens to be at T execute - T mcu Receive instructions at all times, and then pass through T mcu The processing was exactly at T execute The PWM register is updated in real time, which achieves precise synchronization of instruction execution across all units.

[0108] This solution employs a closed-loop adaptive control mechanism of "measurement-calculation-compensation." By establishing dual time bases for both theoretical and actual execution times, it precisely decomposes the total delay into transmission and processing delays, thereby achieving a fundamental shift from passive waiting to proactive prediction. This mechanism, for the first time, uses feedforward predictive compensation to transform uncertainties in fiber optic transmission and protocol processing into deterministic lead times, bringing the deviation between the compensated instruction execution time and the theoretical time close to zero, achieving synchronization accuracy at the microsecond or even nanosecond level. Combined with FPGA hardware synchronization and delay compensation software algorithms, this solution provides dual protection, eliminating clock drift and communication delays while significantly improving long-term system stability while ensuring real-time performance. It possesses anti-interference and anti-drift capabilities, automatically adapting to environmental changes, and is particularly suitable for complex distributed industrial systems with multiple nodes, long distances, and heterogeneous processors. This represents a technological paradigm breakthrough from open-loop blind transmission to closed-loop intelligence, and from coarse synchronization to precise alignment.

[0109] The key formulas and variable descriptions are summarized in Table 1.

[0110] Variable symbol meaning Typical Unit <![CDATA[T carrier ]]> PWM triangular carrier period μs <![CDATA[T1]]> Absolute timestamp of FPGA command transmission μs or clock cycles <![CDATA[T2]]> STM32 receives instruction local timestamp μs or clock cycles <![CDATA[T fiber ]]> One-way transmission delay of a single optical fiber ns <![CDATA[T fpga ]]> FPGA internal protocol handles fixed delay ns <![CDATA[T mcu ]]> Fixed software time for STM32 instruction processing μs <![CDATA[T delay ]]> Total delay from instruction being issued by the FPGA to the STM32 starting to process it μs <![CDATA[T advance ]]> The amount of instructions sent in advance to compensate for the delay μs <![CDATA[T execute ]]> Theoretically, the unified execution time of instructions μs

[0111] Table 1. Summary of Key Formulas and Variables

[0112] This innovative solution employs a two-stage execution strategy of measurement followed by compensation. It utilizes the dual timestamps of FPGA and STM32 to achieve precise delay quantization and performs feedforward predictive compensation based on historical data, effectively avoiding the lag problem of traditional feedback control. The process path is fixed and repeatable, combining real-time synchronization and batch compensation, balancing determinism and adaptability. Its built-in continuous cyclic compensation mechanism further ensures the system's fault tolerance and self-recovery capabilities. Through the collaborative design of hardware implementation of key timing parameters and software processing of complex algorithms, this solution achieves optimal resource allocation and long-term stable operation while ensuring microsecond-level response and nanosecond-level synchronization accuracy. It embodies a fundamental shift in design philosophy from experience-based design to model-driven design, from static configuration to dynamic optimization, and from single-point improvement to system-wide collaboration, providing a reliable, scalable, and high-performance synchronization control paradigm for multiprocessor distributed systems.

[0113] Continuing, based on the two embodiments mentioned above (global hardware synchronization and delay measurement compensation), an embodiment focusing on "multi-level fault diagnosis and adaptive degradation synchronization" is added. This embodiment demonstrates the robustness, fault tolerance, and intelligence of the method.

[0114] Example 3: Multi-level Fault Diagnosis and Adaptive Degradation Synchronization Method

[0115] This embodiment, based on the aforementioned precise synchronization control, adds system health status monitoring, fault diagnosis and classification, and adaptive synchronization strategy switching functions. When the system detects partial unit failure, fiber optic link anomaly, or clock source drift exceeding limits, it can automatically downgrade from "high-precision full synchronization mode" to "high-reliability group synchronization mode" or "basic frequency synchronization mode," ensuring that the system can still maintain basic synchronous operation under fault conditions, avoiding the shutdown of the entire frequency converter, and greatly improving the availability and reliability of the system. The specific implementation method is described below:

[0116] Step 3.1: Real-time monitoring of system health status. This system monitors the fiber optic link (signal strength, bit error rate, and round-trip delay stability), each unit controller (operating status, memory verification, and PWM output), and the clock source (primary and backup clock frequency deviation) in real time, and comprehensively quantifies and generates a unified health score H. score (Value range: 0-100), the scoring criteria include key indicators such as bit error rate, latency jitter, and heartbeat timeliness, enabling a refined assessment of the status of the system's core components. A health score H is defined for the aforementioned objects. score (Value range: 0-100). For example, the lower the bit error rate, the smaller the latency jitter, and the more accurate the heartbeat packets, the higher H... scoreThe higher the value, the better.

[0117] Step 3.2: Fault Diagnosis and Classification. This system implements a three-level fault classification mechanism: Level 1 (mild) faults are determined to be local link interference or mild unit anomalies, manifested as excessive communication delays or abnormal heartbeats in individual units; Level 2 (moderate) faults are determined to be regional communication failures or master clock anomalies, manifested as multiple units in the same region losing connection or excessive master clock drift; Level 3 (severe) faults are determined to be central control link or time base station failures, manifested as interrupted communication between the FPGA and the main control DSP or loss of global synchronization frames.

[0118] Step 3.3: Adaptive Synchronization Strategy Switching. The system has three built-in adaptive synchronization strategies and automatically switches between them based on the fault level:

[0119] Strategy A (Full Precision Synchronization Mode): Default mode, applicable to system health score H. score > 90, which refers to the complete process of Examples 1 and 2.

[0120] Strategy B (Group Synchronization / Master-Slave Mode): Activated upon the occurrence of a Level 1 or Level 2 fault, the FPGA re-groups the remaining healthy cells logically. Within each group, the cell with the best health condition is designated as the "sub-master." The FPGA's global synchronization frame is only sent to each "sub-master." Upon receiving the frame, the "sub-master" uses its own intact PWM output as a hardware synchronization signal to directly drive the "input capture" pins of other cells within the same group (via board-level hardware backup lines), achieving hard synchronization within the group. Inter-group synchronization is maintained softly through the FPGA's synchronization frame. This isolates faulty cells or areas, prevents fault propagation, and ensures that most cells maintain high-precision synchronization.

[0121] Strategy C (Basic Frequency Synchronization Mode): Activated upon a Level 3 fault, the FPGA switches to its internal backup oscillator and broadcasts a simplified "frequency reference frame" (containing only basic clock information, without complex timestamps). Each STM32 unit uses this frame to calibrate only its own PWM carrier frequency (by adjusting the timer prescaler), abandoning strict phase alignment. In the extreme case of complete central control failure, this ensures that the fundamental frequency output of all units is essentially consistent, avoiding equipment damage due to large frequency differences and buying time for a safe system shutdown or switch to the backup control scheme.

[0122] Step 3.4: Status Reporting and Recovery. The FPGA reports the system health status, fault level, and current synchronization strategy to the top-level DSP in real time. When the fault is detected and confirmed after a stable observation period, the system automatically recovers to the high-precision synchronization mode step by step, from strategy C (basic frequency synchronization) to strategy B (group synchronization) and then to strategy A (full-precision synchronization).

[0123] This invention has been described through several embodiments. Those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of this invention, modifications can be made to these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention.

Claims

1. A precision synchronous control method for high-voltage frequency converters based on a multi-processor architecture, characterized in that: The process includes a time base synchronization step: a time base master station periodically generates and broadcasts a global synchronization frame; each power unit controller detects the falling edge of the global synchronization frame through the input capture function of its hardware timer and immediately resets its internal PWM triangular carrier counter, so that the carrier phase of all power unit controllers is zeroed and aligned.

2. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 1, characterized in that: It also includes a delay compensation step: the time base master station measures the total loop delay from sending the PWM command to receiving the confirmation feedback from the power unit controller, and calculates the command advance sending time based on the delay and the fixed processing time of the power unit controller; when sending commands in the future, the command is sent in advance by the time mentioned above, so that all power unit controllers receive and execute the command at the expected theoretical execution time.

3. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 2, characterized in that: It also includes fault tolerance steps: real-time monitoring of system health status and fault diagnosis; adaptively switching from full-precision synchronization mode to degraded synchronization mode based on the diagnosed fault level.

4. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 2, characterized in that: The delay compensation step specifically includes: Step 2.1: The time base master station adds a first timestamp T1 to the PWM command and sends it; Step 2.2: Receive an acknowledgment feedback packet from the power unit controller, which includes a second timestamp T2; Step 2.3: Based on T1, T2, and the time base master station, process the delay T. fpga and fiber optic one-way delay T fiber Calculate the total response delay T delay = (T2 - T1) +T fpga + 2×T fiber ; Step 2.4: According to T delay and the instruction processing delay T of the power unit controller mcu Determine the advance sending time T of the instruction. advance = T delay + T mcu .

5. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 3, characterized in that: The fault diagnosis in the fault tolerance process includes three levels: Level 1 fault: determined to be local link interference or minor unit abnormality; Level 2 fault: determined to be a regional communication failure or a master clock malfunction; Level 3 fault: determined to be a fault in the central control link or time base station; The adaptive switching in the fault-tolerant steps includes: When the system is healthy or fault-free, it operates in the full-precision synchronization mode. When a Level 1 or Level 2 fault occurs, switch to group synchronization mode; When a Level 3 fault occurs, switch to basic frequency synchronization mode.

6. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 5, characterized in that: The packet synchronization modes include: Step 5.1: The time base master station re-divides the remaining health power unit controllers into multiple logical groups, and designates the unit with the best health status in each group as a sub-master station; Step 5.2: The time base master station only sends synchronization instructions to each of the sub-master stations; Step 5.3: Each sub-master station uses its own PWM output as a hardware synchronization signal to drive the input capture pins of other units in the same group to achieve hardware synchronization within the group; inter-group synchronization is maintained by the time base master station.

7. The high-voltage frequency converter precision synchronous control method based on a multiprocessor architecture according to claim 5, characterized in that: The basic frequency synchronization mode includes: Step 6.1: The time base master station switches to the internal backup clock source and broadcasts a simplified frequency reference frame; Step 6.2: Each power unit controller adjusts only the frequency of its PWM carrier according to the frequency reference frame, abandoning strict alignment of the carrier phase.

8. A high-voltage frequency converter precision synchronous control system based on a multiprocessor architecture for implementing the method of any one of claims 1-7, characterized in that: include: The main controller is used to calculate the PWM duty cycle command; The time base master station, connected to the main controller, is used to generate global synchronization frames, perform delay measurement and compensation, and perform fault-tolerant control. Multiple power unit controllers are connected to the time base master station via independent fiber optic links. Each power unit controller includes an input capture unit for hardware capture of synchronization frames and a timer for generating PWM. The time base master station is implemented by a field-programmable gate array (FPGA), and the core of the power unit controller is implemented by a microcontroller (MCU).

9. The high-voltage frequency converter precision synchronous control system based on a multiprocessor architecture according to claim 8, characterized in that: The time base master station also includes: The health status monitoring module is used to monitor the health status of the fiber optic link, each power unit controller and its own clock source in real time. The fault diagnosis module is used to classify and diagnose system faults based on monitoring data.

10. The high-voltage frequency converter precision synchronous control system based on a multiprocessor architecture according to claim 9, characterized in that: The time base master station also includes a mode switching module, which controls the system to switch between the full-precision synchronization mode, the group synchronization mode and the basic frequency synchronization mode according to the output of the fault diagnosis module.

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