Power stage electrostatic discharge protection circuit and power drive chip

Abstract

This application provides a power-level electrostatic discharge (ESD) protection circuit and a power driver chip. The circuit includes a first drive control module, a first coupling adjustment module, a first switch module, a second drive control module, a second coupling adjustment module, and a second switch module. The first coupling adjustment module is electrically connected to both the first drive control module and the first switch module, and the second coupling adjustment module is electrically connected to the second drive control module, the second switch module, and the first switch module. The power-level ESD protection circuit provided in this application eliminates the need for dedicated ESD devices at the input voltage port and intermediate nodes. Instead, it achieves ESD energy discharge by coordinating the switching module's conduction through the coordinated control of each module. This reduces the occupied area of ​​the chip's active region and layout, thus shrinking the overall chip size. Simultaneously, it eliminates the design, manufacturing, and integration costs of independent ESD devices, effectively reducing the chip's R&D and mass production costs.

Description

Technical Field

[0001] This application belongs to the field of power driver chip technology, and particularly relates to a power stage electrostatic discharge protection circuit and a power driver chip. Background Technology

[0002] In the power stage design of power driver chips, ESD (Electrostatic Discharge) is one of the key risk factors leading to chip failure. Therefore, ESD protection is a core component for ensuring chip reliability. Current technologies commonly employ separate ESD devices at critical ports such as the VIN and SW pins for ESD protection. These devices conduct upon encountering an ESD event, providing a discharge path for electrostatic energy and preventing damage to internal functional circuits. However, to meet the chip's required ESD discharge capacity and latch-up resistance, these separate ESD devices often need to be large in size, consuming significant chip area. Summary of the Invention

[0003] This application provides a power-level electrostatic discharge protection circuit and a power drive chip, which can solve the problem of existing independent ESD devices consuming a large chip area.

[0004] In a first aspect, embodiments of this application provide a power-level electrostatic discharge protection circuit, including a first drive control module, a first coupling adjustment module, a first switch module, a second drive control module, a second coupling adjustment module, and a second switch module. The first coupling adjustment module is electrically connected to the first drive control module and the first switch module, respectively, and the second coupling adjustment module is electrically connected to the second drive control module, the second switch module, and the first switch module, respectively.

[0005] When an ESD event occurs in the input voltage, the first drive control module outputs a first voltage according to a first drive signal and a first control signal; the first coupling adjustment module adjusts the first voltage so that the difference between the first voltage and the input voltage is greater than a first preset value, and the first switch module is turned on; the second drive control module outputs a second voltage according to a second drive signal and a second control signal; the second coupling adjustment module adjusts the second voltage so that the difference between the second voltage and ground is greater than a second preset value, and the second switch module is turned on.

[0006] In one possible implementation of the first aspect, after the input voltage ESD event ends, the first coupling adjustment module is used to pull the first voltage up to the input voltage, thereby turning off the first switching module; the second coupling adjustment module is used to pull the second voltage down to ground, thereby turning off the second switching module.

[0007] In one possible implementation of the first aspect, the first control signal is the inverted signal of the second control signal.

[0008] In one possible implementation of the first aspect, the first drive control module includes a first switch, a second switch, and a third switch. The gates of the first and third switches are both used to receive the first drive signal. The source of the first switch is used to receive the input voltage. The drain of the first switch is electrically connected to the source of the second switch. The gate of the second switch is used to receive the first control signal. The drain of the second switch is electrically connected to the drain of the third switch, the first coupling adjustment module, and the first switch module, respectively. The source of the third switch is grounded.

[0009] In one possible implementation of the first aspect, the first coupling adjustment module includes a first resistor and a first capacitor. A first end of the first resistor is used to receive the input voltage. A second end of the first resistor is electrically connected to a first end of the first capacitor, the first drive control module, and the first switch module, respectively. A second end of the first capacitor is electrically connected to the first switch module, the second switch module, and the second coupling adjustment module, respectively.

[0010] In one possible implementation of the first aspect, the second drive control module includes a fourth switch, a fifth switch, and a sixth switch. The gates of the fourth and sixth switches are both used to receive the second drive signal. The source of the fourth switch is used to receive the input voltage. The drain of the fourth switch is electrically connected to the drain of the fifth switch, the second coupling adjustment module, and the second switching module, respectively. The gate of the fifth switch is used to receive the second control signal. The source of the fifth switch is electrically connected to the drain of the sixth switch, and the source of the sixth switch is grounded.

[0011] In one possible implementation of the first aspect, the second coupling adjustment module includes a second resistor and a second capacitor. The first terminal of the second capacitor is electrically connected to the first switching module, the second switching module and the first coupling adjustment module, respectively. The second terminal of the second capacitor is electrically connected to the first terminal of the second resistor, the second switching module and the second drive control module, respectively. The second terminal of the second resistor is grounded.

[0012] In one possible implementation of the first aspect, the first switching module includes a first power transistor, the gate of which is electrically connected to the first drive control module and the first coupling adjustment module, the source of which is used to receive the input voltage, and the drain of which is electrically connected to the first coupling adjustment module, the second switching module and the second coupling adjustment module.

[0013] In one possible implementation of the first aspect, the second switching module includes a second power transistor, the gate of which is electrically connected to the second drive control module and the second coupling adjustment module, the drain of which is electrically connected to the first switching module, the second switching module and the second coupling adjustment module, and the source of which is grounded.

[0014] Secondly, embodiments of this application provide a power drive chip, including the power stage electrostatic discharge protection circuit described in any one of the first aspects.

[0015] The beneficial effects of the embodiments in this application compared with the prior art are: The power-level electrostatic discharge protection circuit provided in this application includes a first drive control module, a first coupling adjustment module, a first switching module, a second drive control module, a second coupling adjustment module, and a second switching module. When an ESD event occurs at the input voltage, the input voltage rises rapidly. The first drive control module receives a first drive signal and a first control signal, and outputs a first voltage based on these signals. The first coupling adjustment module dynamically adjusts the first voltage to ensure that the difference between the first voltage and the input voltage is greater than a first preset value, thus ensuring that the first switching module is turned on. After the first switching module is turned on, the voltage at the intermediate node between the first and second switching modules rises rapidly. Simultaneously, the second drive control module receives a second drive signal and a second control signal, and outputs a second voltage based on these signals. The second coupling adjustment module dynamically adjusts the second voltage to ensure that the difference between the second voltage and ground is greater than a second preset value, thus ensuring that the second switching module is turned on. Ultimately, the ESD energy forms a complete discharge path through the turned-on first and second switching modules, achieving effective protection of the circuit. Therefore, compared to existing technologies that rely on additional independent ESD devices for protection, this application eliminates the need for dedicated ESD devices at the input voltage port and intermediate nodes. Instead, it achieves ESD energy discharge by coordinating the switching module's conduction across various modules. This reduces the occupied area of ​​the chip's active region and layout, thus shrinking the overall chip size. Furthermore, it eliminates the design, manufacturing, and integration costs of independent ESD devices, effectively lowering the chip's R&D and mass production costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a block diagram of an existing power-level electrostatic discharge protection circuit; Figure 2 This is a circuit diagram of an existing power-level electrostatic discharge protection circuit; Figure 3 This is a schematic block diagram of a power stage electrostatic discharge protection circuit provided in an embodiment of this application; Figure 4 This is a circuit connection diagram of a power stage electrostatic discharge protection circuit provided in an embodiment of this application.

[0018] In the figure, 101 is the first drive control module; 102 is the first coupling adjustment module; 103 is the first switch module; 104 is the second drive control module; 105 is the second coupling adjustment module; and 106 is the second switch module. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0023] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0025] In existing technologies, to address the challenges of ESD, chips primarily employ ESD protection devices and adjustable RC clamps for internal protection. For example... Figure 1 As shown, an ESD device is placed inside the chip. When the ESD spike exceeds the trigger voltage of the ESD device, the device activates, providing ESD current discharge capability. This dissipates the ESD energy and protects the internal functional circuitry of the chip.

[0026] Adjustable RC clamping detects ESD transient pulses through an RC circuit and controls the discharge current of a large-size MOSFET. The circuit structure is relatively complex and requires integrated detection logic. By dynamically adjusting the threshold, power consumption is reduced while maintaining ESD performance. The challenge lies in effectively distinguishing between ESD events and normal operating voltage spikes to prevent leakage problems caused by false triggering during normal chip operation.

[0027] Figure 2This is a common ESD protection method for power chips, where an ESD device is placed at the VIN pin to protect the internal circuitry. When an ESD event occurs at the VIN pin, the ESD device at VIN conducts, dissipating the ESD energy. Sometimes, it is necessary to add an ESD device to the SW pin. This type of ESD device conducts when an ESD event occurs, providing a discharge path for electrostatic energy and thus preventing damage to internal functional circuitry. However, to meet the chip's required ESD discharge capability and latch-up resistance, these standalone ESD devices often need to be relatively large, consuming a significant amount of chip space.

[0028] To address the aforementioned issues, the power-level electrostatic discharge (ESD) protection circuit provided in this application includes a first drive control module, a first coupling adjustment module, a first switching module, a second drive control module, a second coupling adjustment module, and a second switching module. When an ESD event occurs at the input voltage, the input voltage rises rapidly. The first drive control module receives a first drive signal and a first control signal, and outputs a first voltage based on these signals. The first coupling adjustment module dynamically adjusts the first voltage to ensure that the difference between the first voltage and the input voltage is greater than a first preset value, thus ensuring that the first switching module is turned on. After the first switching module is turned on, the voltage at the intermediate node between the first and second switching modules rises rapidly. Simultaneously, the second drive control module receives a second drive signal and a second control signal, and outputs a second voltage based on these signals. The second coupling adjustment module dynamically adjusts the second voltage to ensure that the difference between the second voltage and ground is greater than a second preset value, thus ensuring that the second switching module is turned on. Ultimately, the ESD energy forms a complete discharge path through the turned-on first and second switching modules, achieving effective protection of the circuit. Therefore, compared to existing technologies that rely on additional independent ESD devices for protection, this application eliminates the need for dedicated ESD devices at the input voltage port and intermediate nodes. Instead, it achieves ESD energy discharge by coordinating the switching module's conduction across various modules. This reduces the occupied area of ​​the chip's active region and layout, thus shrinking the overall chip size. Furthermore, it eliminates the design, manufacturing, and integration costs of independent ESD devices, effectively lowering the chip's R&D and mass production costs.

[0029] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0030] Figure 3 A schematic block diagram of a power stage electrostatic discharge protection circuit according to an embodiment of this application is shown. See also... Figure 3As shown, the power stage electrostatic discharge protection circuit includes a first drive control module 101, a first coupling adjustment module 102, a first switch module 103, a second drive control module 104, a second coupling adjustment module 105, and a second switch module 106. The first coupling adjustment module 102 is electrically connected to the first drive control module 101 and the first switch module 103, respectively. The second coupling adjustment module 105 is electrically connected to the second drive control module 104, the second switch module 106, and the first switch module 103, respectively.

[0031] Specifically, when an ESD event occurs at the input voltage VIN, the input voltage VIN rises rapidly. The first drive control module 101 receives the first drive signal pdrive and the first control signal Vcn, and outputs a first voltage PDR based on the first drive signal pdrive and the first control signal Vcn. The first coupling adjustment module 102 can dynamically adjust the first voltage PDR so that the difference between the first voltage PDR and the input voltage VIN is greater than a first preset value, ensuring that the first switch module 103 is turned on. After the first switch module 103 is turned on, the voltage at the intermediate node (voltage at SW) between the first switch module 103 and the second switch module 106 will rise rapidly. At the same time, the second drive control module 104 receives the second drive signal ndrive and the second control signal Vc, and outputs a second voltage NDR based on the second drive signal ndrive and the second control signal Vc. The second coupling adjustment module 105 can dynamically adjust the second voltage NDR so that the difference between the second voltage NDR and ground is greater than a second preset value, ensuring that the second switch module 106 is turned on. Ultimately, the ESD energy forms a complete discharge path through the first switch module 103 and the second switch module 106, achieving effective protection of the circuit. Therefore, compared to existing technologies that rely on additional independent ESD devices for protection, this application eliminates the need for dedicated ESD devices at the input voltage VIN port and intermediate nodes. Instead, it achieves ESD energy discharge through the coordinated control of the switch modules, reducing the occupied active area and layout area of ​​the chip, and shrinking the overall chip size. Simultaneously, it eliminates the design, manufacturing, and integration costs of independent ESD devices, effectively reducing the chip's R&D and mass production costs.

[0032] It should be noted that the first drive control module 101 is connected between the input terminal and ground, the first coupling adjustment module 102 is connected between the input terminal and the SW node, and the first switch module 103 is connected between the input terminal and the SW node. The second drive control module 104 is connected between the input terminal and ground, the second coupling adjustment module 105 is connected between the SW node and ground, and the second switch module 106 is connected between the SW node and ground. After the input voltage VIN ESD event ends, the first coupling adjustment module 102 can also slowly pull up the first voltage PDR to match the input voltage VIN, so that the conduction condition of the first switch module 103 disappears and it is reliably turned off; the second coupling adjustment module 105 can also slowly pull down the second voltage NDR to ground potential, so that the conduction condition of the second switch module 106 disappears and it is reliably turned off. Since both the first switch module 103 and the second switch module 106 can return to the off state after the ESD event ends, and the first switch module 103 and the second switch module 106 used in this application are the original power devices inside the chip, not additional dedicated ESD protection devices, the two switch modules can fully follow the original working logic of the chip to perform power drive functions when no ESD event occurs, without interfering with the normal working performance of the chip.

[0033] It should be noted that when an ESD event occurs, the first drive signal pdrive and the second drive signal ndrive output by the chip are inverted signals. If the first drive signal pdrive is low, the second drive signal ndrive is high; conversely, if the first drive signal pdrive is high, the second drive signal ndrive is low. Furthermore, the first control signal Vcn and the second control signal Vc output by the chip are inverted signals. If the first control signal Vcn is high, the second control signal Vc is low; conversely, if the first control signal Vcn is low, the second control signal Vc is high.

[0034] For example, when an ESD event occurs, the chip's internal components automatically output drive and control signals. These components mainly include digital logic gates, oscillators / clock generators, comparators, microcontroller / processor cores, state machines / timing controllers, and latches / flip-flops. These devices can automatically generate and output corresponding drive and control signals based on the chip's operating state or external inputs. Furthermore, the chip contains devices for detecting ESD spikes, such as ESD detection circuits, which can sense ESD characteristics such as transient rapid rises in input voltage VIN or internal node voltages and trigger corresponding protection mechanisms.

[0035] The first driving signal pdrive and the second driving signal ndrive are inverted signals, as are the first control signal Vcn and the second control signal Vc. The inversion of the signals can be achieved using inverters, or through digital logic gates such as NAND gates, NOR gates, and XOR gates. For example, a NAND gate can achieve inversion under a specific input combination, and an XOR gate can also achieve inversion when a fixed input is used. In addition, it can also be achieved through sequential logic circuits such as D flip-flops, analog circuits such as operational amplifiers, and software programming.

[0036] This application uses the following scenario as an example to illustrate the technical solution: When an ESD event occurs, the first drive signal pdrive is a low-level signal, the second drive signal ndrive is a high-level signal, and the first control signal Vcn is a high-level signal and the second control signal Vc is a low-level signal.

[0037] The following is combined with Figure 4 The circuit diagram shown provides a detailed description of the working principle of the power stage electrostatic discharge protection circuit provided in the embodiments of this application.

[0038] In one embodiment of this application, such as Figure 4 As shown, the first drive control module 101 includes a first switch MP2, a second switch MP1, and a third switch MN1. The gates of the first switch MP2 and the third switch MN1 are both used to receive the first drive signal pdrive. The source of the first switch MP2 is used to receive the input voltage VIN. The drain of the first switch MP2 is electrically connected to the source of the second switch MP1. The gate of the second switch MP1 is used to receive the first control signal Vcn. The drain of the second switch MP1 is electrically connected to the drain of the third switch MN1, the first coupling adjustment module 102, and the first switch module 103, respectively. The source of the third switch MN1 is grounded.

[0039] Specifically, when an ESD event occurs, the input voltage VIN rises rapidly. The gate of the first switch MP2 receives the first drive signal pdrive (low-level signal), and the source of the first switch MP2 receives the input voltage VIN, causing the VGS of the first switch MP2 to reach the turn-on threshold and turn on. The input voltage VIN is then transmitted to the source of the second switch MP1. Since the gate of the second switch MP1 receives the first control signal Vcn (high-level signal), the second switch MP1 is not turned on and is in the off state. At the same time, the gate of the third switch MN1 receives the first drive signal pdrive, and the source of the third switch MN1 is grounded, so the third switch MN1 is not turned on and is also in the off state. During this process, since both the second switch MP1 and the third switch MN1 are off, the first voltage PDR generated by the first drive control module 101 is in a high-impedance state.

[0040] For example, designers can select the types of the first switch MP2, the second switch MP1, and the third switch MN1 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the first switch MP2 and the second switch MP1 can both be PMOS transistors, and the third switch MN1 can be an NMOS transistor.

[0041] It should be noted that the embodiments provided in this application only show one circuit structure as the first drive control module 101, and do not mean that only this one circuit structure can realize the function of the first drive control module 101. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0042] In one embodiment of this application, such as Figure 4 As shown, the first coupling adjustment module 102 includes a first resistor RP and a first capacitor Cgdp. The first end of the first resistor RP is used to receive the input voltage VIN. The second end of the first resistor RP is electrically connected to the first end of the first capacitor Cgdp, the first drive control module 101 and the first switch module 103, respectively. The second end of the first capacitor Cgdp is electrically connected to the first switch module 103, the second switch module 106 and the second coupling adjustment module 105, respectively.

[0043] Specifically, during an ESD event, the transient rise in input voltage VIN, coupled through the first capacitor Cgdp, creates a voltage difference between the first voltage PDR and the input voltage VIN. This difference is greater than a preset value, ensuring reliable conduction of the first switch module 103 and providing a path for ESD energy discharge. The first resistor RP acts as a pull-up resistor, slowly pulling the first voltage PDR up to match the input voltage VIN after the ESD event ends, thus eliminating the conduction condition of the first switch module 103 and achieving its smooth turn-off, avoiding interference with normal chip operation. Therefore, the synergistic effect of the first resistor RP and the first capacitor Cgdp enables rapid triggering of the first switch module 103 during an ESD event and smooth reset after the event ends.

[0044] It should be noted that the specific form of the first capacitor Cgdp is not limited. It can be either a parasitic capacitor integrated into the first switching module 103 itself or an independent capacitor added to the circuit. Both can achieve the coupling adjustment function required by this application.

[0045] It should be noted that the embodiments provided in this application only show one circuit structure as the first coupling adjustment module 102, and do not mean that only this one circuit structure can realize the function of the first coupling adjustment module 102. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0046] In one embodiment of this application, such as Figure 4 As shown, the first switching module 103 includes a first power transistor MP. The gate of the first power transistor MP is electrically connected to the first drive control module 101 and the first coupling adjustment module 102, respectively. The source of the first power transistor MP is used to receive the input voltage VIN. The drain of the first power transistor MP is electrically connected to the first coupling adjustment module 102, the second switching module 106 and the second coupling adjustment module 105, respectively.

[0047] Specifically, the first power transistor MP acts as a switching device. When an ESD event occurs, the gate of the first power transistor MP receives the first voltage PDR regulated by the first coupling adjustment module 102, and the source receives the input voltage VIN. At this time, the VGS of the first power transistor MP reaches the turn-on threshold, and the first power transistor MP reliably turns on, providing a path for the discharge of ESD energy. That is, ESD energy can be transferred to the SW node through the turned-on first power transistor MP. When the ESD event ends, the gate voltage (first voltage PDR) of the first power transistor MP equals the source voltage (input voltage VIN). At this time, the VGS of the first power transistor MP = 0, and the first power transistor MP turns off to avoid interfering with the normal operation of the chip.

[0048] For example, designers can select the type of the first power transistor MP according to the actual situation, that is, it can be a fully controllable power device such as a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor. For example, the first power transistor MP can be selected as a PMOS transistor.

[0049] It should be noted that the embodiments provided in this application only show one circuit structure as the first switch module 103, and do not mean that only this one circuit structure can realize the function of the first switch module 103. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0050] In one embodiment of this application, such as Figure 4As shown, the second drive control module 104 includes a fourth switch MP3, a fifth switch MN3, and a sixth switch MN2. The gates of the fourth switch MP3 and the sixth switch MN2 are used to receive the second drive signal ndrive. The source of the fourth switch MP3 is used to receive the input voltage VIN. The drain of the fourth switch MP3 is electrically connected to the drain of the fifth switch MN3, the second coupling adjustment module 105, and the second switch module 106, respectively. The gate of the fifth switch MN3 is used to receive the second control signal Vc. The source of the fifth switch MN3 is electrically connected to the drain of the sixth switch MN2, and the source of the sixth switch MN2 is grounded.

[0051] Specifically, when an ESD event occurs, the input voltage VIN rises rapidly. The gate of the fourth switch MP3 receives the second drive signal ndrive (high-level signal), and the source of the fourth switch MP3 receives the input voltage VIN. The fourth switch MP3 is off and does not conduct. Simultaneously, the gate of the sixth switch MN2 receives the second drive signal ndrive, and the source of the sixth switch MN2 is grounded, causing the VGS of the sixth switch MN2 to reach the conduction threshold and conduct. This causes the source of the fifth switch MN3 to be grounded through the conducting sixth switch MN2. The gate of the fifth switch MN3 receives the second control signal Vc (low-level signal), and the fifth switch MN3 is off and also does not conduct. During this process, since both the fourth switch MP3 and the fifth switch MN3 are off, the second voltage NDR generated by the second drive control module 104 is in a high-impedance state.

[0052] For example, designers can select the types of the fourth switch MP3, the fifth switch MN3, and the sixth switch MN2 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the fourth switch MP3 can be selected as a PMOS transistor, and the fifth switch MN3 and the sixth switch MN2 can both be selected as NMOS transistors.

[0053] It should be noted that the embodiments provided in this application only show one circuit structure as the second drive control module 104, and do not mean that only this one circuit structure can realize the function of the second drive control module 104. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0054] In one embodiment of this application, such as Figure 4As shown, the second coupling adjustment module 105 includes a second resistor RN and a second capacitor Cgdn. The first end of the second capacitor Cgdn is electrically connected to the first switch module 103, the second switch module 106 and the first coupling adjustment module 102, respectively. The second end of the second capacitor Cgdn is electrically connected to the first end of the second resistor RN, the second switch module 106 and the second drive control module 104, respectively. The second end of the second resistor RN is grounded.

[0055] Specifically, during an ESD event, the transient rise in input voltage VIN, coupled through the first capacitor Cgdp, reliably turns on the first switching module 103, causing the SW node voltage to rise rapidly. Then, through the coupling effect of the second capacitor Cgdn, a certain voltage difference is coupled between the second voltage NDR and ground. Even if the difference between the second voltage NDR and ground exceeds a second preset value, this ensures the reliable conduction of the second switching module 106, providing a path for ESD energy discharge. The first resistor RP acts as a pull-down resistor, slowly pulling the second voltage NDR to ground after the ESD event ends, thus eliminating the conduction condition of the second switching module 106 and achieving a smooth turn-off, avoiding interference with the normal operation of the chip. Therefore, the second resistor RN and the second capacitor Cgdn work together to achieve rapid triggering of the second switching module 106 during an ESD event and a smooth reset after the event ends.

[0056] It should be noted that the specific form of the second capacitor Cgdn is not limited. It can be either a parasitic capacitor integrated into the second switch module 106 itself or an independent capacitor added to the circuit. Both can achieve the coupling adjustment function required by this application.

[0057] It should be noted that the embodiments provided in this application only show one circuit structure as the second coupling adjustment module 105, and do not mean that only this one circuit structure can realize the function of the second coupling adjustment module 105. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0058] In one embodiment of this application, such as Figure 4 As shown, the second switching module 106 includes a second power transistor MN. The gate of the second power transistor MN is electrically connected to the second drive control module 104 and the second coupling adjustment module 105, respectively. The drain of the second power transistor MN is electrically connected to the first switching module 103, the second switching module 106 and the second coupling adjustment module 105, respectively. The source of the second power transistor MN is grounded.

[0059] Specifically, the second power transistor MN acts as a switching device. When an ESD event occurs, the gate of the second power transistor MN receives the second voltage NDR regulated by the second coupling adjustment module 105, and the source is grounded. At this time, the VGS of the second power transistor MN reaches the conduction threshold, and the second power transistor MN reliably conducts, providing a path for the discharge of ESD energy. That is, the ESD energy transmitted to the SW node through the conducting first power transistor MP can continue to be discharged to ground through the conducting second power transistor MN. When the ESD event ends, the gate voltage (second voltage NDR) of the second power transistor MN is equal to the ground potential. At this time, the VGS of the second power transistor MN = 0, and the second power transistor MN is turned off to avoid interfering with the normal operation of the chip.

[0060] For example, designers can select the type of the second power transistor MN according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the second power transistor MN can be selected as an NMOS transistor.

[0061] It should be noted that the embodiments provided in this application only show one circuit structure as the second switch module 106, and do not mean that only this one circuit structure can realize the function of the second switch module 106. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0062] It should be noted that when the input voltage VIN is present but the chip is not powered on, the first drive signal pdrive remains low. At this time, the first switch MP2 is turned on and the third switch MN1 is turned off, causing the first voltage PDR to be pulled high. This high level keeps the first power transistor MP off, preventing it from being mistakenly turned on during chip standby. At the same time, when the chip is not powered on, the second drive signal ndrive remains low, causing the fourth switch MP3 to turn off and the sixth switch MN2 to turn on, thereby pulling the second voltage NDR low to ground potential. This low level also keeps the second power transistor MN off, ensuring the circuit safety and stability of the chip in non-operating mode.

[0063] This application also discloses a power driver chip, including the aforementioned power-level electrostatic discharge (ESD) protection circuit. By integrating this circuit, the power driver chip can provide efficient and reliable ESD protection for the chip's input voltage pins and intermediate nodes without the need for additional independent ESD devices, effectively preventing ESD from damaging the chip's internal functional circuits. Simultaneously, by reusing the chip's existing internal switching modules to dissipate ESD energy, the occupied area of ​​the chip's active region is reduced, the overall chip size is minimized, and the chip's R&D and mass production costs are lowered. Furthermore, this ESD protection circuit is seamlessly compatible with the chip's existing power drive logic. When no ESD event occurs, each switching module fully follows the chip's original operating timing to perform the power drive function without interfering with the chip's normal operating performance. This achieves comprehensive optimization of chip protection performance, area cost, and operational stability, making it particularly suitable for power driver chip applications with stringent requirements for miniaturization, low cost, and high reliability.

[0064] Since the processing and functions implemented by the power drive chip in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned power level electrostatic discharge protection circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0065] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power-level electrostatic discharge protection circuit, characterized in that, It includes a first drive control module, a first coupling adjustment module, a first switch module, a second drive control module, a second coupling adjustment module, and a second switch module. The first coupling adjustment module is electrically connected to the first drive control module and the first switch module, respectively. The second coupling adjustment module is electrically connected to the second drive control module, the second switch module, and the first switch module, respectively. When an ESD event occurs in the input voltage, the first drive control module is used to output a first voltage according to the first drive signal and the first control signal; The first coupling adjustment module is used to adjust the first voltage so that the difference between the first voltage and the input voltage is greater than a first preset value, and the first switching module is turned on. The second drive control module is used to output a second voltage according to the second drive signal and the second control signal; The second coupling adjustment module is used to adjust the second voltage so that the difference between the second voltage and ground is greater than a second preset value, and the second switching module is turned on. After the input voltage ESD event ends, the first coupling adjustment module is used to pull the first voltage up to the input voltage, so that the first switching module is turned off; The second coupling adjustment module is used to pull the second voltage down to ground, thereby turning off the second switching module; The first drive control module includes a first switch, a second switch, and a third switch. The gates of the first switch and the third switch are both used to receive the first drive signal. The source of the first switch is used to receive the input voltage. The drain of the first switch is electrically connected to the source of the second switch. The gate of the second switch is used to receive the first control signal. The drain of the second switch is electrically connected to the drain of the third switch, the first coupling adjustment module, and the first switch module, respectively. The source of the third switch is grounded. The first coupling adjustment module includes a first resistor and a first capacitor. The first end of the first resistor is used to receive the input voltage. The second end of the first resistor is electrically connected to the first end of the first capacitor, the first drive control module, and the first switch module, respectively. The second end of the first capacitor is electrically connected to the first switch module, the second switch module, and the second coupling adjustment module, respectively. When an ESD event occurs in the input voltage, the first switch is turned on, and the second and third switches are all turned off. The first voltage generated by the first drive control module is in a high-impedance state.

2. The power-stage electrostatic discharge protection circuit according to claim 1, characterized in that, The first control signal is the inverted signal of the second control signal.

3. The power stage electrostatic discharge protection circuit according to claim 1, characterized in that, The second drive control module includes a fourth switch, a fifth switch, and a sixth switch. The gates of the fourth and sixth switches are both used to receive the second drive signal. The source of the fourth switch is used to receive the input voltage. The drain of the fourth switch is electrically connected to the drain of the fifth switch, the second coupling adjustment module, and the second switching module, respectively. The gate of the fifth switch is used to receive the second control signal. The source of the fifth switch is electrically connected to the drain of the sixth switch, and the source of the sixth switch is grounded.

4. The power stage electrostatic discharge protection circuit according to claim 1, characterized in that, The second coupling adjustment module includes a second resistor and a second capacitor. The first end of the second capacitor is electrically connected to the first switch module, the second switch module and the first coupling adjustment module, respectively. The second end of the second capacitor is electrically connected to the first end of the second resistor, the second switch module and the second drive control module, respectively. The second end of the second resistor is grounded.

5. The power stage electrostatic discharge protection circuit according to any one of claims 1-4, characterized in that, The first switching module includes a first power transistor, the gate of which is electrically connected to the first drive control module and the first coupling adjustment module, the source of which is used to receive the input voltage, and the drain of which is electrically connected to the first coupling adjustment module, the second switching module and the second coupling adjustment module.

6. The power stage electrostatic discharge protection circuit according to any one of claims 1-4, characterized in that, The second switching module includes a second power transistor. The gate of the second power transistor is electrically connected to the second drive control module and the second coupling adjustment module, respectively. The drain of the second power transistor is electrically connected to the first switching module and the second coupling adjustment module, respectively. The source of the second power transistor is grounded.

7. A power drive chip, characterized in that, Includes the power stage electrostatic discharge protection circuit as described in any one of claims 1-6.

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