Hemt transistor packaging method and hemt transistor

Abstract

The present application relates to the technical field of HEMT transistor packaging, and particularly relates to a HEMT transistor packaging method and a HEMT transistor, wherein the HEMT transistor packaging method first constructs a sacrificial layer covering an active region on the upper surface of the HEMT transistor; then performs deposition on the upper surface of the HEMT transistor to form a structure layer covering a HEMT upper structure; then etches a release hole exposing the sacrificial layer at a position corresponding to the sacrificial layer of the structure layer, and removes the sacrificial layer by injecting a solvent through the release hole; and finally performs deposition of a second passivation layer above the structure layer, so that the release hole is blocked and the structure layer is covered with the second passivation layer above, wherein the active region is sealed and protected after the HEMT transistor is packaged, the reliability requirements such as waterproof invasion in engineering application are met, and the problem that high frequency and reliability are difficult to be unified due to the thickness of the passivation layer is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of HEMT transistor packaging technology, and more particularly to a HEMT transistor packaging method and a HEMT transistor. Background Technology

[0002] HEMT (High Electron Mobility Transistor), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a field-effect transistor based on heterojunction design, characterized by extremely high electron mobility and excellent high-frequency performance.

[0003] The key innovation of HEMT transistors lies in the use of two semiconductor materials with different bandgap widths to form a heterojunction (such as AlGaAs / GaAs, AlGaN / GaN): a wide bandgap material (such as n-type AlGaAs) acts as a donor layer to provide electrons; a narrow bandgap material (such as undoped GaAs) acts as a channel layer. Due to band discontinuities and polarization effects, electrons transfer from the wide bandgap material to the interface of the narrow bandgap material, forming a two-dimensional electron gas (2DEG) – a highly concentrated electron cloud confined within a few nanometers of the interface, with an electron density reaching approximately 10¹³ cm⁻¹. - ².

[0004] By spatially separating the doped region and the carrier channel, Coulomb scattering between electrons and ionized impurities is significantly reduced, resulting in a substantial increase in electron mobility (approximately 5000-8000 cm² / V for GaAs-based HEMTs). s, GaN-based, approximately 1500-2000 cm² / V s, far exceeding the approximately 1400 cm² / V of silicon MOSFETs. A standard HEMT consists of: a substrate → a buffer layer → a channel layer (undoped with a narrow bandgap) → a barrier layer (doped with a wide bandgap) → a source / drain / gate three-electrode structure.

[0005] Among these, indium phosphide high electron mobility transistors (InP HEMTs) possess advantages such as low noise, high frequency, and high electron mobility, occupying an important position in high-speed and high-frequency applications and gradually becoming the primary choice for ultra-high frequency low-noise and power amplifier circuit design. In recent years, domestic and international researchers have been competing to conduct research on terahertz solid-state radio frequency electronic devices and circuits based on InP HEMT devices, promoting their application in fields such as medical imaging, space communication, and security inspection.

[0006] In the terahertz band, the key to improving the operating frequency and gain of InP HEMT devices and circuits is to reduce the gate length and thin the silicon nitride passivation layer, thereby reducing the device's parasitic capacitance. However, in engineering applications, this leads to a decrease in the device's resistance to humid water vapor, failing to meet the reliability requirements of engineering applications. Engineering applications generally require devices to use a thick silicon nitride passivation layer structure to prevent moisture intrusion, but a thick silicon nitride passivation layer will result in a large gate parasitic capacitance and deterioration of high-frequency characteristics.

[0007] Therefore, it is necessary to develop novel InP HEMT device fabrication methods to resolve the contradiction between high frequency and reliability. Summary of the Invention

[0008] The present invention provides a HEMT transistor packaging method and a HEMT transistor, which solves the problem that the passivation layer in the prior art is difficult to balance high-frequency characteristics and reliability.

[0009] In a first aspect, embodiments of the present invention provide a HEMT transistor packaging method, comprising: A sacrificial layer covering the active region is constructed on the upper surface of the HEMT transistor, wherein the active region includes the drain, source, and gate regions. A structural layer is deposited on the upper surface of the HEMT transistor to form a structure layer covering the structure above the HEMT; At the location of the structural layer corresponding to the sacrificial layer, release holes are etched to expose the sacrificial layer, and the sacrificial layer is removed by injecting solvent through the release holes; A second passivation layer is deposited over the structural layer, thereby sealing the release hole and covering the structural layer with the second passivation layer.

[0010] In one possible implementation, constructing a sacrificial layer covering the active region on the upper surface of the HEMT transistor includes: A first photoresist is coated on the upper surface of the HEMT transistor and baked to form a first photoresist layer; The first photoresist layer is exposed and developed according to the position of the sacrificial layer; The first photoresist layer after development is subjected to a hardening process to obtain the sacrificial layer.

[0011] In one possible implementation, the first photoresist is a negative photoresist, and the exposure of the first photoresist layer gradually decreases from the edge of the active region to the non-active region.

[0012] In one possible implementation, etching a release hole at a location on the structural layer corresponding to the sacrificial layer to expose the sacrificial layer includes: A second photoresist is coated on the upper surface of the structural layer and baked to form a second photoresist layer, wherein the second photoresist is a positive photoresist; The area outside the corresponding opening position of the second photoresist layer is exposed and developed; The release hole is formed by etching the structural layer at the opening location using an etching process; Remove the second photoresist layer after development.

[0013] In one possible implementation, the cross-section of the structural layer is a trapezoid, narrower at the top and wider at the bottom. The top of the slope of the structural layer is located at the edge of the active region, the bottom of the slope of the structural layer is located in the passive region, and the opening is located on the slope of the structural layer near the bottom.

[0014] In one possible implementation, the passive region is provided with a metal pressure point, and after a second passivation layer is deposited over the structural layer, such that the release hole is sealed and the structural layer is covered with a second passivation layer, the following steps are included: A third photoresist is coated on the upper surface of the second passivation layer and baked to form a third photoresist layer, wherein the third photoresist is a positive photoresist; The positions of the metal pressure points corresponding to the third photoresist layer are exposed and developed; The second passivation layer and structural layer at the metal pressure point location are etched using an etching process to expose the metal pressure point. Remove the third photoresist layer after development.

[0015] In a second aspect, embodiments of the present invention provide a HEMT transistor, comprising: a transistor body formed based on a semiconductor material and a structural layer forming a sealed cavity with the transistor body and surrounding the active region inside the cavity; The active region includes the area containing the drain, source, and gate.

[0016] In one possible implementation, the surface of the active region is covered with a first passivation layer, and a second passivation layer is covered over the structural layer.

[0017] In one possible implementation, gates and sources are provided in pairs along multiple radial lines centered on the drain of the transistor body, with the gate on the same radial line located on the side of the source closer to the drain.

[0018] In one possible implementation, the gate is T-shaped or mushroom-shaped; the gate is formed by coating a substrate material with multiple layers of photoresist, followed by exposure, development, metal deposition, and stripping of the multiple layers of photoresist.

[0019] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: This invention discloses a HEMT transistor packaging method. First, a sacrificial layer covering the active region is constructed on the upper surface of the HEMT transistor. The active region includes the areas containing the drain, source, and gate. Then, a structural layer covering the upper surface of the HEMT transistor is deposited. Next, release holes are etched at positions on the structural layer corresponding to the sacrificial layer, exposing the sacrificial layer. Solvent is injected through these release holes to remove the sacrificial layer. Finally, a second passivation layer is deposited on top of the structural layer, sealing the release holes and covering the structural layer with the second passivation layer. After packaging, the HEMT device can still be fabricated using a thin silicon nitride passivation layer, achieving high-frequency and gain performance. This technology seals and protects the active region after device completion, meeting reliability requirements such as water vapor intrusion in engineering applications, and effectively solving the problem of inconsistent high-frequency performance and reliability due to the thickness of the passivation layer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of the HEMT transistor packaging method provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the HEMT transistor body provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a HEMT transistor after constructing a sacrificial layer, provided by an embodiment of the present invention. Figure 4 This is a schematic diagram of the HEMT transistor after the structural layer is constructed, as provided in the embodiments of the present invention. Figure 5 This is a schematic diagram of a HEMT transistor after constructing a release hole and removing the sacrificial layer, provided by an embodiment of the present invention. Figure 6 This is a schematic diagram of a HEMT transistor after the deposition of a second passivation layer, provided by an embodiment of the present invention. Figure 7 This is a schematic diagram of a HEMT transistor with exposed metal pressure points provided in an embodiment of the present invention.

[0022] In the picture: 201 substrate; 202 Gate; 203 Drain; 204 Source pole; 205 Metal pressure point; 206 First passivation layer; 207 Sacrificial Layer; 208 structural layers; 209 Release hole; 210 Second passivation layer; 211. Hollowed-out window. Detailed Implementation

[0023] In the following description, specific details such as particular system structures and techniques are set forth for illustrative purposes and not for limitation, so as to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0025] The embodiments of the present invention will be described in detail below. This example is implemented based on the technical solution of the present invention, and provides detailed implementation methods and specific operation processes. However, the protection scope of the present invention is not limited to the following embodiments.

[0026] like Figure 1 As shown in the figure, this embodiment of the invention provides a HEMT transistor packaging method, including: In step 101, a sacrificial layer 207 covering the active region is constructed on the upper surface of the HEMT transistor, wherein the active region includes the area where the drain 203, the source 204, and the gate 202 are located. In step 102, a structural layer 208 covering the structure above the HEMT transistor is deposited on the upper surface of the HEMT transistor. In some embodiments, constructing a sacrificial layer 207 covering the active region on the upper surface of the HEMT transistor includes: A first photoresist is coated on the upper surface of the HEMT transistor and baked to form a first photoresist layer; The first photoresist layer is exposed and developed according to the position of the sacrificial layer 207; The first photoresist layer after development is subjected to a hardening process to obtain the sacrificial layer 207.

[0027] In some embodiments, the first photoresist is a negative photoresist, and the exposure of the first photoresist layer gradually decreases from the edge of the active region to the non-active region.

[0028] For example, such as Figure 2-7 As shown, this embodiment of the invention provides a HEMT transistor, which has a gate 202 formed above a substrate 201 (InP epitaxial layer). Figure 2 The part marked with G is the gate, and the drain is 203 ( Figure 2 The electrode marked with D is the drain electrode) and the source electrode 204 ( Figure 2 (The part marked with 'S' is the source). In some scenarios, multiple gates 202 and multiple sources 204 are used to improve the power amplification factor. As mentioned earlier, in order to provide better protection for the active region (the area containing gates 202, drains 203, and sources 204), a thin passivation layer (usually silicon nitride) is formed above the active region. Since the passivation layer covers a wide area, a relatively safe thickness is usually set in the process. However, if this passivation layer is too thick, the parasitic capacitance will increase significantly, leading to a decrease in the high-frequency performance of the HEMT transistor. Thinning the passivation layer will reduce the protection effect to some extent, and the non-uniformity of the passivation layer thickness makes the above problems more prominent in the case of multiple gates 202 and multiple sources 204.

[0029] This invention aims to provide a highly hermetically tight wafer-level packaging method, in which a structural layer 208 and a second passivation layer 210 are sequentially deposited above the active region of the InP HEMT (in one scenario, the two layers are silicon nitride and aluminum oxide thin films) to form a sealed "roof" structure. This dense thin film dielectric does not affect the gate parasites of the InP HEMT, thus ensuring that its high-frequency characteristics are not affected. At the same time, it has a good barrier effect against moisture, thus solving the contradiction between high frequency and reliability in InP HEMT devices.

[0030] To achieve the above objectives, the present invention first constructs a sacrificial layer 207 above the active region (in some scenarios, the upper surface of the HEMT is covered with a first passivation layer 206, i.e., a thin silicon nitride layer). This sacrificial layer 207 is actually constructed using a first photoresist. During construction, the first photoresist is first coated and baked, and then exposure, development, and hardening processes are performed to ensure that only the source region is covered by the photoresist. In some scenarios, this photoresist layer, serving as the sacrificial layer 207, has a thickness of approximately 2 μm. Figure 3 The schematic diagram of the HEMT transistor after constructing the sacrificial layer 207.

[0031] In some scenarios, the first photoresist is a negative photoresist. This means that when exposing the first photoresist, exposure is only applied to the location of the sacrificial layer 207. Furthermore, the present invention aims to create a trapezoidal cross-section for the structural layer, narrower at the top and wider at the bottom. Therefore, during exposure, the exposure amount decreases from the edge of the active region towards the non-active region. Since the exposed portion of the negative photoresist is retained after development, while the unexposed portion is removed, and due to the characteristics of the negative photoresist, the sacrificial layer 207 is more easily formed into a trapezoidal cross-section. Compared to positive photoresist, which requires exposure before removal after development, the first photoresist in the non-active region is removed more thoroughly after development.

[0032] In fact, the sacrificial layer 207 is a layer constructed to create a protective structure. Based on this, the present invention deposits silicon nitride (in one scenario, the deposition material is silicon nitride) on the upper surface of the HEMT transistor, forming a "roof": structural layer 208. For example... Figure 4 As shown in the figure, this diagram illustrates the schematic of the HEMT transistor after constructing structural layer 208.

[0033] In step 103, at the position of the structural layer 208 corresponding to the sacrificial layer 207, a release hole 209 is etched to expose the sacrificial layer 207, and the sacrificial layer 207 is removed by injecting solvent through the release hole 209. In some embodiments, etching a release hole 209 at a location on the structural layer 208 corresponding to the sacrificial layer 207 to expose the sacrificial layer 207 includes: A second photoresist is coated on the upper surface of the structural layer 208 and baked to form a second photoresist layer, wherein the second photoresist is a positive photoresist; The area outside the corresponding opening position of the second photoresist layer is exposed and developed; The release hole 209 is formed by etching the structural layer 208 at the opening location using an etching process. Remove the second photoresist layer after development.

[0034] In some embodiments, the cross-section of the structural layer 208 is a trapezoid that is narrower at the top and wider at the bottom. The top of the slope of the structural layer 208 is located at the edge of the active area, the bottom of the slope of the structural layer 208 is located in the passive area, and the opening is located on the slope of the structural layer 208 near the bottom.

[0035] For example, such as Figure 5 As shown, after forming the structural layer 208, the present invention removes the material of the sacrificial layer 207 by etching a release hole 209 on the structural layer 208 and injecting solvent through the release hole 209.

[0036] Specifically, regarding the etching of the release hole 209, the present invention etches a release hole 209 through the thickness direction of the structural layer 208 at a predetermined position corresponding to the sacrificial layer 207 in the structural layer 208 using a specific etching process. The core function of the release hole 209 is to completely expose the underlying sacrificial layer 207, providing a channel for the subsequent removal of the sacrificial layer 207. After the release hole 209 is formed, a suitable solvent is injected into the sacrificial layer 207 region through the release hole 209. The solvent penetrates along the release hole 209 and dissolves or reacts with the sacrificial layer 207 material, thereby completely removing the sacrificial layer 207 and laying the foundation for the formation of the structural layer 208.

[0037] The specific process for etching the release hole 209 is as follows: First, a second photoresist layer is uniformly coated onto the upper surface of the structural layer 208. The coating method can be spraying, and the coating thickness needs to be adjusted according to the subsequent etching depth and lithography resolution requirements. After coating, the second photoresist is baked to remove solvent components, enhance adhesion between the photoresist and the surface of the structural layer 208, and improve the photoresist's mechanical strength and etching resistance, providing a stable substrate for subsequent exposure and development processes. It should be noted that the second photoresist used in this embodiment is a positive photoresist, characterized by a change in molecular structure after exposure, making it easily dissolved and removed in the developer.

[0038] Subsequently, a light source of the corresponding wavelength is used in conjunction with a preset mask pattern to selectively expose the second photoresist layer. The mask pattern must clearly define the opening area of ​​the release hole 209, so that the area of ​​the second photoresist layer other than the corresponding opening position is blocked by the mask, and only the photoresist layer corresponding to the opening position receives light. After exposure, the device is placed in a special developer for development. The exposed area of ​​the positive photoresist will gradually dissolve in the developer, while the unexposed area (i.e., the area other than the opening position) remains intact. Finally, a cutout pattern corresponding to the position of the release hole 209 is formed on the second photoresist layer, exposing the structural layer 208 area to be etched below.

[0039] After development, using the remaining second photoresist layer as a mask, the structural layer 208 at the opening location is etched using a targeted etching process. The choice of etching process needs to be combined with the material properties of the structural layer 208 (such as silicon nitride, silicon dioxide). Dry etching (such as plasma etching, reactive ion etching) can be used. Dry etching has the advantages of high etching precision, good anisotropy, and minimal damage to the structural layer 208, making it more suitable for the preparation of high-precision release holes 209. During the etching process, the etching gas ratio, power, and time need to be controlled to ensure that the etching depth penetrates the structural layer 208, completely exposing the underlying sacrificial layer 207.

[0040] After the release hole 209 is formed, the remaining second photoresist layer on the device surface must be completely removed. Removal methods include ashing (through plasma oxidation to decompose the photoresist) or wet stripping (using a specialized stripping solution to dissolve the photoresist). Ashing is more suitable for scenarios requiring no residue, effectively removing photoresist residue from the hole walls and the surface of the structural layer 208, preventing residual photoresist from affecting subsequent solvent injection and the removal of the sacrificial layer 207, while also avoiding damage to the structural layer 208 and the active region. After removal, the morphology and location of the release hole 209 can be inspected using a microscope to ensure it meets design requirements.

[0041] In some embodiments, the cross-section of the structural layer 208 is a trapezoidal structure that is narrower at the top and wider at the bottom. This trapezoidal structure has excellent mechanical support performance, which can effectively disperse the stress generated during the operation of the device and avoid problems such as cracking and collapse of the structural layer 208. At the same time, it can optimize the electrical and optical coupling effect between the structural layer 208 and the underlying substrate and surrounding areas.

[0042] From a positional perspective, the top of the slope of structural layer 208 (the upper base of the trapezoid) is precisely aligned with and located at the edge of the active region of the device. As the core working area of ​​the device, the active region needs to minimize the obstruction and interference from structural layer 208. The top of the slope being located at the edge of the active region can minimize the impact of structural layer 208 on the performance of the active region, while also providing some edge protection for the active region. The bottom of the slope of structural layer 208 (the lower base of the trapezoid) extends to the passive region of the device. The passive region is the auxiliary structural area of ​​the device, mainly used for arranging process vias, wiring, and support structures. It has ample space and low performance sensitivity. The bottom of the slope being located here can avoid functional conflicts between structural layer 208 and the active region, while also providing a stable support substrate for structural layer 208.

[0043] Based on the aforementioned trapezoidal structure design, the opening position of the release hole 209 is set on the slope of the structural layer 208 near the bottom. This location selection has multiple advantages: Firstly, the structural layer 208 is thicker and has higher mechanical strength in the area near the bottom of the slope, making it less prone to damage to the structural layer 208 due to stress concentration during etching. At the same time, the bottom of the slope is far from the active area, effectively avoiding indirect damage to the active area caused by the etching process. Secondly, the opening position on the slope optimizes the solvent injection path, allowing the solvent to diffuse rapidly along the surface of the sacrificial layer 207 after being injected through the release hole 209, achieving uniform removal of the sacrificial layer 207 and reducing residue. In addition, setting the opening on the slope also avoids the release hole 209 being directly opposite the active area, further reducing the risk of contamination to the active area during solvent injection and removal of the sacrificial layer 207, ensuring the stability of the core performance of the device.

[0044] Furthermore, the location of the release hole 209 and the shape of the structural layer 208 in this invention make it easier to seal the release hole 209 in subsequent processes.

[0045] In step 104, a second passivation layer 210 is deposited over the structural layer 208, such that the release hole 209 is blocked and the structural layer 208 is covered with the second passivation layer 210.

[0046] Furthermore, in some scenarios, a metal pressure point 205 is provided in the passive region. After the second passivation layer 210 is deposited above the structural layer 208, thereby sealing the release hole 209 and covering the structural layer 208 with the second passivation layer 210, the following steps are taken: A third photoresist is coated on the upper surface of the second passivation layer 210 and baked to form a third photoresist layer, wherein the third photoresist is a positive photoresist; The third photoresist layer is exposed and developed at the position corresponding to the metal pressure point 205; The second passivation layer 210 and the structural layer 208 at the metal pressure point 205 are etched by an etching process to expose the metal pressure point 205. Remove the third photoresist layer after development.

[0047] For example, after the preparation of the release hole 209 and the removal of the sacrificial layer 207 are completed, a second passivation layer 210 needs to be deposited on top of the structural layer 208. The core function of the second passivation layer 210 is to protect the formed structural layer 208 and to permanently seal the release hole 209, preventing impurities, moisture, etc., from entering the device interior in subsequent processes and affecting the performance of the active region and the stability of the structural layer 208. Figure 6 As shown in the figure, this figure illustrates the schematic diagram of a HEMT transistor after deposition of the second passivation layer 210 according to an embodiment of the present invention.

[0048] During the deposition process, materials that are compatible with the device, have excellent insulation properties, and strong adhesion (such as Al2O3 deposited using ALD) must be selected. After deposition, it is necessary to ensure that the second passivation layer 210 uniformly covers the upper surface of the structural layer 208 and the inner wall of the release hole 209 to achieve a tight seal of the release hole 209. At the same time, it is necessary to ensure that the surface of the passivation layer is flat and free of defects such as pinholes and cracks, so as to provide a reliable substrate for subsequent processes.

[0049] Furthermore, in some micro / nano device packaging and electrical connection scenarios, passive areas are pre-set with metal pressure points 205. These metal pressure points 205 are used for device-to-external circuit conduction, test probe contact, or package interconnection, and need to be exposed after the second passivation layer 210 is deposited. Therefore, after the above-mentioned process of "depositing the second passivation layer 210 above the structural layer 208 to seal the release hole 209 and covering the structural layer 208 with the second passivation layer 210", an additional metal pressure point 205 exposure process is required. The specific steps are as follows: First, a third photoresist is uniformly coated on the upper surface of the second passivation layer 210. The coating thickness must be adapted to the subsequent etching depth to ensure effective protection of non-target areas. After coating, the third photoresist is baked. The core purpose is to remove residual solvent from the photoresist, enhance its adhesion to the surface of the second passivation layer 210, and improve its etching resistance, thus preventing photoresist detachment and deformation during subsequent exposure, development, and etching processes. It should be noted that the third photoresist used in this process is also a positive photoresist, maintaining consistency with the previous process to facilitate the reuse of process parameters and quality control. Its molecular chains break after irradiation with specific wavelengths of light, allowing it to selectively dissolve in the developer.

[0050] Subsequently, a dedicated mask is fabricated based on the pre-defined pattern of the metal pressure points 205. A light source of the corresponding wavelength (such as deep ultraviolet light to improve positioning accuracy) is used to selectively expose the third photoresist layer. During exposure, it is crucial to ensure precise alignment between the mask and the device, allowing the area corresponding to the metal pressure points 205 in the third photoresist layer to receive sufficient light, while the remaining areas are blocked by the mask. After exposure, the device is immersed in a matching developer solution for development. This process fully dissolves the exposed photoresist areas (i.e., the areas corresponding to the metal pressure points 205), while maintaining the integrity of the photoresist layer in the unexposed areas. Ultimately, a cutout window 211 corresponding to the metal pressure points 205 is formed on the third photoresist layer, exposing the area of ​​the second passivation layer 210 to be etched below. After development, the device surface must be quickly rinsed with deionized water to remove residual developer and prevent over-reaction from affecting the passivation layer and photoresist in non-target areas.

[0051] Using the residual third photoresist layer as a mask, a targeted etching process is employed to etch the second passivation layer 210 and a portion of the underlying structural layer 208 at the metal pressure point 205. The etching process must be selected based on the passivation layer material and the structural layer 208 material, with dry etching (such as reactive ion etching) being preferred. The etching depth is precisely controlled by adjusting the etching gas composition, etching power, and time—the second passivation layer 210 above the metal pressure point 205 must be completely removed, while the underlying structural layer 208 is lightly etched to ensure the upper surface of the metal pressure point 205 is completely exposed, with neat edges and no passivation layer residue. The etching rate must be monitored in real-time during the etching process to avoid over-etching that damages the metal pressure point 205 or under-etching that results in incomplete exposure of the metal pressure point 205, affecting subsequent electrical connection performance.

[0052] Figure 7 The schematic diagram of the HEMT transistor with the metal pressure point 205 exposed is shown.

[0053] After the metal pressure point 205 is exposed, the remaining third photoresist layer on the device surface must be completely removed. This removal can be achieved using a composite process of ashing combined with wet cleaning: first, plasma ashing (oxygen atmosphere, temperature 150-200℃) decomposes most of the photoresist residue; then, the device is immersed in a specialized stripping solution to remove residual photoresist debris from the hole walls and the surface of the metal pressure point 205; finally, it is rinsed with deionized water and dried. After removal, the exposure effect, edge morphology, and surface cleanliness of the metal pressure point 205 are inspected using a scanning electron microscope (SEM) to ensure no photoresist residue and no metal oxidation. Simultaneously, it is verified that other areas of the second passivation layer 210 are undamaged, meeting the requirements for subsequent device packaging and electrical testing.

[0054] The HEMT transistor packaging method of the present invention first constructs a sacrificial layer 207 covering the active region on the upper surface of the HEMT transistor, wherein the active region includes the area containing the drain 203, the source 204, and the gate 202; then, a structural layer 208 covering the structure above the HEMT transistor is deposited on the upper surface of the HEMT transistor; next, release holes 209 are etched in the structural layer 208 at positions corresponding to the sacrificial layer 207 to expose the sacrificial layer 207, and solvent is injected through the release holes 209 to remove the sacrificial layer 207. Layer 207; Finally, a second passivation layer 210 is deposited on top of the structural layer 208, so that the release hole 209 is blocked and the structural layer 208 is covered with the second passivation layer 210. After the HEMT transistor of the present invention is packaged, the HEMT device can still be fabricated using a thin silicon nitride passivation layer to achieve high frequency, gain and other performance of the device; after the device is completed, the active area is sealed and protected by this technology to meet the reliability requirements of water vapor intrusion in engineering applications, and effectively solve the problem that high frequency and reliability are difficult to unify due to the thickness of the passivation layer.

[0055] A second aspect of the present invention provides a HEMT transistor, comprising: a transistor body formed of a semiconductor material, a first passivation layer 206 covering the upper surface of the transistor body, and a structural layer 208 forming a sealed cavity with the transistor body and surrounding the active region inside the cavity. The active region includes the area containing the drain 203, the source 204, and the gate 202.

[0056] In some embodiments, the surface of the active region is covered with a first passivation layer 206, and a second passivation layer 210 is covered above the structural layer 208.

[0057] In some embodiments, gate 202 and source 204 are provided in pairs on multiple radial lines centered on the drain 203 of the transistor body, with the gate 202 on the same radial line located on the side of the source 204 closer to the drain 203.

[0058] In some embodiments, the gate 202 is T-shaped or mushroom-shaped; the gate 202 is formed by coating a multilayer of photoresist on a substrate 201 material, followed by exposure, development, metal deposition, and stripping of the multilayer photoresist.

[0059] By way of example, a second aspect of the present invention provides a HEMT transistor constructed based on the packaging method of the first aspect. The structural layer 208 and the semiconductor material form a sealed cavity, enclosing the active region inside. The active region includes the area where the drain 203, source 204 and gate 202 are located. This satisfies the reliability requirements for water vapor intrusion in engineering applications while minimizing the impact of the sealing structure on high-frequency characteristics.

[0060] In addition, in some scenarios, a thin passivation layer of silicon nitride is applied to the surface of the active area to enhance the protective effect. In other scenarios, a second passivation layer 210, usually made of Al2O3, is applied to the structural layer 208 to form a very high-quality sealing layer by utilizing the density of the material.

[0061] In some scenarios, such as Figure 2 As shown, with the drain 203 of the transistor as the center, there are pairs of gates 202 and drains 203 on the virtual radial line. The gate 202 is located on the side closer to the drain 203. In this way, the power of the transistor can be increased by using multiple pairs of gates 202 and drains 203.

[0062] In some scenarios, gate 202 is T-shaped or mushroom-shaped. Figure 2 The diagram shows a T-shaped gate. These gates 202 are formed by multiple layers of photoresist through exposure, development, metal deposition, and stripping of the multiple layers of photoresist. Compared with the gate 202 dielectric layer formation method, the gate 202 formed in this way reduces parasitic capacitance and improves the high-frequency characteristics of the transistor because the material used to construct the gate 202 is eventually removed.

[0063] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0064] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the aforementioned method embodiments, and will not be repeated here.

[0065] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0067] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A HEMT transistor packaging method, characterized in that, include: A sacrificial layer covering the active region is constructed on the upper surface of the HEMT transistor, wherein the active region includes the drain, source, and gate regions. A structural layer is deposited on the upper surface of the HEMT transistor to form a structure layer covering the structure above the HEMT, including: A first photoresist is coated on the upper surface of the HEMT transistor and baked to form a first photoresist layer; According to the position of the sacrificial layer, the first photoresist layer is exposed and developed. The first photoresist is a negative photoresist. The exposure amount of the first photoresist layer gradually decreases from the edge of the active region to the non-active region. The first photoresist layer after development is subjected to a hardening process to obtain the sacrificial layer; At the location of the structural layer corresponding to the sacrificial layer, a release hole is etched to expose the sacrificial layer, including: A second photoresist is coated on the upper surface of the structural layer and baked to form a second photoresist layer, wherein the second photoresist is a positive photoresist; The area outside the corresponding opening position of the second photoresist layer is exposed and developed; The release hole is formed by etching the structural layer at the opening location using an etching process; Remove the second photoresist layer after development; The sacrificial layer is removed by injecting solvent through the release hole; A second passivation layer is deposited over the structural layer to seal the release hole and cover the structural layer with the second passivation layer. The cross-section of the structural layer is a trapezoid, narrower at the top and wider at the bottom, and the opening is located on the slope of the structural layer near the bottom of the slope.

2. The HEMT transistor packaging method according to claim 1, characterized in that, The top of the slope of the structural layer is located at the edge of the active region, and the bottom of the slope of the structural layer is located in the passive region.

3. The HEMT transistor packaging method according to any one of claims 1-2, characterized in that, The passive region has a metal pressure point. A second passivation layer is deposited above the structural layer. After the release hole is sealed and the structural layer is covered with the second passivation layer, the process includes: A third photoresist is coated on the upper surface of the second passivation layer and baked to form a third photoresist layer, wherein the third photoresist is a positive photoresist; The positions of the metal pressure points corresponding to the third photoresist layer are exposed and developed; The second passivation layer and structural layer at the metal pressure point location are etched using an etching process to expose the metal pressure point. Remove the third photoresist layer after development.

4. A HEMT transistor manufactured by the HEMT transistor packaging method according to claim 1, characterized in that, include: A transistor body formed of semiconductor material and a structural layer that forms a sealed cavity with the transistor body and surrounds the active region inside the cavity; The active region includes the area containing the drain, source, and gate.

5. The HEMT transistor according to claim 4, characterized in that, The surface of the active region is covered with a first passivation layer, and a second passivation layer is covered on top of the structural layer.

6. The HEMT transistor according to claim 4 or 5, characterized in that, On multiple radial lines centered on the drain of the transistor body, gates and sources are provided in pairs, with the gate on the same radial line located on the side of the source closer to the drain.

7. The HEMT transistor according to claim 6, characterized in that, The gate is T-shaped or mushroom-shaped; the gate is formed by coating multiple layers of photoresist on a substrate material, followed by exposure, development, metal deposition, and stripping of the multiple layers of photoresist.

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