Memory management methods and storage devices

Abstract

This invention provides a memory management method and a memory device. The method includes: determining different candidate configuration strategies for multiple virtual blocks based on the distribution of first-type physical blocks in multiple planes, wherein each virtual block contains multiple second-type physical blocks; obtaining performance evaluation information corresponding to the different candidate configuration strategies; and determining a target configuration strategy from the different candidate configuration strategies based on the performance evaluation information. This improves the performance and operational stability of the memory device.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] Some types of storage devices (such as flash memory) support virtual blocks as the basic unit of management for memory modules. Each virtual block can contain multiple physical blocks. Ideally, multiple physical blocks within the same virtual block are distributed across multiple planes of the memory module. By performing multi-plane reads or multi-plane writes on multiple physical blocks within the same virtual block, the access performance of the memory module can be effectively improved.

[0003] However, a common problem in practice is that after a period of use, bad blocks will gradually appear in multiple physical blocks belonging to the same virtual block. As the number of bad blocks continues to increase, the number of good blocks in the virtual block will continue to decrease, causing a significant drop in the performance of memory modules operating based on virtual blocks. Furthermore, the location of bad blocks in the memory module is often irregular. If a good block located in the same or different plane as the bad block is randomly used to replace it, it is impossible to accurately predict or control the subsequent performance of the memory module. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can effectively improve the above-mentioned problems and thereby improve the performance and / or operational stability of the storage device.

[0005] This invention provides a memory management method, comprising: determining different candidate configuration strategies for multiple virtual blocks based on the distribution of first type entity blocks in multiple planes, wherein each virtual block contains multiple second type entity blocks; obtaining performance evaluation information corresponding to different candidate configuration strategies; and determining a target configuration strategy from the different candidate configuration strategies based on the performance evaluation information.

[0006] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0007] Based on the above, according to the distribution of the first type of entity blocks in multiple planes, different candidate configuration strategies for multiple virtual blocks can be determined, and each virtual block can contain multiple second type of entity blocks. After obtaining performance evaluation information corresponding to different candidate configuration strategies, the target configuration strategy can be automatically determined from different candidate configuration strategies based on this performance evaluation information. Thus, regardless of the health status of the storage device (e.g., whether the memory modules inside the storage device are in the early, middle, or late stages of their life cycle), the performance and operational stability of the storage device can be maintained or even significantly improved. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating the use of multiple virtual blocks to manage a memory module according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating the adjustment of the distribution of physical blocks in a virtual block according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram illustrating different types of virtual blocks corresponding to different operational performances according to embodiments of the present invention;

[0014] Figure 7 This is a schematic diagram of a first type of virtual block mapping table according to an embodiment of the present invention;

[0015] Figure 8 This is a schematic diagram of a first type of virtual block mapping table according to an embodiment of the present invention;

[0016] Figure 9 This is a schematic diagram illustrating the sorting of planes and solid blocks according to an embodiment of the present invention;

[0017] Figure 10 This is a schematic diagram of a second type of virtual block mapping table according to an embodiment of the present invention;

[0018] Figure 11 This is a schematic diagram illustrating mapping optimization according to an embodiment of the present invention;

[0019] Figure 12This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0021] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0022] Please refer to Figure 1 The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0023] Please refer to Figure 1 The buffer memory 112 is connected to the processor 111 and used to cache data. For example, the buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. The buffer memory 112 can be used as the main memory of the host system 11. In addition, the host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0024] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0025] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0026] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0027] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0028] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0029] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0030] Please refer to Figure 2 In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0031] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0032] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(C). Each physical unit includes multiple storage cells for non-volatile storage of data.

[0033] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes (B), and the invention is not limited thereto.

[0034] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes, and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0035] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0036] In one embodiment, an entity unit may include at least one entity erase unit. In another embodiment, if an entity unit includes multiple entity erase units, then this entity unit is also referred to as a virtual block. Multiple entity erase units (i.e., entity blocks) contained in the same virtual block can operate synchronously.

[0037] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0038] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0039] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0040] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0041] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0042] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0043] In one embodiment, the memory module 122 may include one or more chip-enabled (CE) regions. For example, the memory module 122 may include one or more dies. Dies are obtained from a wafer by laser dicing. Each die may be divided into one or more chip-enabled regions. Each chip-enabled region may contain one or more planes (also referred to as memory planes). Each plane may contain multiple physical blocks. Furthermore, the memory control circuitry 23 can access the memory module 122 through multiple channels (also referred to as memory channels) to improve access performance to the memory module 122.

[0044] In one embodiment, the memory control circuit 23 may be configured with multiple virtual blocks. Each virtual block may span multiple physical blocks located on multiple planes. Subsequently, the memory control circuit 23 can manage and / or access the memory module 122 by operating these virtual blocks. For example, the memory control circuit 23 may use one or more virtual blocks to synchronously write, read, or delete (i.e., erase) data on physical blocks located on different planes in the memory module 122.

[0045] Figure 4 This is a schematic diagram illustrating the use of multiple virtual blocks to manage a memory module according to an embodiment of the present invention. Please refer to... Figure 4 Assume that memory module 122 includes planes PL(0)-PL(3). In one embodiment, memory control circuitry 23 may configure multiple virtual blocks to manage and access multiple physical blocks distributed on planes PL(0)-PL(3). For example, the configured virtual blocks may include virtual blocks VB(0)-VB(10).

[0046] In one embodiment, the virtual blocks VB(0)-VB(10) may sequentially include physical blocks PB(0)-PB(3), physical blocks PB(4)-PB(7), physical blocks PB(8)-PB(11)... and physical blocks PB(40)-PB(43). The distribution of physical blocks PB(0)-PB(43) in the plane PL(0)-PL(3) is as follows: Figure 4 As shown. It should be noted that the total number of planes PL(0)-PL(3), the distribution of solid blocks PB(0)-PB(43) in planes PL(0)-PL(3), and the distribution of solid blocks contained in virtual blocks VB(0)-VB(10) in planes PL(0)-PL(3) can all be adjusted according to practical needs, and the present invention does not impose any restrictions.

[0047] In one embodiment, a virtual block can also span multiple chip enable regions within the memory module 122. Furthermore, in Figure 4 In the embodiment, it is assumed that all entity blocks PB(0)-PB(43) are good blocks (i.e., all entity blocks PB(0)-PB(43) can be used normally).

[0048] In one embodiment, the memory control circuit 23 may identify at least one of the physical blocks PB(0)-PB(43) as a bad block. For example, if the data read from physical block PB(i) contains too many error bits (e.g., the total number of error bits exceeds a preset number), the memory control circuit 23 may identify physical block PB(i) as a bad block.

[0049] In one embodiment, if any of the physical blocks PB(0)-PB(43) is determined to be a bad block, then this bad block will be removed from the corresponding virtual block, and this bad block can be replaced by a good block in the memory module 122. Figure 4 For example, assuming that physical block PB(0) is determined to be a bad block, this physical block PB(0) will be removed from the virtual block VB(0), and the original position of physical block PB(0) in the virtual block VB(0) will be replaced by a good block in memory module 122. In other words, in one embodiment, based on the detected bad block, memory control circuit 23 can adjust the distribution of physical blocks in the virtual blocks to remove the bad block from the corresponding virtual block.

[0050] Figure 5 This is a schematic diagram illustrating the adjustment of the distribution of physical blocks within a virtual block according to an embodiment of the present invention. Please refer to... Figure 4 and Figure 5 In one embodiment, the virtual block VB(2) can be adjusted to include physical blocks PB(8)-PB(10) and PB(40). Physical block PB(40) can be used to replace a bad block (e.g., physical block PB(11)) in plane PL(3). Specifically, in the adjusted virtual block VB(2), physical blocks PB(8) and PB(40) are actually located in the same plane (i.e., plane PL(0)), while physical blocks PB(9) and PB(10) are located in planes PL(1) and PL(2), respectively.

[0051] In one embodiment, the virtual block VB(3) can be adjusted to include physical blocks PB(12)-PB(14) and PB(41). Physical block PB(41) can be used to replace a bad block (e.g., physical block PB(15)) in plane PL(3). Specifically, in the adjusted virtual block VB(3), physical blocks PB(13) and PB(41) are actually located in the same plane (i.e., plane PL(1)), while physical blocks PB(12) and PB(14) are located in planes PL(0) and PL(2), respectively.

[0052] In one embodiment, the virtual block VB(4) may be adjusted to include physical blocks PB(16), PB(17), PB(20), and PB(21). Physical blocks PB(20) and PB(21) may be used to replace bad blocks (e.g., physical blocks PB(18) and PB(19)) located on planes PL(2) and PL(3), respectively. Specifically, in the adjusted virtual block VB(4), physical blocks PB(16) and PB(20) are actually located on the same plane (i.e., plane PL(0)), and physical blocks PB(17) and PB(21) are also actually located on the same plane (i.e., plane PL(1)).

[0053] In one embodiment, the virtual block VB(5) can be adjusted to include physical blocks PB(24), PB(28), PB(32), and PB(36). The physical blocks PB(28), PB(32), and PB(36) can respectively replace bad blocks (e.g., physical blocks PB(25) to PB(27)) located on planes PL(1) to PL(3). Specifically, in the adjusted virtual block VB(5), physical blocks PB(24), PB(28), PB(32), and PB(36) are all located on the same plane (i.e., plane PL(0)).

[0054] In one embodiment, the memory control circuit 23 can determine a virtual block as a normal virtual block or a mixed-plane virtual block. For example, if all entity blocks in a virtual block are completely distributed across different planes, the memory control circuit 23 can determine this virtual block as a normal virtual block. In other words, in a normal virtual block, there must be no multiple entity blocks located on the same plane. For example, the memory control circuit 23 can... Figure 5 The virtual blocks VB(0) and VB(1) in the code are determined to be normal virtual blocks.

[0055] On the other hand, if all entity blocks in a virtual block are not completely distributed across different planes, the memory control circuit 23 can define this virtual block as a mixed-plane virtual block. In other words, in a mixed-plane virtual block, there must exist multiple entity blocks located on the same plane. For example, the memory control circuit 23 can... Figure 5 The virtual blocks VB(2) to VB(5) in the middle are determined to be mixed plane virtual blocks.

[0056] In one embodiment, multiple entity blocks in a normal virtual block may lie on a certain number (also referred to as a first preset number) of planes. Multiple entity blocks in a mixed-plane virtual block may lie on another number (also referred to as a second preset number) of planes. The first preset number is greater than the second preset number.

[0057] by Figure 5 For example, the entity blocks in virtual blocks VB(0) and VB(1) (i.e., normal virtual blocks) are located on a total of 4 planes (i.e., the first preset number). The entity blocks in virtual blocks VB(2) and VB(3) (i.e., mixed-plane virtual blocks) are located on a total of 3 planes (i.e., the second preset number). The entity blocks in virtual block VB(4) (i.e., mixed-plane virtual block) are located on a total of 2 planes (i.e., the second preset number). In addition, the entity blocks in virtual block VB(5) (i.e., mixed-plane virtual block) are located on 1 plane (i.e., the second preset number).

[0058] In one embodiment, the memory control circuit 23 can determine the type of a virtual block based on the distribution of multiple physical blocks within a virtual block across multiple planes in the memory module 122. For example, different types of virtual blocks may span different numbers of planes. Figure 5 For example, the memory control circuit 23 can determine virtual blocks VB(0) and VB(1) as virtual blocks of type A; virtual blocks VB(2) and VB(3) as virtual blocks of type B1; virtual block VB(4) as virtual block of type B2; and virtual block VB(5) as virtual block of type C. Different types of virtual blocks can correspond to different operating performance.

[0059] In one embodiment, after initially establishing the various types of virtual blocks, the memory module 122 can further reorganize virtual blocks of type A (the best-performing virtual blocks) and virtual blocks of type C (the worst-performing virtual blocks) into virtual blocks of type B1 or B2. Thus, by reorganizing virtual blocks with extremely high performance into virtual blocks with moderate performance, the operational stability of the storage device 12 can be improved in subsequent operations.

[0060] Figure 6 This is a schematic diagram illustrating different types of virtual blocks corresponding to different operational performances according to embodiments of the present invention. Please refer to... Figure 6 Taking the four planes in memory module 122 as an example, when accessing memory module 122 by operating on a virtual block of type A (e.g., writing data to memory module 122), data can be transferred to the four planes (e.g., planes PL(0)-PB(3)) in one operation cycle. After the data transfer is completed in a single operation cycle, the write circuit inside memory module 122 performs parallel data writing for the physical blocks in these four planes.

[0061] When accessing memory module 122 by operating on a virtual block of type B1 (e.g., writing data to memory module 122), the data must be spread across three planes (e.g., planes PL(0)-PB(2)) in two operation cycles. After each operation cycle of data transfer is completed, parallel data writing to physical blocks in these three planes is performed by the write circuitry inside memory module 122.

[0062] When accessing memory module 122 by operating on a virtual block of type B2 (e.g., writing data to memory module 122), the data must also be distributed across two operation cycles to two planes (e.g., planes PL(0)-PB(1)). After each operation cycle of data transfer is completed, the write circuit inside memory module 122 performs parallel data writing to the physical blocks in these two planes.

[0063] Furthermore, when accessing memory module 122 by operating on a virtual block of type C (e.g., writing data to memory module 122), the data must be transmitted sequentially to a single plane (e.g., plane PL(0)) over four operation cycles. After each operation cycle of data transmission is completed, a separate data write for the physical block in this single plane is performed by the write circuitry inside memory module 122.

[0064] In one embodiment, the memory control circuit 23 can evaluate the operational performance corresponding to different types of virtual blocks. Figure 6 For example, the memory control circuit 23 can represent the operating performance corresponding to different types of virtual blocks according to the following formulas (1)-(4).

[0065]

[0066] In formulas (1)-(4), PER(A) represents the performance evaluation information corresponding to the virtual block of type A, PER(B1) represents the performance evaluation information corresponding to the virtual block of type B1, PER(B2) represents the performance evaluation information corresponding to the virtual block of type B2, PER(C) represents the performance evaluation information corresponding to the virtual block of type C, tDMA represents the duration of performing Direct Memory Access (DMA) on memory module 122, tProg represents the duration of performing programming operation (i.e., write operation) on memory module 122, and NP represents the total number of physical pages in a physical block. It should be noted that formulas (1)-(4) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0067] In one embodiment, PER(A), PER(B1), PER(B2), and PER(C) can be used to reflect the time (i.e., duration) required to access the memory module 122 through different types of virtual blocks (i.e., type A, type B1, type B2, and type C), respectively. Thus, the memory control circuit 23 can utilize PER(A), PER(B1), PER(B2), and PER(C) to evaluate and / or represent the operational performance corresponding to different types of virtual blocks.

[0068] In one embodiment, PER(A), PER(B1), PER(B2), and PER(C) respectively reflect the total time required to fill a virtual block when accessing a single virtual block of different types. In particular, according to formulas (1)-(4), PER(A) is less than PER(B1), PER(B1) is equal to PER(B2), and PER(B1) is less than PER(C). That is, PER(A), PER(B1), PER(B2), and PER(C) reflect that the time required to access the memory module 122 through a virtual block of type A is the shortest, the time required to access the memory module 122 through a virtual block of type B1 or B2 is moderate, and the time required to access the memory module 122 through a virtual block of type C is the longest.

[0069] In one embodiment, assuming that the operation performance corresponding to the virtual block of type A is set to "100%" based on the virtual block of type A, then according to formulas (1)-(4), the memory control circuit 23 can set the operation performance corresponding to the virtual blocks of types B1 and B2 to "75%" and the operation performance corresponding to the virtual block of type C to "50%". That is to say, accessing the memory module 122 through the virtual block of type A can perfectly achieve the highest efficiency. Compared with the virtual block of type A, accessing the memory module 122 through the virtual block of type B1 or B2 can only achieve "75%" of the highest efficiency (i.e., medium efficiency). In addition, compared with the virtual block of type A, accessing the memory module 122 through the virtual block of type C can only achieve "50%" of the highest efficiency (i.e., the lowest efficiency).

[0070] In one embodiment, the memory control circuit 23 can determine whether a physical block (also referred to as a target physical block) in the memory module 122 belongs to a first type of physical block or a second type of physical block. For example, a first type of physical block refers to a bad block in the memory module 122, while a second type of physical block refers to a good block in the memory module 122. In one embodiment, the target physical block can be used to refer to any physical block in the memory module 122.

[0071] In one embodiment, the wear level of the first type of physical block is higher than that of the second type of physical block. In one embodiment, the memory control circuit 23 can obtain a wear level assessment value corresponding to the target physical block. This wear level assessment value may be positively correlated with the wear level of the target physical block. The memory control circuit 23 can determine whether this wear level assessment value is higher than a threshold value (also called a wear threshold). If this wear level assessment value is higher than the wear threshold value, the memory control circuit 23 can determine that the target physical block belongs to the first type of physical block. However, if this wear level assessment value is not higher than the wear threshold value, the memory control circuit 23 can determine that the target physical block belongs to the second type of physical block.

[0072] In one embodiment, the memory control circuit 23 may acquire usage information corresponding to a target physical block. This usage information may reflect the usage level of the target physical block. The usage level of the target physical block may be positively correlated with the wear and tear of the target physical block. For example, this usage information may include at least one of read counts, write counts, erase counts, and bit error rates corresponding to the target physical block. The read count may reflect the number of times a read operation has been performed on the target physical block. This read operation is used to read data from the target physical block. The write count may reflect the number of times a write operation has been performed on the target physical block. This write operation is used to write data into the target physical block. The erase count may reflect the number of times an erase operation has been performed on the target physical block. This erase operation is used to erase data from the target physical block. The bit error rate may reflect the bit error rate of the data read from the target physical block.

[0073] In one embodiment, the memory control circuit 23 may determine a wear level assessment value corresponding to the target physical block based on this usage information. For example, this wear level assessment value may be positively correlated with the read count, write count, erase count, and / or bit error rate corresponding to the target physical block. In one embodiment, the memory control circuit 23 may also determine the wear level assessment value corresponding to the target physical block based on other information (such as temperature information, etc.), which will not be elaborated here.

[0074] In one embodiment, writing new data to a first-class entity block is prohibited. That is, if a target entity block is determined to belong to the first-class entity block, the memory control circuit 23 may prevent data (i.e., new data) from being written to the target entity block. For example, the memory control circuit 23 may set an entity block determined to be a first-class entity block to a write-protected state. If an entity block is in a write-protected state, data cannot be written to this entity block. However, if the target entity block is determined to belong to the second-class entity block, the memory control circuit 23 may allow data (i.e., new data) to be written to the target entity block.

[0075] In one embodiment, the memory control circuit 23 can acquire the distribution of the first type of entity blocks in multiple planes in real time. Based on the distribution of the first type of entity blocks in the multiple planes, the memory control circuit 23 can determine different candidate configuration strategies for multiple virtual blocks. Each virtual block contains multiple second type of entity blocks. In one embodiment, the distribution of the first type of entity blocks in the multiple planes can also be replaced by the distribution of the second type of entity blocks in the multiple planes.

[0076] In one embodiment, these different candidate configuration strategies can avoid first-type physical blocks (i.e., bad blocks) in memory module 122 by combining different types of virtual blocks; simultaneously, based on the type of each virtual block, each virtual block is mapped to multiple second-type physical blocks (i.e., good blocks). Multiple physical blocks mapped to the same virtual block can form a single virtual block. Furthermore, multiple physical blocks mapped to different virtual blocks can form multiple virtual blocks. Subsequently, memory control circuitry 23 can operate or access memory module 122 through these combinations of virtual blocks.

[0077] In one embodiment, based on the current distribution of the first type of entity blocks in multiple planes, under a certain candidate configuration strategy (also referred to as the first candidate configuration strategy), the memory control circuit 23 can configure multiple virtual blocks into a configuration including N virtual blocks of type A (also referred to as the first type of virtual blocks), M virtual blocks of type B1 and / or B2 (also referred to as the second type of virtual blocks) and P virtual blocks of type C (also referred to as the third type of virtual blocks).

[0078] On the other hand, based on the current distribution of the first type of entity blocks in multiple planes, under another candidate configuration strategy (also known as the second candidate configuration strategy), the memory control circuit 23 can configure multiple virtual blocks as including Q virtual blocks of type A (i.e., first type virtual blocks), R virtual blocks of type B1 and / or B2 (i.e., second type virtual blocks) and S virtual blocks of type C (i.e., third type virtual blocks).

[0079] In one embodiment, N, M, P, Q, R, and S must satisfy at least one of the following conditions: (1) N is different from Q; (2) M is different from R; (3) P is different from S. In other words, under different candidate configuration strategies, the configuration methods for the entire (or all) virtual blocks in the memory module 122 can be different from each other.

[0080] In one embodiment, compared to the first candidate configuration strategy, in the second candidate configuration strategy, at least one type A virtual block (i.e., a first-class virtual block) and at least one type C virtual block (i.e., a third-class virtual block) can be replaced by multiple types B1 and / or B2 virtual blocks (i.e., second-class virtual blocks). Alternatively, compared to the first candidate configuration strategy, in the second candidate configuration strategy, at least one type A virtual block (i.e., a first-class virtual block) and at least one type C virtual block (i.e., a third-class virtual block) can be reorganized into multiple types B1 and / or B2 virtual blocks (i.e., second-class virtual blocks).

[0081] In one embodiment, based on the distribution of the first type of physical blocks across multiple planes, the memory control circuit 23 can reorganize the two type A virtual blocks and one type C virtual block originally under the first candidate configuration strategy into three type B1 and / or B2 virtual blocks under the second candidate configuration strategy. This improves the performance and / or operational stability of subsequent access to the memory module 122 based on the configured virtual blocks.

[0082] For example, in one embodiment, based on the distribution of the first type of entity blocks across multiple planes, under a first candidate configuration strategy, the memory control circuit 23 can configure multiple virtual blocks to include 50 virtual blocks of type A, 15 virtual blocks of type B1 and / or B2, and 5 virtual blocks of type C. Furthermore, based on the same distribution of the first type of entity blocks across multiple planes, under a second candidate configuration strategy, the memory control circuit 23 can configure multiple virtual blocks to include 40 virtual blocks of type A, 30 virtual blocks of type B1 and / or B2, and 0 virtual blocks of type C (i.e., under the second candidate configuration strategy, the configured virtual blocks may not include virtual blocks of type C). In other words, the memory control circuit 23 can reorganize the original 10 virtual blocks of type A and 5 virtual blocks of type C under the first candidate configuration strategy into 15 virtual blocks of type B1 and / or B2 under the second candidate configuration strategy. This eliminates at least some of the virtual blocks in the memory module 122 with extremely high performance.

[0083] In one embodiment, a plurality of entity blocks in a first type of virtual block are located on a first number of planes, a plurality of entity blocks in a second type of virtual block are located on a second number of planes, and a plurality of entity blocks in a third type of virtual block are located on a third number of planes. The first number may be greater than the third number, and the second number may be between the first number and the third number.

[0084] by Figure 5 For example, the first quantity can be "4", the second quantity can be "2" or "3", and the third quantity can be "1". However, if the specifications of the memory module 122 are changed (e.g., the number of planes located in the single chip enable region of the memory module 122 is changed), the first quantity, the second quantity, and the third quantity can all be adjusted according to practical needs, and the present invention does not impose any restrictions.

[0085] In one embodiment, the operational performance of a second type of virtual block is between that of a first type of virtual block and that of a third type of virtual block. Figure 6For example, assuming a virtual block of type A (i.e., the first type of virtual block) is used as the benchmark, and the operation performance corresponding to a virtual block of type A is set to "100%" (i.e., the highest efficiency), then the operation performance corresponding to a virtual block of type B1 or B2 (i.e., the second type of virtual block) is about "75%" (i.e., medium efficiency), and the operation performance corresponding to a virtual block of type C (i.e., the third type of virtual block) is about "50%" (i.e., the lowest efficiency).

[0086] In one embodiment, the memory control circuit 23 can acquire performance evaluation information corresponding to different candidate configuration strategies. Based on this performance evaluation information, the memory control circuit 23 can determine a configuration strategy (also referred to as a target configuration strategy) from multiple different candidate configuration strategies. Subsequently, the memory control circuit 23 can configure multiple virtual blocks based on this target configuration strategy and operate (e.g., access) the memory module 122 based on the configured virtual blocks. This effectively improves the operational performance and / or operational stability of the storage device 12.

[0087] In one embodiment, the memory control circuit 23 can obtain performance evaluation information corresponding to a first candidate configuration strategy (also referred to as first performance evaluation information) and performance evaluation information corresponding to a second candidate configuration strategy (also referred to as second performance evaluation information) based on performance evaluation information (e.g., PER(A), PER(B1), PER(B2), and PER(C)) corresponding to different types of virtual blocks. Then, the memory control circuit 23 can determine one of the first candidate configuration strategy and the second candidate configuration strategy as the target configuration strategy based on the numerical relative relationship between the first performance evaluation information and the second performance evaluation information.

[0088] In one embodiment, the first performance evaluation information may reflect the total operational performance (also referred to as the first total operational performance) corresponding to at least one first-type virtual block and at least one third-type virtual block under the first candidate configuration strategy. For example, the first performance evaluation information may reflect the total operational performance (i.e., the first total operational performance) corresponding to 2 (or 2×K) type A virtual blocks and 1 (or K) type C virtual blocks under the first candidate configuration strategy. Furthermore, the second performance evaluation information may reflect the total operational performance (also referred to as the second total operational performance) corresponding to multiple second-type virtual blocks under the second candidate configuration strategy. For example, the second performance evaluation information may reflect the total operational performance (i.e., the second total operational performance) corresponding to 3 (or 3×K) type B1 and / or B2 virtual blocks under the second candidate configuration strategy. K can be any integer. It should be noted that if the specifications of the memory module 122 are changed (e.g., the number of planes located in the single chip enable region of the memory module 122 is changed), the method of obtaining the aforementioned performance evaluation information (e.g., the first performance evaluation information and the second performance evaluation information) can be adjusted according to practical needs, and the present invention does not impose any restrictions.

[0089] In one embodiment, the memory control circuit 23 can compare first performance evaluation information with second performance evaluation information to obtain a numerical relative relationship between the two. This numerical relative relationship can reflect that the first performance evaluation information is greater than, less than, or equal to the second performance evaluation information. In other words, this numerical relative relationship can reflect that the first total operating performance is greater than, less than, or equal to the second total operating performance. Then, the memory control circuit 23 can determine the first candidate configuration strategy or the second candidate configuration strategy as the target configuration strategy based on this numerical relative relationship.

[0090] In one embodiment, if the numerical relationship reflects that the first overall operating performance is better than the second overall operating performance, the memory control circuit 23 can determine the first candidate configuration strategy as the target configuration strategy. Furthermore, if the numerical relationship reflects that the first overall operating performance is not better than the second overall operating performance, the memory control circuit 23 can determine the second candidate configuration strategy as the target configuration strategy.

[0091] In one embodiment, the memory control circuit 23 may obtain the first performance evaluation information and the second performance evaluation information based on the following formulas (5) and (6).

[0092]

[0093] In formulas (5) and (6), TPER(1) can represent the first performance evaluation information, and TPER(2) can represent the second performance evaluation information. Furthermore, PER(B1) can be replaced by PER(B2). It should be noted that formulas (5) and (6) can also be adjusted according to practical needs, and this invention does not impose any limitations on them.

[0094] In one embodiment, the memory control circuit 23 can compare TPER(1) and TPER(2) and obtain a comparison result (i.e., the numerical relative relationship between the first performance evaluation information and the second performance evaluation information). If TPER(1) is greater than TPER(2), it means that the time required to access the memory module 122 by using 2 (or 2×K) virtual blocks of type A combined with 1 (or K) virtual blocks of type C is more than the time required to access the memory module 122 by using 3 (or 3×K) virtual blocks of type B1 and / or B2. In this case, the memory control circuit 23 can determine that the second overall operating performance is better than the first overall operating performance. In response to the second overall operating performance being better than the first overall operating performance, the memory control circuit 23 can determine the second candidate configuration strategy as the target configuration strategy.

[0095] On the other hand, if TPER(1) is not greater than TPER(2) (e.g., TPER(1) is less than or equal to TPER(2)), it means that the time required to access the memory module 122 using 2 (or 2×K) virtual blocks of type A combined with 1 (or K) virtual blocks of type C is no more than the time required to access the memory module 122 using 3 (or 3×K) virtual blocks of type B1 and / or B2. In this case, the memory control circuit 23 can determine that the second overall operating performance is not better than the first overall operating performance. In response to the second overall operating performance being not better than the first overall operating performance, the memory control circuit 23 can determine the first candidate configuration strategy as the target configuration strategy.

[0096] In one embodiment, compared to the first candidate configuration strategy, by reorganizing virtual blocks with extremely high operating performance (e.g., first-type and third-type virtual blocks) under the second candidate configuration strategy, more virtual blocks with moderate operating performance (e.g., second-type virtual blocks) can be obtained, and at least some of the virtual blocks with extremely high performance can be eliminated. Therefore, the operational stability of the storage device 12 can be effectively improved without affecting (or even improving) its operational performance.

[0097] In one embodiment, after determining the target configuration strategy, the memory control circuit 23 can select multiple entity blocks belonging to the second type of entity blocks from multiple planes in the memory module 122 according to the target configuration strategy to construct multiple virtual blocks. For example, the constructed virtual blocks can meet the type and quantity requirements for multiple virtual blocks under the target configuration strategy.

[0098] In one embodiment, after determining the target configuration strategy, the memory control circuit 23 can establish a virtual block mapping table (also referred to as a first type of virtual block mapping table) for a single physical region according to the target configuration strategy. For example, a single physical region may refer to a single chip enable region in the memory module 122. For example, the first type of virtual block mapping table can be used to record operation type information of multiple virtual blocks for a single physical region.

[0099] In one embodiment, it is assumed that the memory module 122 includes two chip enable regions CE(0) and CE(1). The memory control circuit 23 can establish a first type of virtual block mapping table corresponding to the chip enable region CE(0) according to a target configuration strategy (also referred to as a first target configuration strategy) for the chip enable region CE(0). For example, the first type of virtual block mapping table corresponding to the chip enable region CE(0) can be used to record operation type information of multiple virtual blocks for the chip enable region CE(0).

[0100] On the other hand, the memory control circuit 23 can also establish a first type of virtual block mapping table corresponding to the chip enable region CE (1) according to the target configuration strategy (also known as the second target configuration strategy) for the chip enable region CE (1). For example, the first type of virtual block mapping table corresponding to the chip enable region CE (1) can be used to record the operation type information of multiple virtual blocks for the chip enable region CE (1).

[0101] Figure 7 This is a schematic diagram of a first type of virtual block mapping table according to an embodiment of the present invention. Please refer to... Figure 7 In one embodiment, it is assumed that the target configuration strategy corresponding to the chip enable region CE(0) is the first candidate configuration strategy. The memory control circuit 23 can establish a first type of virtual block mapping table 71 according to the target configuration strategy (i.e., the first candidate configuration strategy) corresponding to the chip enable region CE(0).

[0102] In one embodiment, a first type of virtual block mapping table 71 can be used to record operation type information corresponding to multiple virtual blocks. These virtual blocks are all mapped to physical blocks located in the chip enable region CE(0). For example, the first type of virtual block mapping table 71 can record that first type of virtual blocks VB(1)-VB(50) correspond to first type of operation, second type of virtual blocks VB(51)-VB(65) correspond to second type of operation, and third type of virtual blocks VB(66)-VB(70) correspond to third type of operation.

[0103] In one embodiment, assuming that a single chip enable region in memory module 122 contains four planes, then the first type of operation refers to a four-plane operation, the second type of operation refers to a two-plane operation, and the third type of operation refers to a single-plane operation. It should be noted that if the specifications of memory module 122 change (e.g., the number of planes located in the single chip enable region of memory module 122 changes), the aforementioned first, second, and / or third types of operations can also be adjusted according to practical needs, and this invention does not impose any limitations.

[0104] In one embodiment, in a four-plane operation performed on any of the first type of virtual blocks VB(1)-VB(50), entity blocks distributed across the four planes (e.g., PL(0)-PL(3)) can be accessed synchronously or sequentially. In a two-plane operation performed on any of the second type of virtual blocks VB(51)-VB(65), entity blocks distributed across the two planes (e.g., PL(0) and PL(1) or PL(2) and PL(3) etc.) can be accessed synchronously or sequentially. In a single-plane operation performed on any of the third type of virtual blocks VB(66)-VB(70), entity blocks located in a single plane (e.g., any of PL(0)-PL(3)) can be accessed sequentially.

[0105] In one embodiment, two two-plane operations performed on the same virtual block can also be replaced by a three-plane operation and a single-plane operation. Furthermore, descriptions of the first, second, and / or third types of operations can also be found in [reference needed]. Figure 5 and Figure 6 The embodiments are not repeated here.

[0106] Figure 8 This is a schematic diagram of a first type of virtual block mapping table according to an embodiment of the present invention. Please refer to... Figure 8 In one embodiment, it is assumed that the target configuration strategy corresponding to the chip enable region CE(0) is the second candidate configuration strategy. The memory control circuit 23 can establish a first type of virtual block mapping table 81 according to the target configuration strategy (i.e., the second candidate configuration strategy) corresponding to the chip enable region CE(0).

[0107] In one embodiment, a first type of virtual block mapping table 81 can be used to record operation type information corresponding to multiple virtual blocks. These virtual blocks are all mapped to physical blocks located in the chip enable region CE(0). For example, the first type of virtual block mapping table 81 can record that first type virtual blocks VB(1)-VB(40) correspond to first type operations, and second type virtual blocks VB(41)-VB(70) correspond to second type operations. The details of the first type and second type operations have been described above and will not be repeated here.

[0108] In one embodiment, the memory control circuit 23 can sort (also referred to as first sorting) multiple planes in the memory module 122 according to the total number of second-type entity blocks contained in each plane. For example, the memory control circuit 23 can perform first sorting on multiple planes from most to least according to the total number of second-type entity blocks contained in each plane.

[0109] In one embodiment, the memory control circuit 23 can sort (also referred to as a second sorting) multiple entity blocks located on the same plane according to the type of each entity block located on each plane in the memory module 122. For example, the memory control circuit 23 can logically move the second type of entity blocks before the first type of entity blocks according to the total number of second type entity blocks contained in each plane, so as to perform a second sorting of multiple entity blocks located on the same plane.

[0110] Figure 9 This is a schematic diagram illustrating the sorting of planes and solid blocks according to an embodiment of the present invention. Please refer to... Figure 9Taking the chip enable region CE(0) as an example, the memory control circuit 23 can sort the planes PL(0)-PL(3) in the chip enable region CE(0) according to the total number of second-type entity blocks contained in each plane PL(0)-PL(3) (i.e., the first sorting). For example, assume that the total number of second-type entity blocks on the planes PL(0)-PL(3) is "100", "70", "60" and "50" in sequence. Through the first sorting, from left to right, the total number of second-type entity blocks on the planes PL(0)-PL(3) decreases in sequence.

[0111] On the other hand, the memory control circuit 23 can sort the entity blocks located in each plane according to the type of entity blocks contained in each plane PL(0)-PL(3) in the chip enable region CE(0) (i.e., a second sorting). For example, through the second sorting, second-type entity blocks on each plane can be logically moved (or grouped) before first-type entity blocks. Figure 9 For example, the second type of entity block may include at least entity blocks PB(0)-PB(202).

[0112] In one embodiment, the memory control circuit 23 can select multiple entity blocks belonging to the second type of entity blocks from multiple planes according to the aforementioned first type of virtual block mapping table, combined with the results of the first and second sorting, to construct multiple virtual blocks. For example, based on the results of the first and second sorting, the memory control circuit 23 can establish a sorting table 91. The sorting table 91 can present the sorting results of the first and second sorting. The memory control circuit 23 can select the required entity blocks from the second type of entity blocks located in each plane in the sorting table 91 according to the first type of virtual block mapping table to construct the corresponding virtual blocks in the first type of virtual block mapping table.

[0113] by Figure 7 and Figure 9 For example, the memory control circuit 23 can select one physical block from each of the planes PL(0)-PL(3) according to the sorting table 91 to form the first type of virtual block VB(1) in the first type of virtual block mapping table 81. The memory control circuit 23 can repeat the operation of selecting one physical block from each of the planes PL(0) and PL(1) twice according to the sorting table 91 to form the second type of virtual block VB(51) in the first type of virtual block mapping table 81. In addition, the memory control circuit 23 can select four physical blocks separately from the plane PL(0) according to the sorting table 91 to form the third type of virtual block VB(66).

[0114] In one embodiment, the memory control circuit 23 can record the mapping relationship between the selected physical blocks and the corresponding virtual blocks. For example, assuming that the memory control circuit 23 selects physical blocks PB(0)-PB(3) to form a first type of virtual block VB(1), then the memory control circuit 23 can record the mapping relationship between physical blocks PB(0)-PB(3) and the first type of virtual block VB(1) (i.e., the first type of virtual block VB(1) contains physical blocks PB(0)-PB(3)), and so on. Thus, the construction of multiple virtual blocks for a single physical region is completed.

[0115] In one embodiment, the memory control circuit 23 can establish a second type of virtual block mapping table for multiple physical regions based on the first type of virtual block mapping table. For example, the memory control circuit 23 can combine multiple first type of virtual block mapping tables corresponding to different physical regions into a second type of virtual block mapping table. Subsequently, the memory control circuit 23 can perform operational optimization (also known as mapping tuning) on ​​the pre-constructed virtual blocks for different physical regions based on the second type of virtual block mapping table.

[0116] Figure 10 This is a schematic diagram of a second type of virtual block mapping table according to an embodiment of the present invention. Please refer to... Figure 10 Assume that memory module 122 contains two chip enable regions CE(0) and CE(1). Memory control circuit 23 can automatically generate a second type of virtual block mapping table 1001 based on multiple first type virtual block mapping tables corresponding to chip enable regions CE(0) and CE(1) respectively.

[0117] In one embodiment, the second type of virtual block mapping table 1001 can be used to record the total number of various types of virtual blocks, operation type, and mapping relationship between each virtual block and multiple physical blocks for each physical region (e.g., chip enable regions CE(0) and CE(1)).

[0118] by Figure 10 For example, the second type of virtual block mapping table 1001 can record that for the chip enable region CE(0), the total number of the first type of virtual blocks is 40 and the total number of the second type of virtual blocks is 30; for the chip enable region CE(1), the total number of the first type of virtual blocks is 50 and the total number of the second type of virtual blocks is 30.

[0119] In addition, the second type of virtual block mapping table 1001 may also record that, for the first type of virtual block corresponding to the chip enable region CE(0), virtual block VB(1) supports the first type of operation and is mapped to the physical blocks PB(0)-PB(3) scattered in the four planes PL(0)-PL(3), and virtual block VB(2) supports the first type of operation and is mapped to the physical blocks PB(4)-PB(7) scattered in the four planes PL(0)-PL(3), and so on;

[0120] For the second type of virtual block corresponding to the chip enable region CE(0), the virtual block VB(1) supports the second type of operation and is mapped to the physical blocks PB(8), PB(9), PB(12) and PB(13) located in the two planes PL(0) and PL(1), and the virtual block VB(2) supports the second type of operation and is mapped to the physical blocks PB(16), PB(17), PB(20) and PB(21) located in the two planes PL(0) and PL(1), and so on;

[0121] For the first type of virtual block corresponding to the chip enable region CE(1), the virtual block VB(1) supports the first type of operation and is mapped to the physical blocks PB(0)-PB(3) scattered in the four planes PL(0)-PL(3), and the virtual block VB(2) supports the first type of operation and is mapped to the physical blocks PB(4)-PB(7) scattered in the four planes PL(0)-PL(3), and so on;

[0122] Furthermore, for the second type of virtual block corresponding to the chip enable region CE(1), the virtual block VB(1) supports the second type of operation and is mapped to the physical blocks PB(8), PB(9), PB(12) and PB(13) located in the two planes PL(0) and PL(1), and the virtual block VB(2) supports the second type of operation and is mapped to the physical blocks PB(16), PB(17), PB(20) and PB(21) located in the two planes PL(0) and PL(1), and so on.

[0123] In one embodiment, the memory control circuit 23 can pair multiple virtual blocks of the same type for different physical regions according to a first type of virtual block mapping table. Figure 10For example, the memory control circuit 23 can pair first-type virtual blocks for chip enable region CE(0) with first-type virtual blocks for chip enable region CE(1) according to a first-type virtual block mapping table corresponding to different physical regions (e.g., aligning the same virtual block in the second-type virtual block mapping table), to facilitate cross-physical region synchronization operations through these virtual blocks of the same type. Similarly, the memory control circuit 23 can pair second-type virtual blocks for chip enable region CE(0) with second-type virtual blocks for chip enable region CE(1) according to a first-type virtual block mapping table corresponding to different physical regions (e.g., aligning the same virtual block in the second-type virtual block mapping table), to facilitate cross-physical region synchronization operations through these virtual blocks of the same type. This improves the operational efficiency and / or operational stability of accessing the memory module 122 through these virtual blocks.

[0124] In one embodiment, the memory control circuit 23 can optimize the mapping of multiple virtual blocks for different physical regions according to a second type of virtual block mapping table. For example, the memory control circuit 23 can adjust the access operations corresponding to multiple virtual blocks for different physical regions to support interleaved access across physical regions according to the second type of virtual block mapping table. This can improve the operational efficiency of accessing the memory module 122 through these virtual blocks.

[0125] Figure 11 This is a schematic diagram illustrating mapping optimization according to an embodiment of the present invention. Please refer to... Figure 11 In one embodiment, the memory control circuit 23 can perform mapping tuning for virtual block VB(i+1) according to the second type of virtual block mapping table.

[0126] In one embodiment, before performing mapping optimization on the virtual block VB(i+1), if the virtual block VB(i+1) is used to continuously access the chip enable regions CE(0) and CE(1), the memory control circuit 23 will perform two two-plane operations (i.e., the second type of operation) on planes PL(0) and PL(1) in the chip enable region CE(0). Then, the memory control circuit 23 will continue to perform two two-plane operations (i.e., the second type of operation) on planes PL(0) and PL(1) in the chip enable region CE(1). Thus, during the period when two two-plane operations are performed on planes PL(0) and PL(1) in the chip enable region CE(0), the chip enable region CE(1) is idle, resulting in wasted performance.

[0127] In one embodiment, after performing mapping optimization on the virtual block VB(i+1), the memory control circuit 23 can adjust the two-plane operations that originally required sequential execution on the chip enable regions CE(0) and CE(1) to support interleaved access across physical regions. For example, after performing mapping optimization on the virtual block VB(i+1), the memory control circuit 23 can adjust the two-plane operations that originally required sequential execution on the chip enable regions CE(0) and CE(1) to support interleaved access across physical regions. Figure 11 The following operations are performed sequentially using the sequence markers in the chip enable region CE(0): (1) two-plane operations on planes PL(0) and PL(1) in the chip enable region CE(0); (2) two-plane operations on planes PL(0) and PL(1) in the chip enable region CE(1); (3) two-plane operations on planes PL(0) and PL(1) in the chip enable region CE(0); and (4) two-plane operations on planes PL(0) and PL(1) in the chip enable region CE(1). Thus, during access to the memory module 122 via the virtual block VB(i+1), the chip enable regions CE(0) and CE(1) can be accessed interleaved, thereby improving the operational performance of the memory module 122.

[0128] In one embodiment, the memory control circuit 23 can determine, according to the second type of virtual block mapping table, whether the total number of access operations (also called target access operations) corresponding to a certain virtual block (also called target virtual block) is the same as the total number of multiple physical regions. In response to the total number of target access operations corresponding to the target virtual block being different from the total number of multiple physical regions, the memory control circuit 23 can trigger mapping optimization for the target virtual block. Conversely, if the total number of target access operations corresponding to the target virtual block is the same as the total number of multiple physical regions, the memory control circuit 23 may not trigger mapping optimization for the target virtual block.

[0129] by Figure 11 For example, for virtual block (i), the total number of access operations corresponding to virtual block (i) is "2" (i.e., the first type of operation is executed once for each of the chip enable regions CE(0) and CE(1), and the total number of chip enable regions CE(0) and CE(1) is "2". In response to the fact that the total number of access operations corresponding to virtual block (i) (i.e., "2") is the same as the total number of chip enable regions CE(0) and CE(1) (i.e., "2"), the memory control circuit 23 may not trigger mapping tuning of virtual block (i).

[0130] However, for virtual block (i+1), the total number of access operations corresponding to virtual block (i+1) is "4" (i.e., two second-type operations are performed for each of the chip enable regions CE(0) and CE(1), and the total number of chip enable regions CE(0) and CE(1) is "2". In response to the fact that the total number of access operations corresponding to virtual block (i) (i.e., "4") is different from the total number of chip enable regions CE(0) and CE(1) (i.e., "2"), the memory control circuit 23 can trigger the above-mentioned mapping optimization for virtual block (i+1). This improves the operational performance of the memory module 122.

[0131] Figure 12 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 12 In step S1201, based on the distribution of the first type of entity blocks in multiple planes, different candidate configuration strategies are determined for multiple virtual blocks, where each virtual block contains multiple second type of entity blocks. In step S1202, performance evaluation information corresponding to different candidate configuration strategies is obtained. In step S1203, based on the performance evaluation information, a target configuration strategy is determined from the different candidate configuration strategies.

[0132] However, Figure 12 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 12 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 12 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0133] In summary, the memory management method and storage device proposed in this invention can dynamically determine different candidate configuration strategies for multiple virtual blocks in a memory module based on the distribution of first-type physical blocks (e.g., bad blocks) across multiple planes, where each virtual block can contain multiple second-type physical blocks (e.g., good blocks). Then, based on performance evaluation information corresponding to different candidate configuration strategies, an appropriate target configuration strategy can be automatically determined from these candidate strategies. Therefore, regardless of the current health status of the storage device (e.g., whether the memory modules within the storage device are in the early, middle, or late stages of their lifecycle), the performance and operational stability of the storage device can be maintained or even significantly improved.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, include: Based on the distribution of the first type of entity blocks in multiple planes, different candidate configuration strategies are determined for multiple virtual blocks, where each virtual block contains multiple second type of entity blocks; Obtain performance evaluation information corresponding to the different candidate configuration strategies; and Based on the performance evaluation information, a target configuration strategy is determined from the different candidate configuration strategies. The different candidate configuration strategies include a first candidate configuration strategy and a second candidate configuration strategy. Compared to the first candidate configuration strategy, in the second candidate configuration strategy, at least one first-type virtual block and at least one third-type virtual block are replaced by multiple second-type virtual blocks. Multiple entity blocks in a first type of virtual block are located on a first number of planes, multiple entity blocks in a second type of virtual block are located on a second number of planes, and multiple entity blocks in a third type of virtual block are located on a third number of planes, wherein the first number is greater than the third number, and the second number is between the first number and the third number.

2. The memory management method according to claim 1, characterized in that, The operational performance of the second type of virtual block is between that of the first type of virtual block and that of the third type of virtual block.

3. The memory management method according to claim 1, characterized in that, The performance evaluation information includes first performance evaluation information corresponding to a first candidate configuration strategy and second performance evaluation information corresponding to a second candidate configuration strategy. The step of determining the target configuration strategy from the different candidate configuration strategies based on the performance evaluation information includes: Based on the numerical relative relationship between the first performance evaluation information and the second performance evaluation information, one of the first candidate configuration strategy and the second candidate configuration strategy is determined as the target configuration strategy.

4. The memory management method according to claim 3, characterized in that, The first performance evaluation information reflects the first total operational performance corresponding to the at least one first type of virtual block and the at least one third type of virtual block, and the second performance evaluation information reflects the second total operational performance corresponding to the plurality of second type of virtual blocks.

5. The memory management method according to claim 4, characterized in that, The step of determining one of the first candidate configuration strategy and the second candidate configuration strategy as the target configuration strategy based on the numerical relative relationship between the first performance evaluation information and the second performance evaluation information includes: If the numerical relative relationship reflects that the second overall operational performance is better than the first overall operational performance, the second candidate configuration strategy is determined as the target configuration strategy; and If the relative numerical relationship reflects that the second overall operational performance is not better than the first overall operational performance, the first candidate configuration strategy is determined as the target configuration strategy.

6. The memory management method according to claim 1, further comprising: According to the target configuration strategy, multiple entity blocks belonging to the second type of entity blocks are selected from the multiple planes to construct the multiple virtual blocks.

7. The memory management method according to claim 6, characterized in that, The step of selecting the plurality of entity blocks belonging to the second type of entity blocks from the plurality of planes to construct the plurality of virtual blocks according to the target configuration strategy includes: Based on the target configuration strategy, a first type of virtual block mapping table is established for a single entity region. The first type of virtual block mapping table can be used to record operation type information for multiple virtual blocks of the single entity region.

8. The memory management method according to claim 7, characterized in that, The step of selecting the plurality of entity blocks belonging to the second type of entity blocks from the plurality of planes to construct the plurality of virtual blocks according to the target configuration strategy further includes: The multiple planes are sorted in a first order based on the total number of second-type entity blocks contained in the multiple planes; Based on the type of each entity block on each plane, a second sorting is performed on multiple entity blocks located on the same plane; and Based on the first type of virtual block mapping table, and in conjunction with the results of the first sorting and the second sorting, the plurality of entity blocks belonging to the second type of entity blocks are selected from the plurality of planes to construct the plurality of virtual blocks.

9. The memory management method according to claim 7, characterized in that, Also includes: Based on the first type of virtual block mapping table, a second type of virtual block mapping table is established for multiple entity regions; as well as Based on the second type of virtual block mapping table, the mapping of multiple virtual blocks for different entity regions is optimized.

10. The memory management method according to claim 9, characterized in that, The mapping optimization includes: The access operations corresponding to the multiple virtual blocks in the different entity regions are adjusted to support interleaved access across entity regions.

11. The memory management method according to claim 9, characterized in that, The second type of virtual block mapping table is used to record the total number of virtual blocks of various types for each entity region and the mapping relationship between the virtual blocks of various types and multiple entity blocks.

12. The memory management method according to claim 9, characterized in that, The steps for mapping optimization of the multiple virtual blocks for the different entity regions according to the second type of virtual block mapping table include: In response to the fact that the total number of multiple target access operations corresponding to the target virtual block is different from the total number of the multiple entity regions, a mapping optimization of the target virtual block is triggered.

13. The memory management method according to claim 9, characterized in that, The steps for establishing the second type of virtual block mapping table based on the first type of virtual block mapping table include: Based on the first type of virtual block mapping table, multiple virtual blocks of the same type for different entity regions will be paired.

14. The memory management method according to claim 1, characterized in that, The first type of entity block suffers a higher degree of damage than the second type of entity block.

15. The memory management method according to claim 1, characterized in that, New data is prohibited from being written to the first type of entity block.

16. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to perform the memory management method as described in any one of claims 1 to 15.

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