Bus transmission apparatus, system and method and multi-chip system

Abstract

The embodiment of the present disclosure provides a bus transmission device, a system and a method and a multi-chip system, and the bus transmission device comprises the following parts: a communication module; a first bus interface connected between one or more functional modules of a first chip and the communication module; a second bus interface connected between a second chip and the communication module; a last-in first-out storage module connected between the communication module and the first bus interface and configured to be read by the functional module through the first bus interface; the communication module is used for receiving a read operation instruction sent by the functional module through the first bus interface, the read operation instruction is used for reading data of a readable module in the second chip; the read operation instruction is encoded to be sent through the second bus interface; the data sent by the second chip received through the second bus interface is decoded, and the decoded data is written into the last-in first-out storage module. The embodiment of the present disclosure can avoid the mismatch between data and the read operation instruction caused by interruption.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a bus transmission device, system, method, and multi-chip system. Background Technology

[0002] In multi-chip systems, chips can share data. Moving parallel buses to ports results in too many interfaces and excessively large chip pad areas. In related technologies, multi-chip systems facilitate inter-chip interaction by converting the parallel buses within the chips into serial buses. However, converting bus access to a serial protocol takes a considerable amount of time. During this time, if an interrupt occurs that also requests access to another chip, the chip will be unable to distinguish whether the data received is needed by the interrupting process or the original process. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a bus transmission device, system, method, and multi-chip system to solve the above technical problems.

[0004] In a first aspect, embodiments of this disclosure provide a bus transmission device applied to a first chip, the first chip including one or more functional modules. The bus transmission device includes: a communication module; a first bus interface connected between the functional modules and the communication module; a second bus interface connected between the second chip and the communication module; a last-in-first-out (LIFO) storage module connected between the communication module and the first bus interface, configured for read operations to be performed by the functional modules via the first bus interface; the communication module is used to receive read operation instructions sent by the functional modules via the first bus interface, the read operation instructions being used to read data from a readable module in the second chip; to encode the read operation instructions for transmission via the second bus interface; to decode the data sent by the second chip via the second bus interface; and to write the decoded data into the LIFO storage module.

[0005] In some possible implementations, the above-mentioned functional module is used to obtain the amount of data already stored in the first-in-first-out (FIFO) storage module when sending a read operation command, determine the target data amount based on the amount of data already stored, and read data from the last-in-first-out (LIFO) storage module when the amount of data already stored is detected to be the target data amount, so as to obtain the data corresponding to the read operation command.

[0006] In some possible implementations, the above-described functional module is also used to determine that the second bus interface is in an idle state before sending a read operation command.

[0007] In some possible implementations, the communication module is specifically used to convert the address of the register to be operated into the number of the register to be operated; for read operation instructions, it is encoded into a read operation frame, which includes a frame length and the number of the register to be operated; for write operation instructions, it is encoded into a write operation frame, which includes a frame length, the number of the register to be operated, and the data to be written.

[0008] In some possible implementations, the read operation frame contains 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, and the second byte represents the low 8 bits of the register number to be operated on; the write operation frame contains at least 3 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, the second byte represents the low 8 bits of the register number to be operated on, and the remaining bytes represent the data to be written.

[0009] In some possible implementations, the communication module is further configured to receive write operation instructions sent by the functional module via a first bus interface, encode the write operation instructions for transmission via a second bus interface, and write data to a writable module in the second chip.

[0010] In some possible implementations, the communication module includes: an encoding / decoding unit connected to a first bus interface; a first first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and a second bus interface; and a second FIFO storage unit connected between the encoding / decoding unit and the second bus interface; wherein the encoding / decoding unit includes: The encoding unit is used to receive read operation instructions, encode the read operation instructions, and write the encoded read operation instructions into the second first-in-first-out (FIFO) storage unit for transmission via the second bus interface; the decoding unit is used to read data from the first FIFO storage unit, decode the read data, and write the decoded data into the last-in-first-out (LIFO) storage module.

[0011] In some possible implementations, the communication module further includes a configuration register connected between the first bus interface and the second bus interface, and between the first bus interface and the encoding / decoding unit, configured to transmit parameter configuration via the first bus interface by the functional module.

[0012] In some possible implementations, the first bus interface is a first bus slave interface, which is connected to the first bus master interface of the functional module; the second bus interface is a second bus master interface, which is connected to the second bus slave interface of the second chip; the first bus interface is a parallel bus interface, and the second bus interface is a serial bus interface.

[0013] Secondly, embodiments of this disclosure provide a bus transmission system, including: a master transmission device disposed on a first chip; and a slave transmission device disposed on a second chip; The main transmission device includes: a main communication module; a first bus slave interface connected between one or more functional modules of the first chip and the main communication module; a second bus master interface connected between the slave transmission device and the main communication module; a last-in-first-out (LIFO) storage module connected between the main communication module and the first bus slave interface, configured for read operations by functional modules via the first bus slave interface; the main communication module is used to receive read operation instructions sent by functional modules via the first bus slave interface, the read operation instructions being used to read data from readable modules in the second chip; to encode the read operation instructions for transmission via the second bus master interface; to decode the data received via the second bus master interface; and to write the decoded data into the LIFO storage module. The transmission device includes: a slave communication module; a second bus slave interface connected between the second bus master interface and the slave communication module; a first bus master interface connected between the slave communication module and one or more readable modules of the second chip, used for reading operations on the readable modules; the slave communication module is used to decode the read operation instructions received via the second bus slave interface and send the decoded read operation instructions to the first bus master interface for reading operations on the readable modules; and to encode the data sent via the first bus master interface for transmission via the second bus slave interface.

[0014] In some possible implementations, the above-mentioned functional module is used to obtain the amount of data already stored in the last-in-first-out (LIFO) storage module when sending a read operation command, determine the target data amount based on the amount of data already stored, and read data from the LIFO storage module when the amount of data already stored is detected to be the target data amount, so as to obtain the data corresponding to the read operation command.

[0015] In some possible implementations, the above-mentioned functional module is also used to determine that the second bus master interface is in an idle state before sending a read operation command.

[0016] In some possible implementations, the main communication module is further configured to receive write operation instructions sent by the functional module via the first bus slave interface, encode the write operation instructions for transmission via the second bus interface, and write data to the writable module in the second chip; the slave communication module is further configured to decode the write operation instructions received via the second bus slave interface and send the decoded write operation instructions to the first bus main interface to perform a write operation on the writable module.

[0017] In some possible implementations, the main communication module is specifically used to convert the address of the register to be operated into the register number to be operated; for read operation instructions, it is encoded into a read operation frame, the read operation frame containing a frame length and the register number to be operated; for write operation instructions, it is encoded into a write operation frame, the write operation frame containing a frame length, the register number to be operated, and the data to be written; the slave communication module is specifically used to convert the register number into the target register address when decoding the read operation instruction or the write operation instruction; and to encode the read data into a return frame, the return frame containing a frame length and the returned data.

[0018] In some possible implementations, the read operation frame contains 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, and the second byte represents the low 8 bits of the register number to be operated on; the write operation frame contains at least 3 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, the second byte represents the low 8 bits of the register number to be operated on, and the remaining bytes represent the data to be written; the return frame contains at least 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits are reserved fields, and the remaining bytes represent the returned data.

[0019] Thirdly, embodiments of this disclosure provide a multi-chip system, comprising: a first chip, the first chip including one or more functional modules and the aforementioned main transmission device; and a second chip, the second chip including one or more readable modules and the aforementioned slave transmission device.

[0020] Fourthly, this disclosure provides a bus transmission method applied to a first chip. The first chip includes one or more functional modules and the bus transmission device described above. The bus transmission method includes: when a functional module sends a read operation instruction, it obtains the amount of data already stored in the last-in-first-out (LIFO) storage module, determines a target data amount based on the amount of data already stored, and when the amount of data already stored is detected to be the target data amount, it reads data from the LIFO storage module to obtain data corresponding to the read operation instruction.

[0021] In some possible implementations, the amount of stored data is N, and the target amount of data is N+1.

[0022] In the technical solution provided in the embodiments of this disclosure, the bus communication device of the first chip stores the data obtained by the read operation instruction through the last-in-first-out storage unit, so that when an interrupt occurs, the interrupt process can read its corresponding data first, and then the original process can read its corresponding data, thus avoiding the mismatch between the data and the read operation instruction due to the interrupt.

[0023] These or other aspects of this disclosure will become more apparent in the following description of embodiments. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of the structure of the chip provided in the embodiments of this disclosure is shown.

[0026] Figure 2 A schematic diagram of a bus transmission device provided in an embodiment of this disclosure is shown.

[0027] Figure 3 A schematic diagram comparing the read operation process in uninterrupted and interrupted scenarios is shown.

[0028] Figure 4 A schematic diagram of the data structure provided in an embodiment of this disclosure is shown.

[0029] Figure 5 A schematic diagram of the composition structure of a communication module provided in an embodiment of this disclosure is shown.

[0030] Figure 6 A schematic diagram of a bus transmission system provided in an embodiment of this disclosure is shown.

[0031] Figure 7 A flowchart of a bus transmission method provided by an embodiment of this disclosure is shown. Detailed Implementation

[0032] The embodiments of this disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0033] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. To enable those skilled in the art to better understand the solutions of this disclosure, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] In this disclosure, it should be noted that relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0035] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] In the description of embodiments in this disclosure, terms such as "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in this disclosure is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of terms such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0037] Furthermore, in this disclosure, "multiple" refers to two or more. Therefore, in this disclosure, "multiple" can also be understood as "at least two." "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C could mean including A, B, C, A and B, A and C, B and C, or A and B and C. It should be noted that in this disclosure, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following associated objects have an "or" relationship.

[0038] It should be noted that in the embodiments of this disclosure, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0039] The embodiments of this disclosure provide a bus transmission device that can be applied to chips in a multi-chip system and can be used for data sharing between chips in a multi-chip system.

[0040] Please see Figure 1 As shown, a chip in a multi-chip system can include one or more functional modules, which can include one or more processing units. These processing units can include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural-network Processing Unit (NPU), a Digital Signal Processor (DSP), etc. The chip can also include storage units, such as registers, read-only memory, embedded flash memory, and random access memory (RAM). The chip can also include one or more IP cores. The processing units, storage units, and IP cores within the chip can be connected together via an internal interconnect bus to form a complete system. In a multi-chip system, a chip can read and write to the storage units and IP cores of other chips via a bus transmission device located within it. The internal interconnect bus is a parallel bus, such as an Advanced Dextensible Interface (AXI), an Advanced High-performance Bus (AHB), or an Advanced Peripheral Bus (APB).

[0041] For ease of description, the chip that initiates the read / write operation will be referred to as the first chip, and the chip that performs the read / write operation will be referred to as the second chip. Please refer to [link / reference]. Figure 2 As shown, the bus transmission device located on the first chip may include a first bus interface, a second bus interface, a communication module, and a last-in-first-out (LIFO) memory module. The first bus interface connects the functional modules of the chip to the communication module. For example, the first bus interface can connect the CPU, GPU, or NPU to the communication module. As an example, the CPU, GPU, or NPU has a first bus master interface, and the first bus interface in the bus transmission device is a first bus slave interface, controlled by the first bus master interface. The second bus interface connects the second chip to the communication module. As an example, the second bus interface in the bus transmission device is a second bus master interface, and the second chip has a second bus slave interface. The first bus interface can be a parallel bus interface such as AXI, AHB, or APB, and the second bus interface can be a serial bus interface such as SPI or I2C.

[0042] Please continue reading. Figure 2As shown, the communication module is used for protocol conversion between the first bus interface and the second bus interface. The communication module receives read operation instructions sent by functional modules (e.g., CPU, GPU, NPU, etc.) via the first bus interface. These read operation instructions are used to read data from readable modules (e.g., memory cells, IP cores, etc.) in the second chip. The communication module encodes the read operation instructions for transmission via the second bus interface. It decodes the data received from the second chip via the second bus interface and writes the decoded data into the Last-In-First-Out (LIFO) memory module. The LIFO memory module is connected between the communication module and the first bus interface and is configured for read operations by functional modules (e.g., CPU, GPU, NPU, etc.) of the first chip via the first bus interface. The LIFO memory module may include a stack, which stores and retrieves data in the order that the last written data is read first. The LIFO memory module has only one data port, which serves as both an input and an output port. The end where data is inserted or deleted is called the top of the stack, and the remaining end is called the bottom of the stack. Stack operations fall into three main categories: push, pop, and peek. A push operation adds an element to the top of the stack, a pop operation removes and returns the top element, and a peek operation returns the top element without removing it. In some possible implementations, the communication module is also used to receive write operation instructions sent by functional modules (e.g., CPU, GPU, NPU, etc.) via a first bus interface, encode the write operation instructions for transmission via a second bus interface, and use these instructions to write data to writable modules (e.g., memory units, IP cores, etc.) in a second chip.

[0043] In embodiments of this disclosure, the functional module may include parallel processes, where one process can interrupt another. The functional module, upon sending a read operation command, obtains the amount of data already stored in the last-in-first-out (LIFO) storage module, determines the target data amount based on the stored data amount, and, upon detecting that the stored data amount is the target data amount, reads data from the LIFO storage module to obtain the data corresponding to the read operation command. In a specific implementation, each read operation increases the amount of data already stored in the LIFO storage module by 1. That is, if the amount of data already stored before the read operation is N, then after one read operation, the amount of data already stored is N+1. If the functional module sends a read operation command when the amount of data already stored is N and detects that the amount of data already stored is N+2, it indicates that there are other read operation commands after sending this read operation command. As an example, the first process of the CPU sends a first read operation instruction when the amount of data stored in the last-in-first-out (LIFO) memory module is N. In response to the first read operation instruction, data read from the second chip is stored in the LIFO memory module, making the amount of stored data N+1. If an interrupt occurs before the first process reads data from the LIFO memory module, the second process sends a second read operation instruction. In response to the second read operation instruction, data read from the second chip is stored in the LIFO memory module, making the amount of stored data N+2. At this point, the first process detects that the amount of stored data is N+2, which is not its target storage amount (i.e., N+1), and does not read data from the LIFO memory module. The second process detects that the amount of stored data is N+2, which is its target storage amount (i.e., N+2), and reads data from the LIFO memory module, obtaining the data corresponding to the second read operation instruction (i.e., the N+2th data). After the second process reads the data, the amount of stored data in the LIFO memory module becomes N+1. The first process detects that the amount of stored data is N+1, which is its target storage quantity (i.e., N+1). It reads data from the last-in-first-out (LIFO) storage module to obtain the data corresponding to the first read operation instruction (i.e., the N+1th data). Based on this mechanism, when an interrupt occurs, the interrupted process can read its corresponding data first, and then the original process can read its corresponding data, avoiding mismatch between data and read operation instructions due to interruption.

[0044] In some implementations, the functional module also determines whether the second bus interface is in an idle state (also known as a non-communication state) before sending read and write operation commands, to avoid bus conflicts and data corruption. When the second bus interface uses a serial communication protocol, sending read and write operation commands after determining that the second bus interface is in an idle state can maintain protocol timing and state consistency. In some cases, after completing the previous operation, a certain processing time or state recovery may be required. Waiting for the bus to become idle means that it is fully ready to receive new commands, avoiding ignoring or misprocessing commands. In specific implementations, the functional module confirms whether the bus interface is idle through hardware detection, software delay, and querying the status register.

[0045] For example, please refer to Figure 3 As shown, Figure 3 (b) shows the data reading and writing process without interruption, presenting an overall process of reading and writing once. Figure 3 In diagram (b), the process uses a FIFO (First-In, First-Out) memory module as a temporary register. The main process accesses data 0 from the slave chip, and data 0 has already been filled into the FIFO memory module. If the main process has not yet read data from the FIFO memory module, then that data (i.e., data 0) will be retained in the FIFO memory module. If an interrupt needs to read data 1 from the slave chip, then the newly read data 1 will be stored in the FIFO memory module, but the interrupt will first retrieve data 0, causing it to retrieve incorrect data. Figure 3 Figure (c) shows the data reading process using a Last-In-First-Out (LIFO) memory module as a temporary register. For a read operation, it is necessary to first confirm whether there is communication transmission on the line. After the communication transmission ends, the amount of data N in the LIFO memory module is confirmed, and then the read operation is performed. After that, it waits again for the communication to end, and waits until the amount of data in the LIFO memory module is N+1. Then, the data in the LIFO memory module is retrieved, and this data is the data required by this process. Figure 3 In diagram (d), the interruption occurs. In this case, the main process (process 1) confirms that the data volume in the last-in-first-out (LIFO) memory module is 0, performs a read operation, and stores the data in the LIFO memory module. However, before the data is read from the LIFO memory module, an interrupt occurs. The interrupted process (process 2) needs to wait for the communication on the line to end, and then confirm that the data volume in the LIFO memory module is 1. After performing the read operation of the interrupt program, it needs to wait until the data volume in the LIFO memory module is 2 before it can retrieve the data from the LIFO memory module, which is the data needed by the interrupted process. After exiting the interrupt, the main program finds that the data volume in the LIFO memory module is 1, and can then retrieve the data from the LIFO memory module to obtain the data it needs. In the case of nested interrupts, this method ensures that all processes can retrieve the data they need.

[0046] In related technologies, read operation instructions, write operation instructions, and data are packaged with frame headers, frame trailers, and checksums, and then the packaged frames are sent out for reception by communication peripherals. This method is suitable for packaging large amounts of data, but if read and write operation instructions are packaged separately, the frame headers, frame information, and checksums become too redundant, which reduces the communication speed between the two chips. In some possible implementations, the communication module can convert the address of the register to be operated into the register number to reduce its data length. For read operation instructions, the communication module can encode them into read operation frames, which contain the frame length and the register number to be operated. For write operation instructions, the communication module can encode them into write operation frames, which contain the frame length, the register number to be operated, and the data to be written. As an example, a read operation frame contains 2 bytes, where the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated, and the second byte represents the low 8 bits of the register number to be operated. As an example, a write operation frame can contain at least 3 bytes, where the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, the second byte represents the low 8 bits of the register number to be operated on, and the remaining bytes represent the data to be written.

[0047] As an example, see Figure 4 The frame format used for data transmission shown is as follows: write operation frames are 6 bytes, read operation frames are 2 bytes, and return frames are 5 bytes. For write operation frames, the first 4 bits of the first byte frame represent the length of the entire frame in bytes. The last 4 bits of the first byte frame and the second byte are the register numbers to be operated on. The difference between register numbers and register addresses is that register numbers are in words, while register addresses are in bytes. Converting the address of the register to be operated on to the register number can shorten the frame length. The subsequent bytes then form the entire data being written. A total of 1 word of data is written. For read operation frames, the written data portion is not included, and for return frames, the register number portion is not included. Based on the frame format, as much information as possible can be transmitted with a smaller bit length. Assuming an SPI rate of 50 MHz, the longest frame is a write frame, not exceeding 6 bytes. Therefore, transmitting one APB operation takes 960 ns, plus data processing time, approximately 1 µs. The address bits are 12 bits, plus the offset address, for a total of 14 bits, thus ensuring that the bus can access approximately 16KB of address space at a rate of 1M.

[0048] For some possible implementations, please refer to Figure 5As shown, the communication module may include: an encoding / decoding unit connected to a first bus interface; a first first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and a second bus interface; and a second first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and the second bus interface. The encoding / decoding unit includes: an encoding unit for receiving read operation instructions, encoding the read operation instructions, and writing the encoded read operation instructions into the second first-in-first-out storage unit for transmission via the second bus interface; and a decoding unit for reading data from the first first-in-first-out storage unit, decoding the read data, and writing the decoded data into a last-in-first-out (LIFO) storage module. In some possible implementations, the communication module may further include: a configuration register connected between the first bus interface and the second bus interface, and between the first bus interface and the encoding / decoding unit, configured for the functional module to configure transmission parameters via the first bus interface, such as the transmission rate of the second bus interface and the access control of the encoding / decoding unit to the first bus interface.

[0049] Embodiments of this disclosure provide a bus transmission system; please refer to [link to relevant documentation]. Figure 6 As shown, the bus transmission system includes: a master transmission device disposed on the first chip; and a slave transmission device disposed on the second chip. The first and second chips may include one or more functional modules, which may include one or more processing units, such as CPUs, GPUs, NPUs, DSPs, and IP cores. The first and second chips may also include storage units, such as registers, read-only memory, embedded flash memory, and RAM. The first and second chips may also include one or more IP cores. The processing units, storage units, and IP cores within each chip can be connected together via an internal interconnect bus to form a complete system. In a multi-chip system, a chip can perform read and write operations on the storage units and IP cores of other chips via the bus transmission device located within it. The internal interconnect bus of the chips is a parallel bus, such as AXI, AHB, or APB.

[0050] Please see Figure 6 As shown, the main transmission device may include: a main communication module; a first bus slave interface connected between one or more functional modules of the first chip and the main communication module; a second bus master interface connected between the slave transmission device and the main communication module; a last-in-first-out (LIFO) storage module connected between the main communication module and the first bus slave interface, configured for read operations to be performed by functional modules via the first bus slave interface; the main communication module is used to receive read operation instructions sent by functional modules via the first bus slave interface, the read operation instructions being used to read data from readable modules in the second chip; to encode the read operation instructions for transmission via the second bus master interface; to decode the data received via the second bus master interface, and to write the decoded data into the LIFO storage module.

[0051] Please see Figure 6 As shown, the transmission device may include: a slave communication module; a second bus slave interface connected between the second bus master interface and the slave communication module; a first bus master interface connected between the slave communication module and one or more readable modules of the second chip, used for reading operations on the readable modules; the slave communication module used for decoding the read operation command received via the second bus slave interface and sending the decoded read operation command to the first bus master interface for reading operations on the readable modules; and encoding the data sent via the first bus master interface for transmission via the second bus slave interface.

[0052] In some possible implementations, the functional module is used to obtain the amount of data already stored in the last-in-first-out (LIFO) storage module when sending a read operation command, determine the target data amount based on the stored data amount, and read data from the LIFO storage module when the stored data amount is detected to be the target data amount, thus obtaining the data corresponding to the read operation command. The functional module can also be used to determine that the second bus main interface is in an idle state before sending the read operation command. In a specific implementation, each read operation increases the amount of data already stored in the LIFO storage module by 1; that is, if the amount of data already stored before the read operation is N, then after one read operation, the amount of data already stored is N+1. If the functional module sends a read operation command when the amount of data already stored is N and detects that the amount of data already stored is N+2, it indicates that there are other read operation commands after sending this read operation command. As an example, the first process of the CPU sends a first read operation instruction when the amount of data stored in the last-in-first-out (LIFO) memory module is N. In response to the first read operation instruction, data read from the second chip is stored in the LIFO memory module, making the amount of stored data N+1. If an interrupt occurs before the first process reads data from the LIFO memory module, the second process sends a second read operation instruction. In response to the second read operation instruction, data read from the second chip is stored in the LIFO memory module, making the amount of stored data N+2. At this point, the first process detects that the amount of stored data is N+2, which is not its target storage amount (i.e., N+1), and does not read data from the LIFO memory module. The second process detects that the amount of stored data is N+2, which is its target storage amount (i.e., N+2), and reads data from the LIFO memory module, obtaining the data corresponding to the second read operation instruction (i.e., the N+2th data). After the second process reads the data, the amount of stored data in the LIFO memory module becomes N+1. The first process detects that the amount of stored data is N+1, which is its target storage quantity (i.e., N+1). It reads data from the last-in-first-out (LIFO) storage module to obtain the data corresponding to the first read operation instruction (i.e., the N+1th data). Based on this mechanism, when an interrupt occurs, the interrupted process can read its corresponding data first, and then the original process can read its corresponding data, avoiding mismatch between data and read operation instructions due to interruption.

[0053] In some possible implementations, the main communication module is further configured to receive write operation instructions sent by the functional module via the first bus slave interface, encode the write operation instructions for transmission via the second bus interface, and the write operation instructions are used to write data to the writable module in the second chip; the slave communication module is further configured to decode the write operation instructions received via the second bus slave interface and send the decoded write operation instructions to the first bus main interface to perform a write operation on the writable module.

[0054] In some possible implementations, the main communication module specifically converts the address of the register to be operated into the register number to be operated; for read operation instructions, it encodes them into read operation frames, which include a frame length and the register number to be operated; for write operation instructions, it encodes them into write operation frames, which include a frame length, the register number to be operated, and the data to be written. The slave communication module is specifically used to convert the register number into the target register address when decoding read or write operation instructions; and to encode the read data into a return frame, which includes a frame length and the returned data. As an example, a read operation frame contains 2 bytes, where the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, and the second byte represents the low 8 bits of the register number to be operated on. A write operation frame contains at least 3 bytes, where the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, the second byte represents the low 8 bits of the register number to be operated on, and the remaining bytes represent the data to be written. A return frame contains at least 2 bytes, where the high 4 bits of the first byte represent the frame length, the low 4 bits are reserved, and the remaining bytes represent the returned data. For an example, please refer to [link to example]. Figure 4 The frame format used for data transmission is shown.

[0055] In one implementation, the main communication module may include: an encoding / decoding unit connected to the first bus slave interface; a first first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and the second bus master interface; and a second first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and the second bus master interface. The encoding / decoding unit includes: an encoding unit for receiving read operation instructions, encoding the read operation instructions, and writing the encoded read operation instructions into the second first-in-first-out unit for transmission via the second bus master interface; and a decoding unit for reading data from the first first-in-first-out storage unit, decoding the read data, and writing the decoded data into a last-in-first-out (LIFO) storage module. In some possible implementations, the main communication module may further include: a configuration register connected between the first bus slave interface and the second bus master interface, and between the first bus slave interface and the encoding / decoding unit, configured for the functional module to configure transmission parameters via the first bus slave interface, such as the transmission rate of the second bus master interface and the authorization judgment of the encoding / decoding unit for the first interface slave bus.

[0056] In one implementation, the communication module may include: an encoding / decoding unit connected to a first bus master interface; a first first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and a second bus slave interface; and a second first-in-first-out (FIFO) storage unit connected between the encoding / decoding unit and the second bus slave interface. The encoding / decoding unit includes: a decoding unit for reading read operation instructions from the first FIFO storage unit, decoding the read operation instructions, and sending the decoded read operation instructions to the first bus master interface for execution; and an encoding unit for receiving data sent by the first bus master interface, encoding the received data, and writing the encoded data into the second FIFO storage unit for transmission by the second bus slave interface. In some possible implementations, the communication module may further include: a flow controller connected between the second bus slave interface and the encoding / decoding unit, configured to control the flow of the encoding / decoding unit.

[0057] Taking SPI as a serial bus as an example, when the CS of the SPI is low, transmission begins. The configuration register of the main communication module configures the SPI CLK rate and how long after CS is pulled low should communication transmission begin. The process controller of the slave communication module detects the falling edge of CS and prepares to receive data, and determines the read / write operation based on the frame information to execute the receive process.

[0058] Embodiments of this disclosure also provide a multi-chip system, including: a first chip, the first chip including one or more functional modules and the aforementioned main transmission device; and a second chip, the second chip including one or more readable modules and the aforementioned slave transmission device.

[0059] This disclosure provides a bus transmission method applied to a first chip. The first chip includes one or more functional modules and the aforementioned bus transmission device. In embodiments of this disclosure, the functional modules may include parallel processes, where one process can interrupt another. Figure 7 As shown, the bus transmission method includes the following steps.

[0060] In step S701, when the functional module sends a read operation command, it obtains the amount of data already stored in the last-in-first-out storage module and determines the target data amount based on the amount of data already stored.

[0061] As one implementation method, in Figure 2 In this system, functional modules send read operation commands via the first bus interface, and communication modules receive read operation commands from functional modules (e.g., CPU, GPU, NPU, etc.) via the first bus interface. These read operation commands are used to read data from readable modules (e.g., memory units, IP cores, etc.) in the second chip. The communication module encodes the read operation commands for transmission via the second bus interface. Data received from the second chip via the second bus interface is decoded, and the decoded data is written to the Last-In-First-Out (LIFO) memory module. The LIFO memory module is configured for read operations by functional modules (e.g., CPU, GPU, NPU, etc.) of the first chip via the first bus interface.

[0062] As one implementation method, in Figure 6 In this process, the functional module sends read operation commands through the first bus slave interface, and the main communication module receives the read operation commands sent by the functional module through the first bus slave interface. These read operation commands are used to read data from the readable module in the second chip. The main communication module encodes the read operation commands for transmission through the second bus master interface. The slave communication module decodes the read operation commands received through the second bus slave interface and sends the decoded read operation commands to the first bus master interface to perform a read operation on the readable module; it also encodes the data transmitted through the first bus master interface for transmission through the second bus slave interface. The main communication module decodes the data received through the second bus master interface and writes the decoded data into the last-in-first-out (LIFO) memory module.

[0063] In step S702, when the functional module detects that the amount of stored data is the target amount of data, it reads data from the last-in-first-out storage module to obtain the data corresponding to the read operation instruction.

[0064] In some possible implementations, the communication module is also used to receive write operation instructions sent by functional modules (such as CPU, GPU, NPU, etc.) via a first bus interface, encode the write operation instructions for transmission via a second bus interface, and write data to a writable module (such as a memory unit, IP core, etc. in the second chip).

[0065] In the specific implementation, each read operation increases the amount of data stored in the Last-In-First-Out (LIFO) memory module by 1. That is, if the amount of data stored before the read operation is N, then after the read operation, the amount of data stored is N+1. If the functional module sends a read operation instruction when the amount of data stored is N, and detects that the amount of data stored is N+2, it indicates that there are other read operation instructions after sending this read operation instruction. As an example, the first process of the CPU sends a first read operation instruction when the amount of data stored in the LIFO memory module is N. In response to the first read operation instruction, the data read from the second chip is stored in the LIFO memory module, making the amount of data stored N+1. If an interrupt occurs before the first process reads data from the LIFO memory module, the second process sends a second read operation instruction. In response to the second read operation instruction, the data read from the second chip is stored in the LIFO memory module, making the amount of data stored N+2. At this time, the first process detects that the amount of data stored is N+2, which is not its target storage amount (i.e., N+1), and does not read data from the LIFO memory module. The second process detects that the amount of stored data is N+2, which is its target storage quantity (i.e., N+2). It reads data from the last-in-first-out (LIFO) storage module to obtain the data corresponding to the second read operation instruction (i.e., the N+2th data). After the second process reads the data, the amount of stored data in the LIFO storage module becomes N+1. The first process detects that the amount of stored data is N+1, which is its target storage quantity (i.e., N+1). It reads data from the LIFO storage module to obtain the data corresponding to the first read operation instruction (i.e., the N+1th data). Based on this mechanism, when an interrupt occurs, the interrupted process can read its corresponding data first, and then the original process can read its corresponding data, avoiding mismatch between data and read operation instructions due to interruption. In addition, the functional module is also used to determine that the second bus interface is in an idle state (also known as a non-communication state) before sending the read operation instruction.

[0066] The embodiments disclosed herein use a last-in-first-out (LIFO) memory module to handle interrupts, which can ensure that each process can retrieve the data it needs, and an n-level stack can ensure that n-level interrupt nesting will not cause problems.

[0067] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to preferred embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A bus transmission device applied to a first chip, the first chip comprising one or more functional modules, characterized in that, The bus transmission device includes: Communication module; The first bus interface is connected between the functional module and the communication module; The second bus interface is connected between the second chip and the communication module; The last-in-first-out (LIFO) storage module is connected between the communication module and the first bus interface and is configured to be read by the functional module via the first bus interface. The communication module is configured to receive a read operation instruction sent by the functional module via the first bus interface, the read operation instruction being used to read data from the readable module in the second chip; encode the read operation instruction for transmission via the second bus interface; decode the data sent by the second chip via the second bus interface; and write the decoded data into the last-in-first-out storage module. The functional module is configured to, when sending a read operation command, obtain the amount of data already stored in the last-in-first-out (LIFO) storage module, determine the target data amount based on the amount of data already stored, and when the amount of data already stored is detected to be the target data amount, read data from the LIFO storage module to obtain data corresponding to the read operation command.

2. The bus transmission device as described in claim 1, characterized in that, The functional module is also used to determine that the second bus interface is in an idle state before sending a read operation command.

3. The bus transmission device as described in claim 1, characterized in that, The communication module is specifically used for: Convert the address of the register to be operated on to the register number to be operated on; For read operation instructions, they are encoded into read operation frames, which include the frame length and the register number to be operated on; For write operation instructions, they are encoded into write operation frames, which include frame length, register number to be operated, and data to be written.

4. The bus transmission device as described in claim 3, characterized in that, The read operation frame contains 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated, and the second byte represents the low 8 bits of the register number to be operated. The write operation frame contains at least 3 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated on, the second byte represents the low 8 bits of the register number to be operated on, and the remaining bytes represent the data to be written.

5. The bus transmission device as described in claim 1, characterized in that, The communication module is further configured to receive a write operation instruction sent by the functional module via the first bus interface, encode the write operation instruction for transmission via the second bus interface, and the write operation instruction is used to write data to the writable module in the second chip.

6. The bus transmission device as described in claim 1, characterized in that, The communication module includes: The encoding / decoding unit is connected to the first bus interface; The first first-in-first-out storage unit is connected between the encoding / decoding unit and the second bus interface; The second first-in-first-out storage unit is connected between the encoding / decoding unit and the second bus interface; The encoding / decoding unit includes: An encoding unit is used to receive the read operation instruction, encode the read operation instruction, and write the encoded read operation instruction into the second first-in-first-out storage unit for transmission via the second bus interface. The decoding unit is used to read the data from the first first-in-first-out storage unit, decode the read data, and write the decoded data into the last-in-first-out storage module.

7. The bus transmission device as described in claim 6, characterized in that, The communication module further includes: A configuration register, connected between the first bus interface and the second bus interface, and between the first bus interface and the encoding / decoding unit, is configured to transmit parameter configurations via the first bus interface by the functional module.

8. The bus transmission device as described in claim 1, characterized in that, The first bus interface is a first bus slave interface, and the first bus slave interface is connected to the first bus master interface of the functional module; The second bus interface is the second bus master interface, and the second bus master interface is connected to the second bus slave interface of the second chip; The first bus interface is a parallel bus interface, and the second bus interface is a serial bus interface.

9. A bus transmission system, characterized in that, include: The main transmission device is located in the first chip; From the transmission device, it is set in the second chip; The main transmission device includes: Main communication module; The first bus slave interface is connected between one or more functional modules of the first chip and the main communication module; The second bus main interface is connected between the slave transmission device and the main communication module; The last-in-first-out (LIFO) storage module is connected between the main communication module and the first bus slave interface and is configured to be read by the functional module through the first bus slave interface. The main communication module is used to receive read operation instructions sent by the functional module via the first bus slave interface. The read operation instructions are used to read data from the readable module in the second chip. The main communication module is used to encode the read operation instructions and send them via the second bus main interface. The main communication module is used to decode the data received via the second bus main interface and write the decoded data into the last-in-first-out storage module. The transmission device includes: From the communication module; The second bus slave interface is connected between the second bus master interface and the slave communication module; The first bus main interface is connected between the slave communication module and one or more readable modules of the second chip, and is used to perform read operations on the readable modules; The communication module is used to decode the read operation command received via the second bus slave interface, and send the decoded read operation command to the first bus master interface to perform a read operation on the readable module; and to encode the data sent via the first bus master interface for transmission via the second bus slave interface. The functional module is configured to, when sending a read operation command, obtain the amount of data already stored in the last-in-first-out (LIFO) storage module, determine the target data amount based on the amount of data already stored, and when the amount of data already stored is detected to be the target data amount, read data from the LIFO storage module to obtain data corresponding to the read operation command.

10. The bus transmission system as described in claim 9, characterized in that, The functional module is also used to determine that the second bus master interface is in an idle state before sending a read operation command.

11. The bus transmission system as described in claim 9, characterized in that, The main communication module is also used to receive write operation instructions sent by the functional module via the first bus slave interface, encode the write operation instructions for transmission via the second bus main interface, and the write operation instructions are used to write data to the writable module in the second chip. The communication module is further configured to decode the write operation instruction received via the second bus slave interface, and send the decoded write operation instruction to the first bus master interface to perform a write operation on the writable module.

12. The bus transmission system as described in claim 9, characterized in that, The main communication module is specifically used to convert the address of the register to be operated into the number of the register to be operated; for read operation instructions, it is encoded into a read operation frame, which includes the frame length and the number of the register to be operated; for write operation instructions, it is encoded into a write operation frame, which includes the frame length, the number of the register to be operated, and the data to be written. The communication module is specifically used to convert the register number into the target register address when decoding read or write operation instructions; and to encode the read data into a return frame, which includes the frame length and the returned data.

13. The bus transmission system as described in claim 12, characterized in that, The read operation frame contains 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated, and the second byte represents the low 8 bits of the register number to be operated. The write operation frame contains at least 3 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits represent the high 4 bits of the register number to be operated, the second byte represents the low 8 bits of the register number to be operated, and the remaining bytes represent the data to be written. The returned frame contains at least 2 bytes, wherein the high 4 bits of the first byte represent the frame length, the low 4 bits are reserved fields, and the remaining bytes represent the returned data.

14. A multi-chip system, characterized in that, include: The first chip includes: one or more functional modules, and the main transmission device of the bus transmission system as described in any one of claims 9 to 13; The second chip includes: one or more readable modules, and a slave transmission device of the bus transmission system as described in any one of claims 9 to 13.

15. A bus transmission method applied to a first chip, characterized in that, The first chip includes one or more functional modules and a bus transmission device as described in any one of claims 1 to 8, wherein the bus transmission method includes: When sending a read operation command, the functional module obtains the amount of data already stored in the last-in-first-out (LIFO) storage module, determines the target data amount based on the amount of data already stored, and reads data from the LIFO storage module when the amount of data already stored is the target data amount, thereby obtaining the data corresponding to the read operation command.

16. The bus transmission method as described in claim 15, characterized in that, The amount of stored data is N, and the target amount of data is N+1.

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