Directional selective spiking integrated chip based on heterogeneous integration and preparation method

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a direction-selective sensing and computing integrated chip based on heterogeneous integration and a preparation method, which comprises a feature extraction Chiplet and a computing Chiplet; the computing Chiplet adopts a high-performance silicon-based CMOS chip, internally integrates a large-scale convolution pulse neural network processing core, and is used for executing high-level object recognition and classification tasks; wherein the feature extraction Chiplet is mainly composed of a plurality of mutually parallel visual arrays, a single visual array is composed of a bidirectional response synapse phototransistor, a memristor and a substrate, and the bidirectional response synapse phototransistor and the memristor are located on the left and right sides above the substrate. In the application, preprocessed pulse data is directly transmitted through high-density parallel interconnection, the bottleneck of data bandwidth and transmission delay is fundamentally broken, system power consumption and communication load are greatly reduced, and complex visual tasks can be processed in real time on resource-limited edge devices.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a direction-selective in-memory computing chip based on heterogeneous integration and its fabrication method. Background Technology

[0002] Existing machine vision systems suffer from a separation between color and spatial information processing. Traditional CMOS image sensors acquire color information through Bayer filters, and then a back-end processor executes complex algorithms (such as edge detection and color constancy) to extract features. This entire process is characterized by low energy efficiency and high latency. In recent years, although neuromorphic vision sensors have been proposed, most focus on pulse coding of grayscale information or simple color detection, lacking the ability to perform collaborative and biomimetic preprocessing of color and spatial relationships. For example, the dual-handed neuron array proposed in the aforementioned paper achieves the function of retina-to-primary visual cortex (V1), but how to integrate this array as a standalone device with a powerful back-end computing system (such as a massively multi-spiking neural network, SNN) with high bandwidth and low latency to cope with complex real-time vision tasks remains an unsolved challenge.

[0003] Traditional two-dimensional integration methods cannot meet the requirements for high-speed, parallel transmission of massive pulse data between the sensor array and the computing core. Specifically: 1. High load due to post-feature extraction: The original color data is huge, and the transmission to the back-end processor for feature extraction results in extremely high data bandwidth requirements and power consumption.

[0004] 2. Lack of biomimetic intelligent preprocessing: Existing hardware lacks the ability to extract primary visual features such as orientation and color resistance in parallel, and cannot achieve efficient data compression and redundancy removal at the information source like biological vision.

[0005] 3. System integration and bandwidth bottleneck: Even with high-performance bionic sensor arrays, the interconnection bandwidth and latency between them and computing units in a 2D architecture severely restrict the overall performance of the system, forming a "preprocessing wall".

[0006] 4. Challenges in integrating heterogeneous materials and processes: High-performance biomimetic devices (such as those based on oxide semiconductors, organic heterojunctions, and Mott memristors) are incompatible with mainstream silicon-based CMOS computing processes in terms of materials and thermal budget, making them difficult to implement on a single chip. Summary of the Invention

[0007] This invention provides a direction-selective in-memory computing chip based on heterogeneous integration and its fabrication method to solve existing technical problems, thereby addressing the bottlenecks of data bandwidth and transmission delay.

[0008] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a heterogeneous integrated direction-selective in-memory computing chip includes a feature extraction chiplet and a computation chiplet; the computation chiplet uses a high-performance silicon-based CMOS chip, which integrates a large-scale convolutional spiking neural network (CSNN) processing core for performing high-level object recognition and classification tasks. The feature extraction chiplet is mainly composed of several parallel visual arrays. Each visual array is composed of a bidirectional synaptic phototransistor, a memristor, and a substrate, wherein the bidirectional synaptic phototransistor and the memristor are located on the left and right sides above the substrate, respectively. The bidirectional responsive synaptic phototransistor comprises, from bottom to top, a control gate, a dielectric layer, a semiconductor layer, and a photosensitive layer; the memristor comprises, from bottom to top, an output metal layer and a memory resistor layer. A drain metal layer is deposited above the semiconductor layer and to the left of the photosensitive layer, and a source metal layer is deposited above the semiconductor layer and to the right of the photosensitive layer. The right end of the source metal layer covers the memory resistor layer and is in ohmic contact with it.

[0009] Furthermore, the heterogeneous integration-based direction-selective in-memory computing chip also includes a silicon interposer, which is a silicon-based interconnect platform with a high-density redistribution layer (RDL) and through-silicon vias (TSVs). The feature extraction chipplet and the computation chipplet are mounted side-by-side on the silicon interposer via microbumps.

[0010] Furthermore, the feature chiplet outputs a preprocessed directional color boundary pulse map, which is transmitted in parallel to the computation chiplet via high-density redistribution layers (RDLs) and through-silicon vias (TSVs) within the output metal layer and silicon interposer. This significantly reduces communication latency and enables a direct "feature stream" connection between sensing and computation.

[0011] Furthermore, the feature extraction chipplet is directly stacked on the computing chipplet using chip-wafer bonding technology.

[0012] Furthermore, the feature extraction Chiplet and the computation Chiplet are interconnected in three dimensions with the TSV via hybrid bonding or microbumps.

[0013] Furthermore, the pulse signals generated by each pixel or processing unit (such as a dual-handed receptive field) on the feature chip can be directly, one-to-one or one-to-many, transmitted to the corresponding SNN neuron layer in the computation chip via the output metal layer and the TSV directly below. This "perforated" connection achieves the shortest physical path and the highest interconnect density. This 3D vertical integration method physically simulates the layered, parallel processing pathway of the retina-lateral geniculate body-primary visual cortex in the biological visual system, achieving extreme energy efficiency and speed.

[0014] Furthermore, an oxide layer (10) is filled between the bidirectional responsive synaptic phototransistor and the memristor.

[0015] Furthermore, the dielectric layer is made of... , , Any one of the following; the semiconductor layer is made of IGZO; the photosensitive layer is made of P3HT:PCBM.

[0016] Methods for fabricating direction-selective in-memory computing chips based on heterogeneous integration include: S1. Based on standard silicon-based CMOS technology, fabricate a computational chiplet integrating a convolutional spiking neural network processing core; S2. Feature extraction chiplets are fabricated on independent substrates using a heterogeneous integration process; S3. The feature extraction chiplet and the computation chiplet are heterogeneously integrated to form an integrated sensing, storage, and computing chip.

[0017] The directional selective in-memory computing chip and its fabrication method based on heterogeneous integration provided by this invention have the following advantages compared to existing technologies: 1. This invention utilizes 2.5D / 3D heterogeneous integration technology to efficiently combine biomimetic visual feature extraction with back-end computing units, achieving a significant improvement in system performance. This chip moves the color and spatial feature extraction tasks from the traditional back-end processor to the sensing end, directly transmitting preprocessed pulse data through high-density parallel interconnects. This fundamentally breaks through the bottlenecks of data bandwidth and transmission latency, significantly reducing system power consumption and communication load, enabling complex visual tasks to be processed in real time on resource-constrained edge devices.

[0018] 2. This invention implements the direction selectivity and dual-hand color processing functions in the biological vision system through hardware, and solidifies the biomimetic preprocessing capability in the feature extraction chiplet, avoiding redundant calculations in software algorithms. As a result, it can maintain high recognition accuracy even in extremely low light and high noise environments, and improve the robustness and adaptability of the system in changing scenarios.

[0019] 3. This invention utilizes advanced packaging technology to solve the integration problem of heterogeneous materials and silicon-based CMOS processes, enabling biomimetic sensor arrays based on oxide semiconductors, organic materials and memristors to work in tandem with high-performance computing units, giving full play to the advantages of different processes, and achieving high energy efficiency and miniaturization at the system level.

[0020] 4. This invention supports dynamic voltage configuration and reconfigurable sensing capabilities, allowing the direction preference and color processing mode of the receptive field to be adjusted in real time through electrical signals, enabling it to flexibly adapt to different visual task requirements, such as lane detection in autonomous driving or obstacle recognition in drone navigation, further enhancing the practicality and application scope of the system. Attached Figure Description

[0021] Figure 1 This is a 2.5D integration schematic diagram of the present invention; Figure 2 This is a 3D integration diagram of the present invention; Figure 3 This is a schematic diagram of the array in this invention; Figure 4 This is a circuit diagram of the array in this invention.

[0022] In the diagram: 1. Substrate; 2. Control gate; 3. Dielectric layer; 4. Semiconductor layer; 5. Drain metal layer; 6. Photosensitive layer; 7. Source metal layer; 8. Memory resistor layer; 9. Output metal layer; 10. Oxide layer. Detailed Implementation

[0023] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example

[0024] 2.5D Intermediate Layer Integration Solution like Figure 1 , 3 As shown in Figure 4, the direction-selective in-memory computing chip based on heterogeneous integration is characterized by including a feature extraction chiplet and a computation chiplet; the computation chiplet uses a high-performance silicon-based CMOS chip, which integrates a large-scale convolutional spiking neural network (CSNN) processing core to perform high-level object recognition and classification tasks. The feature extraction chiplet mainly consists of several parallel visual arrays. Each visual array consists of a bidirectional synaptic phototransistor, a memristor, and a substrate 1. The bidirectional synaptic phototransistor and the memristor are located on the left and right sides above the substrate 1, respectively. like Figure 3 , 4As shown, the bidirectional synaptic phototransistor includes, from bottom to top, a control gate 2, a dielectric layer 3, a semiconductor layer 4, and a photosensitive layer 6; the memristor includes, from bottom to top, an output metal layer 9 and a memory resistor layer 8. A drain metal layer 5 is deposited above the semiconductor layer 4 and to the left of the photosensitive layer 6, and a source metal layer 7 is deposited above the semiconductor layer 4 and to the right of the photosensitive layer 6. The right end of the source metal layer 7 covers the memory resistor layer 8 and is in ohmic contact with it.

[0025] After the drain metal layer 5 is connected to the VDD voltage, when the photosensitive layer 6 receives light stimulation, a circuit is formed between the drain metal layer 5 and the source metal layer 7. The charge in the source metal layer 7 can be output through the memory resistor layer 8 and then through the output metal layer 9.

[0026] The heterogeneous integration-based directional selective in-memory computing chip also includes a silicon interposer, which is a silicon-based interconnect platform with a high-density redistribution layer (RDL) and through-silicon vias (TSVs). Feature extraction chiplets and computation chiplets are mounted side-by-side on the silicon interposer via microbumps. The feature chiplets output a pre-processed directional color boundary pulse map, which is transmitted in parallel to the computation chiplets through the output metal layer 9 and the high-density redistribution layer (RDL) and through-silicon vias (TSVs) within the silicon interposer. This significantly reduces communication latency and enables a direct "feature stream" connection between sensing and computation.

[0027] The specific steps and principles of this embodiment are as follows: 1) Silicon Interposer: Provides a silicon-based interconnect platform with a high-density redistribution layer (RDL) and through-silicon vias (TSVs).

[0028] 2) Feature Extraction Chiplet: The dual-arm neuron array is fabricated as an independent chiplet. This chiplet integrates a bidirectional responsive synaptic phototransistor (BPRPT, based on an In2O3 / PTB7-Th:Y6 heterojunction) and NbO. x Mott memristors (1PT1TS structure) can generate configurable excitation / inhibition impulse responses to ultraviolet (UV) and near-infrared (NIR) light inputs and achieve direction-selective spatial-color dual-hand processing.

[0029] 3) Computation Chiplet: It uses a high-performance silicon-based CMOS chip with a large-scale convolutional spiking neural network (CSNN) processing core to perform high-level object recognition and classification tasks.

[0030] 4) High-density parallel interconnect: The feature extraction chipplet and the computation chipplet are mounted side by side on the silicon interposer via microbumps. The pre-processed directional color boundary pulse map output by the feature chipplet is transmitted to the computation chipplet in parallel and at high speed through high-density interconnects in the interposer, which greatly reduces communication latency and realizes a direct "feature stream" connection between sensing and computation.

[0031] This embodiment utilizes a high-density redistribution layer in the silicon interposer and through-silicon vias to interconnect the feature extraction chipplet and the computation chipplet side-by-side, enabling high-speed parallel transmission of directional color boundary pulse maps. The feature extraction chipplet employs bidirectional synaptic phototransistors and memristor arrays to directly perform biomimetic visual feature extraction and pulse coding at the sensing end, significantly compressing the data volume. Its advantages lie in breaking through the "preprocessing wall" of traditional two-dimensional integration, significantly reducing communication latency and power consumption through high-density interconnection, and simultaneously improving the system's robustness and real-time processing capabilities in low-light and noisy environments through hardware-based biomimetic preprocessing, perfectly meeting the high energy efficiency requirements of edge intelligent devices. Example

[0032] 3D stacking integration solution like Figure 2 , 3 4. The feature extraction chipplet is directly stacked on top of the computation chipplet using chip-to-wafer bonding technology. The feature extraction chipplet and the computation chipplet are interconnected in three dimensions with the TSV via hybrid bonding or microbumps.

[0033] The pulse signals generated by each pixel or processing unit (such as a pair of hand receptive fields) on the feature chip can be directly, one-to-one or one-to-many, transmitted to the corresponding SNN neuron layer in the computation chip via the output metal layer 9 and the TSV directly below it. This "perforated" connection achieves the shortest physical path and the highest interconnect density. This 3D vertical integration method physically simulates the hierarchical, parallel processing pathway of the retina-lateral geniculate body-primary visual cortex in the biological visual system, achieving extreme energy efficiency and speed.

[0034] An oxide layer (10) is filled between the bidirectional synaptic phototransistor and the memristor. The dielectric layer 3 is made of [material name missing]. , , Any one of the following; the semiconductor layer 4 is made of IGZO; the photosensitive layer 6 is made of P3HT:PCBM.

[0035] The specific steps and principles of this embodiment are as follows: 1) Vertical stacking: Feature extraction chiplets are directly stacked on top of computing chiplets using chip-wafer bonding technology.

[0036] 2) Direct Vertical Interconnection: Two chipplets are interconnected in three dimensions with a TSV via hybrid bonding or microbumps. The pulse signals generated by each pixel or processing unit (such as a pair of hand receptive fields) on a feature chipplet can be directly, one-to-one or one-to-many transmitted to the corresponding SNN neuron layer in the computation chipplet via the TSV directly below it. This "perforated" connection achieves the shortest physical path and the highest interconnection density.

[0037] 3) Biomimetic pathway simulation: This 3D vertical integration method simulates the layered and parallel processing pathway of the retina-lateral geniculate body-primary visual cortex in the biological visual system in terms of physical structure, achieving extreme energy efficiency and speed.

[0038] This embodiment, through the aforementioned integration, enables the direct extraction and pulse coding of key visual features such as color boundaries and orientation at the sensing end, reducing the data volume by 1-2 orders of magnitude. Even in low-light (20% of standard brightness) and high-noise environments, through biomimetic preprocessing, the system's classification accuracy can be improved from nearly 0% and stabilized at over 90%. Through electrical configuration (VGS), the orientation preference and color adversarial mode of the receptive field in the feature extraction chipplet can be dynamically changed to adapt it to different visual tasks and environments.

[0039] This embodiment employs chip-wafer bonding technology to vertically stack feature extraction chipplets on top of computing chipplets, and uses TSV (Through-Vacuum Transistor) to achieve three-dimensional through-hole interconnection, allowing pulse signals from each receptive field to be transmitted directly to the computing unit via the shortest path. Combined with a voltage control strategy, the orientation and color preference of the receptive fields are dynamically configured, simulating the hierarchical processing pathway of biological vision. Its advantages include achieving extreme interconnect density and nanosecond-level transmission latency, significantly improving system energy efficiency and processing speed; dynamic reconfiguration capabilities enable the chip to adapt to various visual tasks, maintaining high recognition accuracy even in extreme environments, and fully leveraging the synergistic advantages of heterogeneous integrated materials and processes. Example

[0040] like Figure 1-4 As shown, the fabrication method of a direction-selective in-memory computing chip based on heterogeneous integration includes: Based on standard silicon-based CMOS technology, a computing chiplet integrating a convolutional spiking neural network processing core is fabricated; on a separate substrate, a feature extraction chiplet is fabricated through heterogeneous integration; the feature extraction chiplet and the computing chiplet are heterogeneously integrated to form an integrated sensing, storage, and computing chip.

[0041] Among them, the pulse signal mapping and timing synchronization mechanism between the sensing and computing units 1) Pulse signal mapping mechanism a. Spatial mapping: In 2.5D ensemble, each pair of receptive fields in the feature extraction chipplet forms a parallel, one-to-one, or one-to-many mapping relationship with the SNN input layer neurons in the computation chipplet through a high-density redistribution layer on a silicon interposer. In 3D stacking, vertical perforated connections are achieved through TSVs, and the output of each pixel or receptive field is directly connected to the corresponding SNN neuron in the computation layer directly below, forming the shortest path pulse propagation pathway.

[0042] b. Pulse code mapping: The Chiplet output is a preprocessed sequence of pulses, the frequency of which encodes the color boundary intensity and direction information. The SNN used to compute the Chiplet employs LeakyIntegrate-and-Fire neurons, which receive these pulses and perform spatiotemporal integration, as shown in the following formula: ; Where, Xi(t) The pulse input for the i-th receptive field at time t; R represents the weights of the corresponding connections (which can be trained or fixed); R is the reset mechanism, which generates a pulse and resets the membrane when the membrane potential exceeds the threshold.

[0043] 2) Timing synchronization mechanism a. Event-driven synchronization: The entire system employs an asynchronous event-driven approach, only issuing pulses when the receptive field detects valid features (such as color boundaries), thus reducing invalid data transmission. The computational unit performs time-encoding based on the pulse arrival time, consistent with the biological rationale of SNNs.

[0044] b. Global-local clock coordination: The computational chipplet can use a global clock for the simulation time stepping of the SNN; the sensing chipplet is a clockless pulse event output, and the pulse queue is synchronized at the intermediate layer or TSV interface through asynchronous FIFO or pulse buffer to ensure that the pulse is processed by the SNN within the correct time window.

[0045] c. Delay control: In 3D integration, due to the extremely short physical path (micrometer level), the pulse transmission delay can be controlled at the nanosecond level, which is much lower than that of traditional board-level interconnection, ensuring system-level timing consistency.

[0046] The voltage control strategy and hardware implementation for dynamically configured direction / color preferences are as follows: 1) Voltage control strategy (based on VGS modulation) a. Basic principles: Each BPRPT's gate voltage VGS controls its load line and NbO. x The location of the junction point of the TS device determines its excitation / inhibition response mode to UV / NIR. Four basic modes can be achieved by adjusting VGS: Low VGS: UV-ON, NIR-OFF; High VGS: UV-OFF, NIR-ON; VGS (Partial Response) is used for multi-band coding. Negative VGS: Turns off neurons to construct the inhibitory region of direction-selective radiofrequency.

[0047] b. Direction-selective construction: Artificial receptive fields with orientation preferences are constructed by using different spatially distributed VGS configurations. For example, an elliptical receptive field with a 0° orientation is constructed: The left half of the zone is set to VGS=2V (UV-ON); The right half of the circuit is set to VGS=10V (NIR-ON). The center line is set to VGS = −5V (off).

[0048] Only when the direction of light stimulation matches the direction of the receptive field can the maximum number of neurons be activated, producing the strongest impulse output.

[0049] 2) Hardware implementation details a. Voltage configuration network: A programmable voltage drive circuit is integrated into the feature extraction chiplet to provide an independent VGS control signal for each pixel or group of pixels. A row-column addressing + DAC structure can be used to achieve fast, parallel voltage configuration for large-scale arrays.

[0050] b. Dynamic reconfiguration capability: The VGS configuration can be switched in real time according to the visual task requirements via an external controller or on-chip state machine, changing the receptive field orientation preference or color adversarial mode. For example: In autonomous driving, the system switches to a horizontal orientation preference to detect lane lines. Switch to multi-directional scanning in the drone's navigation to detect obstacles.

[0051] c. Co-configuration with SNN: Calculating the Chiplet can provide feedback on task results (such as classification confidence), triggering the VGSVGS reconfiguration of the feature Chiplet, and realizing closed-loop optimization of perception-decision.

[0052] This embodiment fabricates computational chiplets using standard CMOS technology and heterogeneously integrates feature extraction chiplets on independent substrates. By combining spatial mapping, encoding mapping, and event-driven timing synchronization mechanisms for pulse signals, it ensures efficient integration of feature pulses into the SNN. An integrated voltage configuration network supports real-time electrical reconfiguration of the receptive field, achieving closed-loop optimization of the perception-decision process. Its advantages lie in solving the challenges of integrating heterogeneous materials, enabling efficient fabrication and operation of an integrated sensing-memory-computing system. The pulse processing mechanism ensures high data throughput and low latency processing, giving the chip real-time, robust visual understanding capabilities in resource-constrained edge scenarios.

[0053] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A direction-selective in-memory computing chip based on heterogeneous integration, characterized in that, It includes feature extraction chipplet and computation chipplet; the computation chipplet uses a high-performance silicon-based CMOS chip, which integrates a large-scale convolutional spiking neural network processing core to perform high-level object recognition and classification tasks. The feature extraction Chiplet comprises several parallel visual arrays, each of which consists of a bidirectional synaptic phototransistor, a memristor, and a substrate (1), wherein the bidirectional synaptic phototransistor and the memristor are located on the left and right sides above the substrate (1), respectively. The bidirectional responsive synaptic phototransistor comprises, from bottom to top, a control gate (2), a dielectric layer (3), a semiconductor layer (4), and a photosensitive layer (6); the memristor comprises, from bottom to top, an output metal layer (9) and a memory resistor layer (8). A drain metal layer (5) is deposited above the semiconductor layer (4) and to the left of the photosensitive layer (6), and a source metal layer (7) is deposited above the semiconductor layer (4) and to the right of the photosensitive layer (6). The right end of the source metal layer (7) covers the memory resistor layer (8) and is in ohmic contact with it. The pulse signal generated by each pixel or each processing unit on the feature extraction chip can be transmitted one-to-one or one-to-many to the corresponding SNN neuron layer in the computation chip through the output metal layer (9) and the TSV directly below it; The bidirectional synaptic phototransistor can generate configurable excitation or inhibition pulse responses to ultraviolet and near-infrared inputs, and achieve direction-selective spatial-color dual-hand processing. The heterogeneous integration-based direction-selective in-memory computing chip also includes a silicon interposer, which is a silicon-based interconnect platform with a high-density redistribution layer and through-silicon vias; the feature extraction chipplet and the computation chipplet are mounted side by side on the silicon interposer via microbumps. Alternatively, the direction-selective in-memory computing chip based on heterogeneous integration may also include a silicon interposer. The feature extraction chiplets and computing chiplets are stacked or mounted side-by-side on the silicon interposer through three-dimensional heterogeneous integration technology, and high-density parallel interconnection is achieved through silicon vias.

2. The heterogeneous integration-based direction-selective in-memory computing chip according to claim 1, characterized in that: When the heterogeneous integration-based directional selective in-memory computing chip also includes a silicon interposer, the silicon interposer is a silicon-based interconnect platform with a high-density redistribution layer and through-silicon vias (TSVs). When the feature extraction chipplet and the computation chipplet are mounted side by side on the silicon interposer through microbumps, the feature extraction chipplet outputs a preprocessed directional color boundary pulse map, which is transmitted to the computation chipplet in parallel through the output metal layer (9) and the high-density redistribution layer (RDL) and through-silicon vias (TSVs) in the silicon interposer.

3. The heterogeneous integration-based direction-selective in-memory computing chip according to claim 1, characterized in that: When the direction-selective in-memory computing chip based on heterogeneous integration also includes a silicon interposer, and the feature extraction chipplet and the computing chipplet are stacked or mounted side by side on the silicon interposer through three-dimensional heterogeneous integration technology and high-density parallel interconnection is achieved through silicon vias, the feature extraction chipplet is directly stacked on the computing chipplet through chip-wafer bonding technology.

4. The heterogeneous integration-based direction-selective in-memory computing chip according to claim 3, characterized in that: The feature extraction chipplet and the computation chipplet are interconnected in three dimensions with the TSV via hybrid bonding or microbumps.

5. The direction-selective in-memory computing chip based on heterogeneous integration according to claim 1, characterized in that: An oxide layer (10) is filled between the bidirectional responsive synaptic phototransistor and the memristor.

6. The direction-selective in-memory computing chip based on heterogeneous integration according to claim 1, characterized in that: The dielectric layer (3) is made of the following material: , , Any one of the following; the semiconductor layer (4) is made of IGZO; the photosensitive layer (6) is made of P3HT:PCBM.

7. A method for fabricating a direction-selective in-memory computing chip based on heterogeneous integration, characterized in that, The method for fabricating the heterogeneous integration-based orientation-selective in-memory computing chip according to any one of claims 1-6 includes: S1. Based on standard silicon-based CMOS technology, fabricate a computational chiplet integrating a convolutional spiking neural network processing core; S2. Feature extraction chiplets are fabricated on independent substrates using a heterogeneous integration process; S3. The feature extraction chiplet and the computation chiplet are heterogeneously integrated to form an integrated sensing, storage, and computing chip.

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