Image processing method and display device

Abstract

This application provides an image processing method and a display device. The image processing method includes: recognizing an image data to obtain a recognition result; adjusting the image data according to the recognition result to obtain a new image data; dividing the new image data into multiple bit planes; storing the multiple bit planes in multiple block buffers of at least one frame buffer, wherein each block buffer is used to store multiple rows of data in each bit plane; transferring the multiple rows of data from the multiple block buffers to multiple line buffers; loading the multiple rows of data from the line buffers into a display unit; adjusting the original dimming factor of the image data according to the recognition result to obtain a new dimming factor; and generating multiple parallel light emission control signals according to the new dimming factor to control the light emission time of multiple pixels of the display unit.

Description

Technical Field

[0001] The embodiments of this application relate to the field of display technology, and more specifically, to image processing methods and display devices. Background Technology

[0002] In recent years, to improve the display efficiency and stability of display panels in subfield driving mode, various image display methods based on parallel scanning algorithms have been proposed in existing technologies. These algorithms, through parallel control and timing optimization of multiple subfields, can effectively improve the latency and brightness unevenness problems of traditional sequential scanning modes, and achieve better display quality under normal brightness conditions.

[0003] However, parallel scanning technology still suffers from insufficient display quality in low grayscale or low brightness scenarios. Specifically, when the input image is a low grayscale image, the duty cycle of the illumination time in the subfield driver is too low, which can easily cause flickering that is perceptible to the naked eye. Especially at low frame rates (e.g., 30fps), if the image only activates low bits (bitX) within a single subfield (ts), the low grayscale images in the high grayscale subfields are all off, resulting in an extremely low on / off ratio during the display cycle and causing flickering.

[0004] Furthermore, under extremely low brightness conditions, the duration of the light emission control signal (em signal) is extremely short, sometimes even only one clock cycle. At this time, due to the delay effect of signal rise and fall, the inconsistencies between circuits and pixels are amplified, causing problems such as unstable brightness output and image quality degradation. Summary of the Invention

[0005] In view of this, the main objective of this application is to provide an image processing method and display device that obtains a new dimming factor for the image data by adjusting its original dimming factor based on the recognition result of the image data, thereby realizing an equivalent variable replacement mechanism and coordinating the adjustment of the pixel or brightness of the image data with the dimming factor, thereby achieving a more stable and flicker-free display effect.

[0006] To achieve the above objectives, one aspect of this application provides an image processing method, the image processing method comprising: To identify an image data and obtain a recognition result; The image data is adjusted based on the recognition result to obtain new image data; The new image data is divided into multiple bit planes; The multiple bit planes are respectively stored in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data of each bit plane; Transmit multiple rows of data from the multiple block caches to multiple row caches; Load the multiple rows of data from the row cache into the display unit; Adjust the original dimming factor of the image data according to the recognition result to obtain a new dimming factor; and Multiple parallel light emission control signals are generated based on the new dimming factor to control the light emission time of multiple pixels in the display unit.

[0007] Optionally, the process of recognizing the image data to obtain the recognition result includes: The recognition result identifies the image data as low grayscale and obtains the original pixels and original dimming factor of the image data.

[0008] Optionally, adjusting the image data based on the recognition result to obtain the new image data includes: The original pixels of the image data are multiplied by a preset factor to obtain the new image data with new pixels.

[0009] Optionally, adjusting the original dimming factor of the image data based on the recognition result to obtain the new dimming factor includes: The original dimming factor is divided by the preset multiple to obtain the new dimming factor.

[0010] Optionally, the image processing method is applied to a display device, the display device comprising a main control chip and the display unit, the main control chip comprising an image processing module, a memory module, a sequencing module and a scanning control module, wherein: The original pixels and original dimming factor of the image data are obtained by the image processing module, and the image processing module is configured to multiply the original pixels of the image data by the preset multiple and divide them into the multiple bit planes; The memory module is configured to store the multiple bit planes in multiple block caches of the frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module, and the sequencing module is configured to load the multiple rows of data from the row caches into the display unit; The scanning control module is configured to divide the original dimming factor by the preset multiple to obtain the new dimming factor, and generate multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

[0011] Optionally, the process of recognizing the image data to obtain the recognition result includes: The recognition result identifies the image data as low brightness and obtains the original dimming factor of the image data.

[0012] Optionally, adjusting the image data based on the recognition result to obtain the new image data includes: The image data is subjected to gamma correction to obtain the new image data.

[0013] Optionally, adjusting the original dimming factor of the image data based on the recognition result to obtain the new dimming factor includes: The original dimming factor is amplified to obtain the new dimming factor.

[0014] Optionally, the image processing method is applied to a display device, the display device comprising a main control chip and the display unit, the main control chip comprising an image processing module, a memory module, a sequencing module and a scanning control module, wherein: The original dimming factor of the image data is obtained by the image processing module, and the image processing module is configured to perform γ correction on the image data and divide it into the plurality of bit planes; The memory module is configured to store the multiple bit planes in multiple block caches of the frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module, and the sequencing module is configured to load the multiple rows of data from the row caches into the display unit; The scanning control module is configured to amplify the original dimming factor to obtain the new dimming factor, and generate multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

[0015] Another aspect of this application provides a display device, the display device comprising: The main control chip includes: An image processing module is configured to: recognize an image data to obtain a recognition result; adjust the image data according to the recognition result to obtain a new image data; and divide the new image data into multiple bit planes. A memory module, coupled to the image processing module, is configured to store multiple bit planes in multiple block caches of at least one frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A sequencing module, coupled to the memory module, wherein multiple rows of data in the plurality of block caches are configured to be transmitted to the row cache of the sequencing module; and A scanning control module, coupled to the sequencing module, is configured to: adjust the original dimming factor of the image data according to the recognition result to obtain a new dimming factor; and control the row selection line of the sequencing module to load multiple rows of data from the row cache into the display unit; and The display unit is coupled to the sequencing module, and the scanning control module generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

[0016] Optionally, the image processing module is configured as follows: The recognition result identifies the image data as low grayscale, and obtains the original pixels and original dimming factor of the image data; the original pixels of the image data are multiplied by a preset factor to obtain new image data with new pixels; and The scanning control module is configured to divide the original dimming factor by the preset multiple to obtain the new dimming factor.

[0017] Optionally, the memory module includes a time-slice sequence memory, which adjusts the bit plane corresponding to the read time-slice sequence based on the multiple relationship between the new pixel and the original pixel.

[0018] Optionally, the image processing module is configured as follows: The recognition result identifies the image data as low brightness, and the original dimming factor of the image data is obtained; Perform gamma correction on the image data to obtain the new image data; and The scanning control module is configured to amplify the original dimming factor to obtain the new dimming factor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein: Figure 1 A schematic diagram of a display device according to an embodiment of this application is shown.

[0020] Figure 2 This diagram illustrates a row buffer, row selection line, and display unit in a display device according to an embodiment of this application.

[0021] Figure 3 A flowchart illustrating an image processing method according to an embodiment of this application is shown.

[0022] Figure 4 A flowchart illustrating another embodiment of the image processing method of this application is shown. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Firstly, in this application, to achieve precise control of each pixel in the micro LED display device, subsequent embodiments will specifically employ digital quantities (i.e., binary data) as the control method. Specifically, by precisely controlling the illumination duration of each pixel, different grayscale levels are achieved for each pixel in the micro LED display device, thereby realizing a delicate image display effect. For example, the scanning frequency of the micro LED display device is 60Hz, meaning that one scanning cycle is completed every 16.6ms, and the grayscale value range of each pixel in the micro LED display device is... 255 corresponds to 8 bits in binary. Therefore, to precisely control the different grayscale levels of each pixel in a micro LED display, 8 bits are needed for individual control. More specifically, this is achieved by controlling the 8-bit binary number input to each pixel (i.e., ... This allows for fine-tuning of its grayscale levels.

[0027] It should be noted that a bit plane refers to the binary data used for each pixel, where each bit of binary data can be considered a bit plane. Referring to the previous example, It can be considered as the first bit plane. This can be considered a second bit plane, and so on. When the display device sequentially reads the data from each bit plane, it can generate the image of the current frame. Based on the foregoing, the control data of the micro-LED display device is divided into multiple bit plane data. In some embodiments, the micro-LED display device sequentially reads the data from each bit plane to complete image scanning. Specifically, it will... Divide into 255 equal parts and read... The scan can be completed by analyzing the data of each bit plane.

[0028] like Figure 1 The diagram shown is a schematic of a display device according to an embodiment of this application. The display device includes a main control chip 2 and a display unit 3. The main control chip 2 (such as an FPGA chip, including a CPU, GPU and MCU) includes an image processing module, a memory module, a sequencing module and a scanning control module.

[0029] The image processing module preprocesses and transforms the raw image data to meet the specific needs of the subsequent scanning control module and display unit. For example, it performs gamma correction, including compression and gamma functions, and adjusts the overall brightness of the image non-linearly before storing it in the frame buffer of the memory module to solve the problem of the excessively short luminous control signal (em signal) in extremely low brightness scenes. It also performs grayscale scaling, multiplies the pixel values ​​of the image, and implements the equivalent brightening operation required in the low grayscale anti-flicker scheme. As part of the pipeline, it connects the input data to the memory module, receives image data from the data channel, performs necessary processing (such as gamma correction), and then separates the processed data bit plane before sending it to the memory module for storage.

[0030] The memory module is coupled to the image processing module. The memory module is configured to store multiple bit planes into multiple block buffers within a frame buffer of the memory module, where each block buffer stores multiple rows of data from each bit plane. Specifically, in the microdisplay driving system, the memory module stores and manages the multi-stage processing flow of display data. The memory module stores the data after bit plane separation. During grayscale image input, bit plane separation processing is performed, where the original multi-bit wide grayscale data (8 bits) is separated into multiple parallel unit-width (1-bit) bit plane data. For example, after passing through the image signal processing unit, the multiple rows of data are divided into multiple bit planes and stored in eight block buffers 0-7 according to a preset block configuration, ultimately forming a complete frame buffer.

[0031] The sequencing module is coupled to the memory module, wherein multiple rows of data in the multiple block caches are configured to be transmitted to the first row cache and the second row cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the row selection line of the sequencing module to load multiple rows of data in the first row cache and the second row cache into the display unit 3.

[0032] Specifically, the sequencing module is the core of timing and data control for the entire driver architecture, and its overall operation is as follows: When the scanning control module starts the display operation, it initiates a request for bit plane data transmission, reads the separated bit plane data from the frame buffer according to block buffers 0-7, and transmits it to the first row buffer and the second row buffer. The first row buffer and the second row buffer are responsible for transmitting the received bit plane data to the display unit 3 according to a predetermined timing at a low clock frequency, in order to wait for the row selection signals of the first row selection line and the second row selection line to be triggered.

[0033] Cooperate Figure 2 The diagram shown is a schematic of a row buffer, row selection line, and display unit in a display device according to an embodiment of this application. The display unit 3 is coupled to the sequencing module. Multiple row selection signals generated by the sequencing module are transmitted to the display unit 3 through the first row selection line and the second row selection line. The scanning control module generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels in the display unit. The light emission control signals are generated using a subfield scanning method, where each subfield scans a different subfield. The light emission time length of each subfield is calculated by multiplying the dimming factor (dim_factor) of the entire frame, such as the light emission time ratio and the light emission time ratio of its subfields, the ratio stored in the time slice sequence memory (TSRAM), and the dimming factor of the entire frame.

[0034] In this embodiment, the scanning control module controls the first row selection line to activate the rows to be loaded from the first pixel array corresponding to the first row cache, and simultaneously controls the second row selection line to activate the rows to be loaded from the second pixel array corresponding to the second row cache. Furthermore, the first row cache and the second row cache each contain multiple sets of row caches, wherein the first sequence of the first row cache (top portion) corresponds to row caches A0-A3 (the first half of the row) and B0-B3 (the second half of the row), and the second sequence of the second row cache (bottom portion) corresponds to row caches A4-A7 (the first half of the row) and B4-B7 (the second half of the row). When loading the first row of the first pixel array (top part), line cache A0 loads the first half of the first row, and line cache B0 loads the second half of the first row, wherein the loading time interval between line cache A0 and line cache B0 is at least one clock cycle; simultaneously, when loading the first row of the second pixel array (bottom part), line cache A4 loads the first half of the first row, and line cache B4 loads the second half of the first row, wherein the loading time interval between line cache A4 and line cache B4 is at least one clock cycle, and the loading time interval between line cache B0 and line cache A4 is at least one clock cycle, and so on.

[0035] Based on the above design, in the implementation of identifying the image data as low grayscale, the image processing module identifies the image data to obtain a recognition result indicating that the image data is low grayscale, and obtains the original pixels and original dimming factor of the image data. Next, the image processing module multiplies the original pixels of the image data by a preset multiple to obtain new image data with new pixels, and divides the new image data into multiple bit planes for storage in multiple line buffers. Finally, the multiple lines of data in the line buffers are loaded into the display unit. The scanning control module divides the original dimming factor by the preset multiple to obtain the new dimming factor, and generates multiple parallel emission control signals based on the new dimming factor to control the emission time of multiple pixels in the display unit. Furthermore, the memory module also includes a time-slice sequence memory, which adjusts the bit plane corresponding to the read time-slice sequence based on the multiple relationship between the new pixels and the original pixels. In one example, if the pixel value is magnified by a factor of 2 (or a power of 2), then if the index of bit 0 is obtained, the microplane data of bit 1 is retrieved (if it is bit 9, then the blank data needs to be retrieved). Alternatively, the contents of the time-slice sequence memory (TSRAM) can be directly updated to match the corresponding multiplier relationship.

[0036] This application obtains a new dimming factor for image data by adjusting the original dimming factor based on the recognition result of the image data, thus achieving an equivalent variable replacement mechanism. The original pixel values ​​of the original image data are multiplied by a preset factor (e.g., K=4), and the bit plane corresponding to the subfield (ts) is changed. For example, if the overall image data requires x4, when selecting the corresponding subfield (ts) bit plane, if it is b8, then the actual bit plane b6 is used for scanning. For b1 and b0, the hidden bit planes need to be canceled for scanning, which is equivalent to dividing by 2^n. In this case, the minimum value of the dimming factor (dim_factor) needs to be constrained to prevent the length of the emission control signal from being 0. This application can double the effective refresh rate without increasing the actual frame rate, thereby suppressing low grayscale screen flicker and improving the stability of human visual perception.

[0037] Compared to existing technologies, current parallel scanning techniques based on subfield driving are prone to perceptible flickering at extremely low grayscale and low frame rates due to excessively short illumination times and low duty cycles. To address this issue, this application multiplies the original pixel value by a preset factor while simultaneously reducing the dimming factor proportionally to maintain overall brightness. Since the magnified pixel value triggers more bit planes to participate in illumination and is distributed across more dispersed time slots, the effective refresh rate can be increased (e.g., from 30 fps to 60 fps), effectively eliminating flickering in low grayscale scenes. In contrast, this application achieves a more stable and flicker-free display while maintaining extremely low brightness output, and this can be achieved by changing the bit planes without requiring actual computation of the original image data, thus balancing display quality and hardware implementation efficiency.

[0038] Based on the above design, in the implementation of identifying the image data as low brightness, the image processing module identifies the image data to obtain an identification result indicating that the image data is low brightness, and obtains the original dimming factor of the image data. Next, the image processing module performs gamma correction on the image data to obtain new image data, and divides the new image data into multiple bit planes for storage in multiple line buffers. Finally, the multiple lines of data in the line buffers are loaded into the display unit, the scan control module amplifies the original dimming factor to obtain the new dimming factor, and generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels in the display unit.

[0039] This application obtains a new dimming factor for image data by adjusting the original dimming factor based on the recognition results of the image data, thus achieving an equivalent variable replacement mechanism. This mechanism coordinates the adjustment of the image data's brightness and dimming factor, achieving the effect of extending the emission control signal while maintaining overall brightness. Specifically, in the image processing pipeline, gamma correction (such as a gamma curve) is first used to compress the overall brightness of the image data, reducing pixel size; simultaneously, the dimming factor is amplified to compensate for the brightness loss after compression. Through this synchronous operation, although the image pixel value decreases, the amplification of the dimming factor keeps the equivalent brightness extremely low, while the length of the emission control signal is significantly extended, thereby avoiding distortion and flickering caused by extremely short signals.

[0040] Compared to existing technologies, existing technologies, under extremely low brightness conditions, suffer from amplified effects during the ramp-up and ramp-down phases of the circuit due to the excessively short (even just one clock cycle) emission control signal of the emission control signal. This, in turn, leads to a decline in display quality due to component inconsistencies. This application addresses this by applying gamma curve compression to the overall brightness of the image data, reducing pixel size, and simultaneously amplifying the dimming factor to extend the duration of the emission control signal. This effectively avoids distortion caused by extremely short signals, resulting in a more stable waveform for the emission control signal and maintaining or improving display quality even at extremely low brightness. In contrast, this application achieves a more stable and flicker-free display while maintaining extremely low brightness output. Furthermore, it can be implemented using a bit-plane transformation method, eliminating the need for actual computation of the original image data, thus balancing display quality and hardware implementation efficiency.

[0041] like Figure 3 The diagram shown is a flowchart of an image processing method according to an embodiment of this application, applied to... Figures 1 to 2 The display device includes a main control chip 2 and a display unit 3, wherein the main control chip 2 includes an image processing module, a memory module, a sequencing module and a scanning control module.

[0042] The memory module is configured to store multiple bit planes into multiple block caches of a frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane. The sequencing module is coupled to the memory module, wherein the multiple rows of data in the multiple block caches are configured to be transmitted to the row cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit 3. The display method includes the following steps S101, S102, S103, S104, S105, S106 and S107: Step S101: The image processing module identifies the image data to obtain a recognition result that the image data is low grayscale, and obtains the original pixels and original dimming factor of the image data.

[0043] Step S102: The image processing module multiplies the original pixels of the image data by a preset multiple to obtain new image data with new pixels.

[0044] Step S103: Divide the new image data into multiple bit planes.

[0045] Step S104: Store the multiple bit planes in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data in each bit plane.

[0046] Step S105: The memory module transfers multiple rows of data from multiple block caches to multiple row caches.

[0047] Step S106: The sequencing module loads the multiple rows of data from the row cache into the display unit.

[0048] Step S107: The scanning control module divides the original dimming factor by the preset multiple to obtain the new dimming factor, and generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

[0049] Compared to existing technologies, current parallel scanning techniques based on subfield driving are prone to perceptible flickering at extremely low grayscale and low frame rates due to excessively short illumination times and low duty cycles. To address this issue, this application multiplies the original pixel value by a preset factor while simultaneously reducing the dimming factor proportionally to maintain overall brightness. Since the magnified pixel value triggers more bit planes to participate in illumination and is distributed across more dispersed time slots, the effective refresh rate can be increased (e.g., from 30 fps to 60 fps), effectively eliminating flickering in low grayscale scenes. In contrast, this application achieves a more stable and flicker-free display while maintaining extremely low brightness output, and this can be achieved by changing the bit planes without requiring actual computation of the original image data, thus balancing display quality and hardware implementation efficiency.

[0050] like Figure 4 The diagram shown is a flowchart of an image processing method according to another embodiment of this application, applied to... Figures 1 to 2 The display device includes a main control chip 2 and a display unit 3, wherein the main control chip 2 includes an image processing module, a memory module, a sequencing module and a scanning control module.

[0051] The memory module is configured to store multiple bit planes into multiple block caches of a frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane. The sequencing module is coupled to the memory module, wherein the multiple rows of data in the multiple block caches are configured to be transmitted to the row cache of the sequencing module. The scan control module is coupled to the sequencing module, and the scan control module is configured to control the row selection line of the sequencing module to load the multiple rows of data in the row cache into the display unit 3. The display method includes the following steps S201, S202, S203, S204, S205, S206 and S207: Step S201: The image processing module identifies the image data to obtain a recognition result that the image data is low brightness, and obtains the original dimming factor of the image data.

[0052] Step S202: The image processing module performs γ (gamma curve) correction on the image data to obtain the new image data.

[0053] Step S203: Divide the new image data into multiple bit planes.

[0054] Step S204: Store the multiple bit planes in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data in each bit plane.

[0055] Step S205: The memory module transfers multiple rows of data from multiple block caches to multiple row caches.

[0056] Step S206: The sequencing module loads the multiple rows of data from the row cache into the display unit.

[0057] Step S207: The scanning control module amplifies the original dimming factor to obtain the new dimming factor, and generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

[0058] Compared to existing technologies, existing technologies, under extremely low brightness conditions, suffer from amplified effects during the ramp-up and ramp-down phases of the circuit due to the excessively short (even just one clock cycle) emission control signal of the emission control signal. This, in turn, leads to a decline in display quality due to component inconsistencies. This application addresses this by applying gamma curve compression to the overall brightness of the image data, reducing pixel size, and simultaneously amplifying the dimming factor to extend the duration of the emission control signal. This effectively avoids distortion caused by extremely short signals, resulting in a more stable waveform for the emission control signal and maintaining or improving display quality even at extremely low brightness. In contrast, this application achieves a more stable and flicker-free display while maintaining extremely low brightness output. Furthermore, it can be implemented using a bit-plane transformation method, eliminating the need for actual computation of the original image data, thus balancing display quality and hardware implementation efficiency.

[0059] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0060] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An image processing method, characterized in that, The image processing method includes: To identify an image data to obtain an identification result, the identification result identifies the image data as low grayscale and obtains the original pixels and original dimming factor of the image data. Adjusting the image data based on the recognition result to obtain new image data includes: multiplying the original pixels of the image data by a preset multiple to obtain the new image data with new pixels; The new image data is divided into multiple bit planes; The multiple bit planes are respectively stored in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data of each bit plane; Transmit multiple rows of data from the multiple block caches to multiple row caches; Load the multiple rows of data from the row cache into the display unit; and The original dimming factor of the image data is adjusted according to the recognition result to obtain a new dimming factor, and multiple parallel light emission control signals are generated according to the new dimming factor to control the light emission time of multiple pixels of the display unit. The adjustment of the original dimming factor of the image data based on the recognition result to obtain the new dimming factor includes: dividing the original dimming factor by the preset multiple to obtain the new dimming factor.

2. The image processing method according to claim 1, characterized in that, The image processing method is applied to a display device, which includes a main control chip and the display unit. The main control chip includes an image processing module, a memory module, a sequencing module, and a scanning control module, wherein: The original pixels and the original dimming factor of the image data are obtained by the image processing module, and the image processing module is configured to multiply the original pixels of the image data by the preset multiple and divide them into the plurality of bit planes; The memory module is configured to store the multiple bit planes in multiple block caches of the frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module, and the sequencing module is configured to load the multiple rows of data from the row caches into the display unit; The scanning control module is configured to divide the original dimming factor by the preset multiple to obtain the new dimming factor, and generate multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

3. An image processing method, characterized in that, The image processing method includes: To identify an image data to obtain an identification result, the identification result identifies the image data as having low brightness and obtains the original dimming factor of the image data; Adjusting the image data based on the recognition result to obtain new image data includes: performing gamma correction on the image data to obtain the new image data; The new image data is divided into multiple bit planes; The multiple bit planes are respectively stored in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data of each bit plane; Transmit multiple rows of data from the multiple block caches to multiple row caches; Load the multiple rows of data from the row cache into the display unit; and The original dimming factor of the image data is adjusted according to the recognition result to obtain a new dimming factor, and multiple parallel light emission control signals are generated according to the new dimming factor to control the light emission time of multiple pixels of the display unit. The adjustment of the original dimming factor of the image data based on the recognition result to obtain the new dimming factor includes: amplifying the original dimming factor to obtain the new dimming factor, thereby extending the duration of the plurality of light emission control signals.

4. The image processing method according to claim 3, characterized in that, The image processing method is applied to a display device, which includes a main control chip and the display unit. The main control chip includes an image processing module, a memory module, a sequencing module, and a scanning control module, wherein: The original dimming factor of the image data is obtained by the image processing module, and the image processing module is configured to perform γ correction on the image data and divide it into the plurality of bit planes; The memory module is configured to store the multiple bit planes in multiple block caches of the frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; The multiple rows of data from the multiple block caches are transmitted to the multiple row caches of the sequencing module, and the sequencing module is configured to load the multiple rows of data from the row caches into the display unit; The scanning control module is configured to amplify the original dimming factor to obtain the new dimming factor, and generate multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit.

5. A display device, characterized in that, The display device includes: The main control chip includes: The image processing module is configured to: recognize an image data to obtain a recognition result; and adjust the image data according to the recognition result to obtain new image data. And the new image data is divided into multiple bit planes; A memory module, coupled to the image processing module, is configured to store multiple bit planes in multiple block caches of at least one frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A sequencing module, coupled to the memory module, wherein the multiple rows of data in the multiple block caches are configured to be transmitted to the row cache of the sequencing module; and A scanning control module, coupled to the sequencing module, is configured to: adjust the original dimming factor of the image data according to the recognition result to obtain a new dimming factor; And control the row selection line of the sequencing module to load the multiple rows of data in the row cache to the display unit; and The display unit is coupled to the sequencing module, and the scanning control module generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit. The image processing module is configured to: obtain the recognition result to identify the image data as low grayscale, and obtain the original pixels and the original dimming factor of the image data; multiply the original pixels of the image data by a preset factor to obtain the new image data with new pixels; The scanning control module is configured to divide the original dimming factor by the preset multiple to obtain the new dimming factor.

6. The display device according to claim 5, characterized in that, The memory module also includes time-slice sequence memory, which adjusts the bit plane corresponding to the read time-slice sequence based on the multiple relationship between the new pixel and the original pixel.

7. A display device, characterized in that, The display device includes: The main control chip includes: The image processing module is configured to: recognize an image data to obtain a recognition result; and adjust the image data according to the recognition result to obtain new image data. And the new image data is divided into multiple bit planes; A memory module, coupled to the image processing module, is configured to store multiple bit planes in multiple block caches of at least one frame buffer of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A sequencing module, coupled to the memory module, wherein the multiple rows of data in the multiple block caches are configured to be transmitted to the row cache of the sequencing module; and A scanning control module, coupled to the sequencing module, is configured to: adjust the original dimming factor of the image data according to the recognition result to obtain a new dimming factor; And control the row selection line of the sequencing module to load the multiple rows of data in the row cache to the display unit; and The display unit is coupled to the sequencing module, and the scanning control module generates multiple parallel light emission control signals based on the new dimming factor to control the light emission time of multiple pixels of the display unit. The image processing module is configured to: obtain the recognition result to identify the image data as low brightness, and obtain the original dimming factor of the image data; perform γ correction on the image data to obtain the new image data; and the scanning control module is configured to: amplify the original dimming factor to obtain the new dimming factor, thereby extending the duration of the plurality of light emission control signals.

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