Non-volatile memory read abort test system

Abstract

The application provides a non-volatile memory read interruption test system. By judging whether the read data of the read interruption request is the same as the test expected value, if yes, the non-volatile memory supports the read interruption operation, which indicates that the non-volatile memory has the dynamic interruption response capability, can be seamlessly switched to a high-priority task in the read process, and significantly improves the real-time performance of the non-volatile memory. If not, the non-volatile memory does not support the read interruption operation, which can simplify the software design of the non-volatile memory, avoid the additional overhead and delay caused by processing interruption, make the data read process more direct and efficient, and be suitable for scenes with high requirements for continuous data read speed. Therefore, the application can verify whether the non-volatile memory supports the read interruption operation, and provides a solution for testing whether the non-volatile memory supports the read interruption.

Description

Technical Field

[0001] The embodiments of this application belong to the field of memory read operation technology, and in particular relate to a non-volatile memory read interruption test system. Background Technology

[0002] In today's era of rapid digital development, non-volatile memory (NDRAM), as a core component for data storage and retrieval, directly impacts the operational efficiency and stability of the entire system. From the perspective of industrial control systems with extremely high real-time requirements, if NDRAM cannot respond promptly to sudden interruptions when reading critical configuration parameters, such as continuing to read even when an emergency stop command is triggered, it may lead to the equipment failing to stop quickly, resulting in a safety accident.

[0003] However, there is a lack of unified and effective verification methods for read interruption operations of existing non-volatile memory. The performance of products from different manufacturers varies, which poses a hidden danger to system stability and security. Therefore, how to verify the read interruption operation support of non-volatile memory has become an urgent technical problem to be solved. Summary of the Invention

[0004] To address or alleviate the technical challenges in existing technologies regarding how to verify read-break operations for non-volatile memory.

[0005] This application provides a non-volatile memory read interruption test system, including an address signal generation module, a first read signal generation circuit, a second read signal generation circuit, a data acquisition and comparison circuit, a signal switching circuit, and a first control circuit;

[0006] The output terminals of the first and second read signal generation circuits are connected to the signal switching circuit, and the signal switching circuit is connected to the first control circuit.

[0007] The address signal generation circuit generates read addresses. The first read signal generation circuit reads test data corresponding to different read addresses in the non-volatile memory with read request cycles greater than the minimum read cycle, and uses this as the test expectation value. The second read signal generation circuit reads read data corresponding to different read addresses in the non-volatile memory in a read interruption manner. The data acquisition and comparison circuit compares the read data at the same address with the test expectation value to determine whether the read data of the read interruption request is the same as the test expectation value. If they are the same, the non-volatile memory supports the read interruption operation; otherwise, the non-volatile memory does not support the read interruption operation.

[0008] The signal switching circuit is used to bypass the logic of the second read signal generation circuit and select the logic from the first read signal generation circuit.

[0009] The first control circuit is used to bypass the logic of the original circuit and select the logic from the read interruption test circuit when a read interruption test is required, so that the non-volatile memory can perform a read operation.

[0010] As a preferred embodiment of this application, it also includes a first parameter configuration module;

[0011] The first parameter configuration module is connected to the first read signal generation circuit and the second read signal generation module, and is used to set the clock frequency of the first read signal and the second read signal.

[0012] As a preferred embodiment of this application, the address signal generation module includes a second parameter configuration module, a read address generation module, and a second control circuit;

[0013] The second parameter configuration module is connected in sequence to the read address generation module and the second control circuit;

[0014] The second parameter configuration module sets the clock frequency for generating the read address. The read address generation module generates the read address based on the clock frequency. The second control circuit bypasses the logic of the original circuit and selects the logic from the read address generation circuit when a read address needs to be generated, so that the non-volatile memory can obtain the read address.

[0015] As a preferred embodiment of this application, the data acquisition and comparison circuit includes a data acquisition circuit, a verification module, and a status storage module;

[0016] The data acquisition circuit, the verification module, and the status storage module are connected in sequence.

[0017] The data acquisition circuit is used to acquire test data obtained from the non-volatile memory at n clock cycles starting from the xth read request.

[0018] The verification circuit is used to verify the data acquired by the data acquisition circuit, compare the test data with the expected test value, and determine whether the read data of the read interruption request is the same as the expected test value. If they are the same, the non-volatile memory supports the read interruption operation; otherwise, the non-volatile memory does not support the read interruption operation.

[0019] The state storage module is used to store the comparison result of the comparison circuit after all the test data in all read addresses has been compared with the corresponding expected test value according to the comparison circuit.

[0020] As a preferred embodiment of this application, the first read signal generation circuit and the second read signal generation circuit include an accumulator, a comparator, a signal switching module, and a trigger.

[0021] The output of the accumulator is connected to the first input of the comparator, the second input of the comparator is connected to the reference input, the output of the comparator is connected to the input of the accumulator, the output of the comparator is also connected to the input of the signal switching module, the output of the signal switching module is connected to the input of the flip-flop; the output of the flip-flop is connected to the first input of the signal switching module, and the output of the flip-flop is connected to the second input of the signal switching module through an inverter.

[0022] The accumulator is used to count the total number of clock cycles with continuous high-level pulses and the total number of clock cycles with continuous high-level pulses, respectively; and compare them with the parameters input at the parameter input terminal; the output signal of the comparator is transmitted to the accumulator to reset the accumulator, and the output signal of the comparator is also transmitted to the signal switching module to realize the flipping of the read request signal within a specific time.

[0023] Compared with existing technologies, this application provides a non-volatile memory read interruption testing system. By determining whether the data read in the read interruption request is the same as the expected test value, if they are the same, the non-volatile memory supports read interruption operations. This indicates that the non-volatile memory has dynamic interrupt response capabilities, allowing seamless switching to high-priority tasks during the reading process, significantly improving the real-time performance of the non-volatile memory. If they are different, the non-volatile memory does not support read interruption operations. This simplifies the software design of non-volatile memory, avoids the additional overhead and latency caused by interrupt handling, and makes the data reading process more direct and efficient. It is suitable for scenarios with high requirements for continuous data reading speed. Therefore, this application can verify whether a non-volatile memory supports read interruption operations, providing a solution for testing whether a non-volatile memory supports read interruption. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0025] Figure 1 This application provides a structural diagram of a non-volatile memory read interruption test system.

[0026] Figure 2This is a structural diagram of the first or second read signal generation circuit provided in the embodiments of this application;

[0027] Figure 3 This is a timing diagram of the pre-read phase operations;

[0028] Figure 4 This is a sequence diagram of the read interrupt phase operations;

[0029] Figure 5 This is another timing diagram of the read interrupt phase operation;

[0030] Figure 6 This is a timing diagram of the pre-read phase, showing the timing relationship of the ADDR / READ signals.

[0031] Figure 7 This is a parameter configuration example for the read interruption test phase, including key parameter settings such as break_seq, BHx / BLx, and SPx. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0033] like Figure 1 As shown, this application provides a non-volatile memory read interruption test system, including an address signal generation module 1, a first read signal generation circuit 101, a second read signal generation circuit 102, a data acquisition and comparison circuit 2, a signal switching circuit 104, and a first control circuit 105.

[0034] The output terminals of the first read signal generating circuit 101 and the second read signal generating circuit 102 are connected to the signal switching circuit 104, and the signal switching circuit 104 is connected to the first control circuit 105.

[0035] The address signal generation circuit 1 generates read addresses. The first read signal generation circuit 101 reads test data corresponding to different read addresses in the non-volatile memory with read request cycles greater than the minimum read cycle, and uses this as the test expectation value. The second read signal generation circuit 102 reads read data corresponding to different read addresses in the non-volatile memory in a read interruption manner. The data acquisition and comparison circuit 2 compares the read data at the same address with the test expectation value to determine whether the read data of the read interruption request is the same as the test expectation value. If they are the same, the non-volatile memory supports the read interruption operation; otherwise, the non-volatile memory does not support the read interruption operation.

[0036] The signal switching circuit 104 is used to bypass the logic of the second read signal generation circuit 102 and select the logic from the first read signal generation circuit 101.

[0037] The first control circuit 105 is used to bypass the logic of the original circuit and select the logic from the read interruption test circuit when a read interruption test is required, so that the non-volatile memory can perform a read operation.

[0038] As a preferred embodiment of this application, it also includes a first parameter configuration module 103;

[0039] The first parameter configuration module 103 is connected to the first read signal generation circuit 101 and the second read signal generation module 102, and is used to set the clock frequency of the first read signal and the second read signal.

[0040] As a preferred embodiment of this application, the address signal generation module 1 includes a second parameter configuration module 106, a read address generation module 107, and a second control circuit 108;

[0041] The second parameter configuration module 106 is connected in sequence to the read address generation module 107 and the second control circuit 108;

[0042] The second parameter configuration module 106 sets the clock frequency for setting the read address. The read address generation module 107 generates a read address based on the clock frequency. The second control circuit 108 bypasses the logic of the original circuit and selects the logic from the read address generation circuit when a read address needs to be generated, so that the non-volatile memory can obtain a read address.

[0043] As a preferred embodiment of this application, the data acquisition and comparison circuit 2 includes a data acquisition circuit 111, a verification module 110, and a status storage module 109;

[0044] The data acquisition circuit 111, the verification module 110, and the status storage module 109 are connected in sequence;

[0045] The data acquisition circuit 111 is used to acquire test data obtained from the non-volatile memory at n clock cycles starting from the xth read request.

[0046] The verification circuit 110 is used to verify the data acquired by the data acquisition circuit, compare the test data with the test expectation value, and determine whether the read data of the read interruption request is the same as the test expectation value. If they are the same, the non-volatile memory supports the read interruption operation; otherwise, the non-volatile memory does not support the read interruption operation.

[0047] The state storage module 109 is used to store the comparison result of the comparison circuit after all the test data in all read addresses have been compared with the corresponding expected test values ​​according to the comparison circuit.

[0048] like Figure 2 As shown, the first read signal generation circuit 101 and the second read signal generation circuit 102 include an accumulator 112, a comparator 113, a signal switching module 114, and a trigger 115;

[0049] The output of the accumulator 112 is connected to the first input of the comparator 113, the second input of the comparator 113 is connected to the reference input, the output of the comparator 113 is connected to the input of the accumulator 112, the output of the comparator 113 is also connected to the input of the signal switching module 114, the output of the signal switching module 114 is connected to the input of the trigger 115; the output of the trigger 115 is connected to the first input of the signal switching module, and the output of the trigger 115 is connected to the second input of the signal switching module 114 through an inverter 116.

[0050] The accumulator 112 is used to count the total number of clock cycles with continuous high-level pulses and the total number of clock cycles with continuous high-level pulses respectively; and compare them with the parameters input at the parameter input terminal; the output signal of the comparator 113 is transmitted to the accumulator to reset the accumulator 115, and the output signal of the comparator 113 is also transmitted to the signal switching module to realize the flipping of the read request signal within a specific time.

[0051] The testing methods using the testing system provided in this application are as follows:

[0052] Step 1: Test data pre-writing

[0053] Test data is pre-programmed into the non-volatile memory under test (hereinafter referred to as NVM). The data format can be, but is not limited to, the following: byte format: 0xFF; double-byte format: 0xFF00; word format: 0xFFFF0000, 0xFFFFFFFF, 0x00000000, etc. The data writing process can be implemented using the NVM controller.

[0054] Step Two: Pre-reading Stage Operation

[0055] like Figure 3 As shown, the circuit is switched to the pre-read signal mode through a signal switching structure;

[0056] The first read signal generation circuit generates a pre-read signal based on an external high-frequency clock CLK, with a clock frequency ≥ 2 times the normal read clock frequency and a pulse width of N CLK cycles; the address signal generation circuit synchronously generates an address signal (offset + A0~A15); and completes 16 consecutive normal read operations to obtain the pre-read data.

[0057] Step 3: Read Interruption Phase Operation

[0058] like Figure 4 and Figure 5 As shown, the first read signal generation circuit generates a read interrupt signal, including:

[0059] Read interrupt sequence: The duty cycle of the READ signal is adjustable, controlled by the parameters Bx_H and Bx_L.

[0060] Normal read sequence: The duty cycle of the READ signal is fixed at 50%;

[0061] The sequence type is controlled by the break_seq parameter (0 - normal reading, 1 - reading interrupted).

[0062] The address signal generation circuit generates the same address signal (offset + A0~A15) again; 16 read operations are completed based on the external high-frequency clock CLK (frequency ≥ 2 times the normal read clock frequency), with pulse degrees of M (read interruption) and L (normal read) clock CLK cycles respectively.

[0063] Step 4: Data Comparison and Analysis

[0064] The data acquisition and comparison circuit performs the following operations:

[0065] Data acquisition: The acquisition time is controlled by the SPx parameter, which determines the interval between the read signal READ and the CLK cycle of data acquisition;

[0066] Data comparison: Supports three comparison rules: (1) If the data is the same, it is considered to pass; (2) If the data is different, it is considered to fail; (3) No comparison is made; Complete the comparison of 16 sets of expected values ​​and actual read data.

[0067] Step 5: Full Address Space Testing

[0068] Repeat steps two through four to traverse the entire address space of the NVM. When all address data comparisons meet the set rules, it is determined that the memory supports the read interruption function.

[0069] This application embodiment reads the expected value normally and then interrupts the read operation to read data, comparing the two sets of data. Each read operation reads 16 words, but is not limited to 16 words; it can be values ​​within a reasonable range such as 8, 32, or 64 words. A read interrupt signal is generated by changing the duty cycle of the read signal. A complete read signal consists of a high level followed by a low level, but is not limited to a high level followed by a low level; it can also be a low level followed by a high level, or other reasonable forms. The expected value is compared with the read-back value during the read interruption. The comparison method can be word-by-word comparison (equalities, unequalities, or no comparison), but is not limited to this form; it can also be byte-by-byte, bit-by-bit, etc.

[0070] The following detailed embodiments of the non-volatile memory read interruption function testing system provided in this application are described in detail. Simulation tests, based on test data burned into the NVM, simulate actual read interruption scenarios according to the configured read interruption sequence. Alternating pre-fetching and read interruption reading methods are used to obtain the expected value and comparison value respectively. The system achieves the purpose of accessing the expected value using relatively few resources and automatically completes the comparison according to the set method, enabling the test of the read interruption function in a short time.

[0071] Test implementation process:

[0072] Step 1: Test Data Initialization

[0073] 1. Burn the test data into the non-volatile memory (NVM) under test.

[0074] 2. Data writing can be completed using a reusable NVM controller.

[0075] 3. Recommended test data format (customizable):

[0076] Byte format: 0xFF; Double-byte format: 0xFF00; Word format: 0xFFFF0000, 0xFFFFFFFF, 0x00000000, etc.

[0077] Step 2: Test Mode Configuration

[0078] By switching to test mode through the control circuit, the structure will bypass the logic of the original circuit and select the logic of the read interrupt test circuit.

[0079] Set the test clock CLK frequency to 10 times the normal read signal frequency using the parameter configuration module.

[0080] Step 3: Pre-reading stage operation

[0081] To achieve real-time comparison without prior storage, a pre-reading phase is first implemented. This phase uses read requests with a read cycle longer than the minimum read cycle to group data from the NVM as expected values. Specifically, a group of expected values ​​is read, then data from the same address group in the NVM is read in a read-interrupted manner, compared, then another group of expected values ​​is updated, and so on, with the same read-interrupted manner repeated. This cyclical reading process is repeated.

[0082] like Figure 2 As shown, the first and second read signal generation circuits have similar structures, both including an accumulator, a comparator, a signal switching module, and a flip-flop. The difference between the first and second read signal generation circuits is that the input parameters are different. The accumulator counts BHx and BLx. It compares the count with the set parameters. The comparator output is split into two paths: one returns to the accumulator to reset it, and the other is sent to the signal switching module to switch the signal. The signal switching module is used to implement the toggling of the read request signal within a specific time period.

[0083] The first step is the pre-fetch operation:

[0084] The signal switching structure switches to the pre-read signal generation module. At this time, the structure bypasses the logic of the second read signal generation circuit and selects the logic from the first read signal generation circuit.

[0085] like Figure 6 As shown, a pre-read operation is performed in groups of 16 data entries. First, the address signal generation circuit sequentially generates 16 addresses from offset+A0 to A15. The first read signal generation circuit generates the corresponding read signal READ and timing parameters: the address signal ADDRn is generated on the rising edge of CLK, corresponding to a READ signal duty cycle of 50%, and each read address lasts for 12 CLK cycles. Step 2 explains that the test clock CLK frequency is set to 10 times the frequency of the normal read signal, meaning 10 clock cycles constitute one minimum read request cycle. Here, 12 cycles are set, with 2 as a margin.

[0086] The desired data is acquired at the rising edge of the same clock cycle when the read address switches from ADDRn to ADDRn+1. This operation meets the timing requirements of synchronous design in general digital circuits.

[0087] Step 4: Read interruption test phase

[0088] The data in the same set of addresses in step 3 is read in a way that simulates a real read interruption scenario. The read interruption scenario means that this set of read requests includes both normal read request pulses and read interruption pulses. The period of a normal read request is greater than the minimum read period, while a read interruption refers to actively inserting a new read request during the normal read request period.

[0089] The read interruption test phase is as follows:

[0090] 1. When the signal switching circuit selects the second read signal generation circuit, the structure will bypass the logic of the first read signal generation circuit and select the logic from the second read signal generation circuit.

[0091] 2. Read data from the same 16 addresses in step 3 using a read-interrupt method:

[0092] First, the signal reading mode is controlled by the break_seq parameter:

[0093] 0: Normal read sequence (50% duty cycle, high and low level time AT=6 CLK), indicating that this read request is a pulse signal that satisfies the minimum read cycle.

[0094] 1: Read interruption sequence (duty cycle adjustable, BHx / BLx controls the high and low level time), indicating that the read request is a read interruption request signal that interrupts the normal read request, which means that the read request does not meet the minimum read cycle requirement.

[0095] like Figure 7 As shown, the implementation case parameter configuration is as follows:

[0096] break_seq: [1,1,0,0,1,...,0,0].

[0097] BHx settings: BH0=2, BH1=2, BH4=2, ... The value of BHx represents the number of clock cycles the high-level pulse lasts.

[0098] BLx settings: BL0=2, BL1=2, BL4=2, ... The value of BLx represents how many clock cycles the low-level pulse lasts.

[0099] Step 5: Data Comparison and Analysis

[0100] 1. Data Acquisition:

[0101] The acquisition time is controlled by the SPx parameter, where the value of SPx represents the interval of SPx clock cycles starting from the xth read request.

[0102] Implementation examples: SP0=5, SP1=3, SP2=10, ..., SP15=10

[0103] 2. Data Comparison:

[0104] Three comparison rules are supported: (1) If the data is the same, the comparison is passed; (2) If the data is different, the comparison is failed; (3) No comparison is performed.

[0105] 3. Result determination:

[0106] According to the set comparison rules, after all comparisons of the entire address space are completed, if all comparisons pass, it can be determined that the NVM supports the read interruption function, and the results are stored in the state storage module.

[0107] Test process loop:

[0108] Repeat steps 3-5 to traverse the entire address space of NVM to complete a comprehensive test.

[0109] This application's implementation case achieves efficient and accurate non-volatile memory read interruption function testing through a highly integrated hardware structure and configurable test parameters.

[0110] The non-volatile memory read interruption function test structure provided in this application has the following significant advantages:

[0111] 1. High-efficiency testing capabilities

[0112] By alternately performing pre-fetch and read interruption read operations, the expected value and the actual value are automatically obtained;

[0113] By employing on-chip data acquisition and comparison circuitry, real-time comparison is achieved, significantly shortening the testing cycle.

[0114] Actual testing showed that the read interruption function for a single address group can be completed within μs.

[0115] 2. Resource optimization design

[0116] The address signal generation circuit (300) and clock control module are reused to reduce the cost of coupling with the original functional blocks;

[0117] Hardware resource sharing is achieved through a pre-read signal / read interrupt signal switching structure (101).

[0118] 3. High-precision testing

[0119] Supports bit-level data comparison and can detect single-bit flip errors;

[0120] Timing control precision reaches 1 CLK cycle (e.g.) Figure 7 (as shown in the timing waveform)

[0121] Three configurable comparison rules meet the needs of different testing scenarios.

[0122] 4. Comprehensive scene coverage

[0123] The break mode (continuous / intermittent) can be flexibly configured by reading the break control parameter break_seq.

[0124] Supports simulating random interruption scenarios in real SoCs

[0125] It can reproduce timing violations caused by environmental factors such as power supply noise.

[0126] 5. Automated Testing Process

[0127] The entire process, from data acquisition and timing control to result comparison, is automated.

[0128] Built-in self-test (BIST) function reduces external intervention.

[0129] A single test can cover the entire address space (e.g.) Figure 6 Test coverage analysis).

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A non-volatile memory read interruption test system, characterized in that, It includes an address signal generation circuit, a first read signal generation circuit, a second read signal generation circuit, a data acquisition and comparison circuit, a signal switching circuit, and a first control circuit; The output terminals of the first and second read signal generation circuits are connected to the signal switching circuit, and the signal switching circuit is connected to the first control circuit. The address signal generation circuit generates a read address, and the first read signal generation circuit reads test data corresponding to different read addresses in the non-volatile memory with a read request period greater than the minimum read period, as test expected values. The second read signal generation circuit reads the read data corresponding to different read addresses in the non-volatile memory in the form of read interruption. The data acquisition and comparison circuit compares the read data at the same address with the test expectation value to determine whether the read data of the read interruption request is the same as the test expectation value. If they are the same, the non-volatile memory supports the read interruption operation. Otherwise, the non-volatile memory does not support read interruption operations; The signal switching circuit is used to bypass the logic of the second read signal generation circuit and select the logic from the first read signal generation circuit. Alternatively, it can be used to bypass the logic of the first read signal generation module circuit and to select the logic from the second read signal generation circuit. The first control circuit is used to bypass the logic of the original circuit and select the logic from the read interruption test circuit when a read interruption test is required, so that the non-volatile memory can perform a read operation.

2. The non-volatile memory read interruption test system as described in claim 1, characterized in that, It also includes a first parameter configuration module; The first parameter configuration module is connected to the first read signal generation circuit and the second read signal generation module, and is used to set the clock frequency of the first read signal and the second read signal.

3. The non-volatile memory read interruption test system as described in claim 1, characterized in that, The address signal generation circuit includes a second parameter configuration module, a read address generation module, and a second control circuit. The second parameter configuration module is connected in sequence to the read address generation module and the second control circuit; The second parameter configuration module sets the clock frequency for generating the read address. The read address generation module generates the read address based on the clock frequency. The second control circuit bypasses the logic of the original circuit and selects the logic from the read address generation circuit when a read address needs to be generated, so that the non-volatile memory can obtain the read address.

4. The non-volatile memory read interruption test system as described in claim 1, characterized in that, The data acquisition and comparison circuit includes a data acquisition circuit, a verification circuit, and a status storage module; The data acquisition circuit, the verification circuit, and the status storage module are connected in sequence. The data acquisition circuit is used to acquire test data obtained from the non-volatile memory at n clock cycles starting from the xth read request. The verification circuit is used to verify the data acquired by the data acquisition circuit, compare the test data with the test expectation value, and determine whether the read data of the read interruption request is the same as the test expectation value. If they are the same, the non-volatile memory supports the read interruption operation. Otherwise, the non-volatile memory does not support read interruption operations; The state storage module is used to store the comparison result of the comparison circuit after all the test data in all read addresses has been compared with the corresponding expected test value according to the comparison circuit.

5. The non-volatile memory read interruption test system as described in claim 1, characterized in that, The first read signal generation circuit and the second read signal generation circuit include an accumulator, a comparator, a signal switching module, and a flip-flop; The output of the accumulator is connected to the first input of the comparator, the second input of the comparator is connected to the first parameter configuration module, the output of the comparator is connected to the input of the accumulator, the output of the comparator is also connected to the input of the signal switching module, the output of the signal switching module is connected to the input of the flip-flop; the output of the flip-flop is connected to the first input of the signal switching module, and the output of the flip-flop is connected to the second input of the signal switching module through an inverter. The accumulator is used to count the total number of clock cycles with continuous high-level pulses and the total number of clock cycles with continuous high-level pulses, respectively; and compare them with the parameters input by the first parameter configuration module; the output signal of the comparator is transmitted to the accumulator to reset the accumulator, and the output signal of the comparator is also transmitted to the signal switching module to realize the toggling of the read request signal within a specific time.

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