Sgt device and method of manufacturing the same

Abstract

The application discloses an SGT device, comprising: a gate trench formed in a first epitaxial layer, a multilayer stepped polysilicon field plate is formed in the gate trench; each layer of the stepped polysilicon field plate and the corresponding gate trench are separated by a field plate dielectric layer, each field plate dielectric layer is formed by stacking multiple layers of dielectric sub-layers, the materials between the adjacent two layers of dielectric sub-layers are different and can realize selective etching. The width of each layer of the stepped polysilicon field plate is defined by the thickness of the corresponding field plate dielectric layer, from the bottom to the top of the gate trench, the number of dielectric sub-layers contained in the corresponding field plate dielectric layer of each layer of the stepped polysilicon field plate gradually decreases, the thickness of the field plate dielectric layer gradually decreases and the width of each layer of the stepped polysilicon field plate gradually increases, which is used for optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench. The application also provides a manufacturing method of the SGT device. The application can optimize the longitudinal distribution of the electric field intensity in the drift region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to an SGT device; this invention also relates to a method for manufacturing a shielded gate trench (SGT) device. Background Technology

[0002] Two important fundamental characteristics of power MOSFETs are their on-resistance (R0). dson ) and breakdown voltage (V BR Rdson is the resistance that measures the conduction resistance, and it is an important parameter for measuring the static energy loss when the device is conducting. BR This is a parameter that measures the voltage it can block when turned off. Existing traditional VDMOS devices achieve their breakdown voltage through a lightly doped drift region, where the depletion layer electric field distribution is triangular. BR and on-resistance R dson Satisfy the following formula: .

[0003] The above formula is known as the silicon limit. To overcome this limit, different device structures have emerged, such as super junctions and split gates. For example, in split-gate devices, to achieve a low specific on-resistance, the cell size (W) needs to be reduced. FP ), increase the doping concentration in the drift region (N) FP The corresponding formula is: .

[0004] SGTs typically achieve high breakdown voltage (BV) by depleting the N-type drift region through deep trenches and thick oxide layers. However, because the polysilicon in an SGT is usually heavily doped, it has an isopotential during reverse breakdown of the MOSFET, resulting in a catenary-like electric field distribution in the drift region of the semiconductor. Figure 1 These are the electric field intensity distribution curves in the drift region of existing SGT devices. Figure 1 The curve in the figure has a catenary structure. The electric field strength in the middle region of the drift region is low. Since the breakdown voltage is the integral of the electric field strength with respect to the depth, the area enclosed by the curve will decrease after the electric field strength decreases, so the breakdown voltage will decrease. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide an SGT device that can realize a stepped polycrystalline silicon field plate and a field plate dielectric layer, and the width of each stepped polycrystalline field plate can be precisely controlled, thereby optimizing the longitudinal distribution of the electric field intensity in the drift region and improving the device's breakdown voltage. To this end, this invention also provides a method for manufacturing an SGT device.

[0006] To solve the above-mentioned technical problems, the SGT device provided by the present invention includes: a gate trench formed in a first epitaxial layer doped with a first conductivity type.

[0007] A trench field plate formed in the gate trench is formed by stacking multiple stepped polysilicon field plates; a field plate dielectric layer is spaced between each of the stepped polysilicon field plates and the corresponding gate trench, and each of the field plate dielectric layers is formed by stacking multiple dielectric sublayers.

[0008] The width of each stepped polysilicon field plate is defined by the thickness of the corresponding field plate dielectric layer. From the bottom to the top of the gate trench, the number of dielectric sub-layers contained in the field plate dielectric layer of each stepped polysilicon field plate gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each stepped polysilicon field plate gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0009] The materials between two adjacent dielectric sublayers are different and selective etching can be achieved. The dielectric layer of the field plate corresponding to each layer of the stepped polysilicon field plate after removing all or part of the thickness of the topmost dielectric sublayer above the top surface of the stepped polysilicon field plate is used as the dielectric layer of the next layer of the stepped polysilicon field plate.

[0010] A first inter-electrode dielectric layer is formed on the top surface of the trench field plate.

[0011] A gate conductive material layer is filled in the gate trench above the top surface of the first inter-electrode dielectric layer, and a gate dielectric layer is spaced between the gate conductive material layer and the sidewalls of the gate trench.

[0012] A further improvement is that a channel region doped with a second conductivity type is formed in the surface region of the first epitaxial layer, and the gate conductive material layer extends longitudinally through the channel region.

[0013] The drift region is formed by the first epitaxial layer at the bottom of the channel region.

[0014] A source region of a first conductivity type is formed in the surface region of the channel region, and the source region is aligned with the sidewall of the gate trench.

[0015] The gate conductive material layer is connected to the gate, which is composed of a front metal layer group.

[0016] The source region is connected to the source electrode, which is composed of the front metal layer.

[0017] A further improvement is that the stepped polysilicon field plates of each layer of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source electrode.

[0018] A further improvement is that a second inter-electrode dielectric layer is formed on the top surface of at least one of the stepped polysilicon field plates; the electrodes connected to the two stepped polysilicon field plates separated by the second inter-electrode dielectric layer are independent of each other.

[0019] A further improvement is that the bottommost stepped polycrystalline silicon field plate is connected to the source electrode.

[0020] The potential of the electrodes connected to each of the stepped polysilicon field plates that are not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0021] A further improvement is that the thickness of the dielectric layer of the stepped polysilicon field plate corresponding to each layer is set according to the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased. The greater the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased, the greater the thickness of the dielectric layer of the corresponding field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0022] A further improvement is that, when the operating voltage of the SGT device is 25V, the thickness of the dielectric layer corresponding to the bottommost stepped polycrystalline silicon field plate is 700Å to 900Å.

[0023] When the operating voltage of the SGT device is 200V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is on the order of µm.

[0024] A further improvement is that the superimposed structure of each dielectric sublayer of the field plate dielectric layer is composed of alternating superimposed dielectric sublayers of two different materials; A further improvement is that the dielectric sublayer of the first material includes an oxide layer, and the dielectric sublayer of the second material includes a nitrided layer.

[0025] A further improvement is that the number of layers of the stepped polycrystalline silicon field plate included in the trench field plate includes two or three or more layers.

[0026] To solve the above-mentioned technical problems, the manufacturing method of the SGT device provided by the present invention includes the following steps: Step 1: Form a gate trench in the first epitaxial layer doped with the first conductivity type.

[0027] Step 2: Form a field plate dielectric layer corresponding to the lowest layer of the stepped polysilicon field plate, which is composed of multiple dielectric sublayers stacked on the inner surface of the gate trench; the materials between adjacent dielectric sublayers are different and selective etching can be achieved.

[0028] Step 3: Use polysilicon deposition and etch-back to form the current layer's stepped polysilicon field plate in the gate trench; the stepped polysilicon field plate formed by the first polysilicon deposition and etch-back is the bottommost stepped polysilicon field plate.

[0029] Step 4: Perform field plate dielectric etching. Remove all or part of the thickness of the topmost dielectric sublayer in the field plate dielectric layer above the top surface of the current layer of the stepped polysilicon field plate, and use the field plate dielectric layer after the field plate dielectric etching as the field plate dielectric layer corresponding to the next layer of the stepped polysilicon field plate.

[0030] Step 5: Repeat steps 3 and 4 to obtain a trench field plate formed by stacking multiple layers of the stepped polycrystalline silicon field plates; Step 4 after step 3 for the topmost stepped polycrystalline silicon field plate is omitted.

[0031] From the bottom to the top of the gate trench, the number of dielectric sublayers contained in the field plate dielectric layer corresponding to each of the stepped polysilicon field plates gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each of the stepped polysilicon field plates gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0032] Step 6: Form a first inter-electrode dielectric layer on the top surface of the trench field plate.

[0033] Step 7: Remove all the dielectric layer remaining on the side of the gate trench above the top surface of the first inter-electrode dielectric layer to form a gate dielectric layer.

[0034] Step 8: Fill the gate trench above the top surface of the first inter-electrode dielectric layer with a gate conductive material layer.

[0035] Further improvements include the following steps: A channel region doped with a second conductivity type is formed in the surface region of the first epitaxial layer, and the gate conductive material layer extends longitudinally through the channel region; a drift region is formed by the first epitaxial layer at the bottom of the channel region.

[0036] A source region of a first conductivity type is formed in the surface region of the channel region, and the source region is aligned with the sidewall of the gate trench.

[0037] An interlayer film, contact holes, and a front metal layer are formed. The front metal layer is patterned to form a gate and a source. The gate conductive material layer is connected to the gate. The source region is connected to the source.

[0038] A further improvement is that the stepped polysilicon field plates of each layer of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source electrode.

[0039] A further improvement is that, after step four is completed for at least one of the stepped polysilicon field plates, a second inter-electrode dielectric layer is formed on the top surface of the stepped polysilicon field plate; the electrodes connected to the two stepped polysilicon field plates separated by the second inter-electrode dielectric layer are independent of each other.

[0040] A further improvement is that the bottommost stepped polycrystalline silicon field plate is connected to the source electrode.

[0041] The potential of the electrodes connected to each of the stepped polysilicon field plates that are not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0042] A further improvement is that the thickness of the dielectric layer of the stepped polysilicon field plate corresponding to each layer is set according to the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased. The greater the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased, the greater the thickness of the dielectric layer of the corresponding field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

[0043] A further improvement is that, when the operating voltage of the SGT device is 25V, the thickness of the dielectric layer corresponding to the bottommost stepped polycrystalline silicon field plate is 700Å to 900Å.

[0044] When the operating voltage of the SGT device is 200V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is on the order of µm.

[0045] A further improvement is that the superimposed structure of each dielectric sublayer of the field plate dielectric layer is composed of alternating superimposed dielectric sublayers of two different materials; A further improvement is that the dielectric sublayer of the first material includes an oxide layer, and the dielectric sublayer of the second material includes a nitrided layer.

[0046] A further improvement is that the number of layers of the stepped polycrystalline silicon field plate included in the trench field plate includes two or three or more layers.

[0047] The field plate dielectric layer of this invention is composed of multiple dielectric sublayers stacked together, with each adjacent dielectric sublayer made of a different material. By using the material difference between adjacent dielectric sublayers, selective etching of the dielectric sublayers can be achieved, thereby controlling the thickness of the field plate dielectric layer of each polycrystalline silicon field plate pair, and thus controlling the width of each stepped polycrystalline field plate, and optimizing the longitudinal distribution of the electric field intensity in the drift region. Furthermore, in this invention, by controlling the growth of the dielectric sublayers and combining it with subsequent selective etching of the dielectric sublayers, precise control of the thickness of each field plate dielectric layer can be achieved, thereby enabling precise control of the longitudinal distribution of the electric field intensity in the drift region, and ultimately improving the withstand voltage of the device.

[0048] In this invention, since the processes of each layer of stepped polysilicon field plate are independent of each other, a second inter-electrode dielectric layer can be further formed between each layer of stepped polysilicon field plate to achieve isolation between adjacent stepped polysilicon field plates. In this way, the adjacent stepped polysilicon field plates in the second inter-electrode dielectric layer can be independently connected to the corresponding electrodes. By applying voltage to each electrode independently to each stepped polysilicon field plate, voltage can be applied to each stepped polysilicon field plate according to the need to optimize the electric field intensity distribution in the drift region, so that the electric field intensity distribution in the drift region can be further optimized. Attached Figure Description

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is the electric field intensity distribution curve in the drift region of an existing SGT device; Figure 2 This is a schematic diagram of the structure of the SGT device according to the first embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the SGT device according to the second embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the SGT device according to the third embodiment of the present invention; Figure 5 This is the electric field intensity distribution curve in the drift region of the SGT device according to the first embodiment of the present invention; Figures 6A-6J This is a schematic diagram of the device structure in each step of the manufacturing method of the SGT device according to the first embodiment of the present invention; Figure 7 This is a schematic diagram of the device structure after the formation of the first inter-electrode dielectric layer in the manufacturing method of the SGT device according to the second embodiment of the present invention; Figure 8This is a schematic diagram of the device structure after the formation of the first inter-electrode dielectric layer in the manufacturing method of the SGT device according to the third embodiment of the present invention. Detailed Implementation

[0050] like Figure 2 The diagram shown is a schematic representation of the SGT device according to a first embodiment of the present invention. The SGT device of this embodiment includes a gate trench 102 formed in a first epitaxial layer 2 doped with a first conductivity type. Please refer to [reference needed] for the gate trench 102. Figure 6B As shown.

[0051] A trench field plate formed by stacking multiple stepped polysilicon field plates is formed in the gate trench 102; a field plate dielectric layer is spaced between each stepped polysilicon field plate and the corresponding gate trench 102, and each field plate dielectric layer is formed by stacking multiple dielectric sublayers.

[0052] The width of each stepped polysilicon field plate is defined by the thickness of the corresponding field plate dielectric layer. From the bottom to the top of the gate trench 102, the number of dielectric sub-layers contained in the field plate dielectric layer of each stepped polysilicon field plate gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each stepped polysilicon field plate gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 at the side of the gate trench 102.

[0053] The materials between two adjacent dielectric sublayers are different and selective etching can be achieved. The dielectric layer of the field plate corresponding to each stepped polysilicon field plate, after removing all or part of the thickness of the topmost dielectric sublayer above the top surface of the stepped polysilicon field plate, is used as the dielectric layer of the next stepped polysilicon field plate.

[0054] In the first embodiment of the present invention, the number of stepped polycrystalline silicon field plates included in the trench field plate is 2. Figure 2The diagram also shows two stepped polysilicon field plates, namely stepped polysilicon field plates 4a and 4b; the corresponding two field plate dielectric layers are field plate dielectric layers 3a and 3b, respectively. Field plate dielectric layer 3a is composed of dielectric sublayers 31, 32, and 33 stacked together; field plate dielectric layer 3b is composed of dielectric sublayers 31 and 32 stacked together. It can be seen that the width of the stepped polysilicon field plate 4a is determined by the thickness of the field plate dielectric layer 3a, that is, the width of the gate trench 102 minus twice the thickness of the field plate dielectric layer 3a gives the width of the stepped polysilicon field plate 4a; similarly, the width of the stepped polysilicon field plate 4b is determined by the thickness of the field plate dielectric layer 3b. It can also be seen that the dielectric sublayer 33 above the stepped polysilicon field plate 4a is removed, so the field plate dielectric layer 3b corresponding to the stepped polysilicon field plate 4b has fewer dielectric sublayers 33 than the bottom field plate dielectric layer 3a, thus the thickness of the field plate dielectric layer 3b is reduced. In the first embodiment of the present invention, the thickness of the dielectric sublayer 33 can be precisely controlled by the growth process, so the width of the final stepped polycrystalline silicon field plate 4b can be precisely controlled.

[0055] In the first embodiment of the present invention, the stacked structure of the dielectric sublayers of the field plate dielectric layer is composed of alternating dielectric sublayers of two different materials. The first material dielectric sublayer includes an oxide layer, and the second material dielectric sublayer includes a nitride layer. For example, in some embodiments, dielectric sublayers 31 and 33 are both oxide layers, and dielectric sublayer 32 is a nitride layer. In other embodiments, dielectric sublayers 31 and 33 may also be both oxide layers, and dielectric sublayer 32 may also use other dielectric materials with different etching rates than the oxide layers.

[0056] A first inter-electrode dielectric layer 5 is formed on the top surface of the trench field plate. In some embodiments, the material of the first inter-electrode dielectric layer is an oxide layer.

[0057] A gate conductive material layer 7 is filled in the gate trench 102 above the top surface of the first inter-electrode dielectric layer 5, and a gate dielectric layer 6 is spaced between the gate conductive material layer 7 and the side surface of the gate trench 102.

[0058] In some embodiments, the gate dielectric layer 6 is an oxide layer. The gate conductive material layer 7 is a polysilicon gate.

[0059] In the first embodiment of the present invention, a channel region 8 doped with a second conductivity type is also formed in the surface region of the first epitaxial layer 2, and the gate conductive material layer 7 extends longitudinally through the channel region 8.

[0060] The drift region is formed by the first epitaxial layer 2 at the bottom of the channel region 8. The drift region serves as a withstand voltage layer, that is, the first epitaxial layer 2 serves as a withstand voltage layer. In this embodiment of the invention, the higher the doping concentration of the first epitaxial layer 2 and the lower the thickness of the first epitaxial layer 2, the lower the breakdown voltage that the device can withstand. The doping concentration of the first epitaxial layer 2 can be uniform, or it can be multiple, two or three layers, or it can be gradually varied.

[0061] A source region 9, heavily doped with a first conductivity type, is formed in the surface region of the channel region 8, and the source region 9 is aligned with the side of the gate trench 102.

[0062] The gate conductive material layer 7 is connected to the gate (not shown) which is composed of a front metal layer 12.

[0063] The source region 9 is connected to the source electrode, which is composed of the front metal layer 12, through the contact hole 11 passing through the interlayer membrane 10. Figure 2 The front metal layer 12 shown is the front metal layer 12 that constitutes the source electrode.

[0064] In the first embodiment of the present invention, the SGT device is an SGT MOSFET. A first epitaxial layer 2 is formed on a semiconductor substrate 1. The semiconductor substrate 1 is heavily doped with a first conductivity type and then thinned to serve as a drain region; or the semiconductor substrate 1 is thinned and then subjected to backside implantation with a first conductivity type to form a drain region. A drain electrode (not shown) composed of a backside metal layer is formed on the backside of the drain region.

[0065] In the first embodiment of the present invention, the stepped polysilicon field plates of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source electrode.

[0066] In the first embodiment of the present invention, the thickness of the dielectric layer of the field plate corresponding to each stepped polysilicon field plate is set according to the voltage of the first epitaxial layer 2 at the corresponding position when the SGT device is reverse biased. The larger the voltage of the first epitaxial layer 2 at the corresponding position when the SGT device is reverse biased, the larger the thickness of the corresponding dielectric layer of the field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 at the side of the gate trench 102.

[0067] In some embodiments, when the operating voltage of the SGT device is 25V, the thickness of the dielectric layer corresponding to the bottommost stepped polysilicon field plate is 700Å to 900Å.

[0068] In some embodiments, when the operating voltage of the SGT device is 200V, the thickness of the dielectric layer corresponding to the bottommost stepped polysilicon field plate is on the order of µm.

[0069] In SGT devices with operating voltages between 25V and 200V, the thickness of the dielectric layer of the bottommost stepped polysilicon field plate can be set between 700Å and 900Å and in the µm range.

[0070] In the first embodiment of the present invention, the SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the SGT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0071] In the first embodiment of the present invention, the field plate dielectric layer is composed of multiple layers of dielectric sublayers stacked together, and the materials of each adjacent dielectric sublayer are different. By using the different materials between adjacent dielectric sublayers, selective etching of the dielectric sublayers can be achieved, thereby controlling the thickness of the field plate dielectric layer of each polycrystalline silicon field plate pair, and thus controlling the width of each stepped polycrystalline field plate, and optimizing the longitudinal distribution of the electric field intensity in the drift region. Moreover, in the first embodiment of the present invention, by controlling the growth of the dielectric sublayers and combining it with the subsequent selective etching of the dielectric sublayers, the thickness of each field plate dielectric layer can be precisely controlled, thereby achieving precise control of the longitudinal distribution of the electric field intensity in the drift region, and finally improving the withstand voltage of the device.

[0072] like Figure 5 The figure shows the electric field intensity distribution curve in the drift region of the SGT device according to the first embodiment of the present invention; and Figure 1 Compared to the curves shown, Figure 5 In the curve, the electric field strength in the middle region of the drift region is improved because: compared with the existing structure, if the potential of the drift region corresponding to the same depth of the gate trench is the same, since the thickness of the field plate dielectric layer in the first embodiment of the present invention is smaller, the electric field strength in the drift region at the corresponding position will increase. Therefore, the electric field strength distribution of the drift region can be optimized by setting the stepped polysilicon field plate in the first embodiment of the present invention; the breakdown voltage is the integral of the electric field strength along the depth, so the breakdown voltage can be improved in the end.

[0073] like Figure 3 The diagram shown is a structural schematic of the SGT device according to the second embodiment of the present invention. The difference between the SGT device and the SGT device according to the first embodiment of the present invention is that the SGT device according to the second embodiment of the present invention includes three layers of stepped polysilicon field plates in the trench field plate. Figure 3The image also shows three stepped polycrystalline silicon field layers, namely stepped polycrystalline silicon field layers 4a, 4b, and 4c; the corresponding three field layer dielectric layers are field layer dielectric layers 3a, 3b, and 3c. Field layer dielectric layer 3a is composed of dielectric sublayers 31, 32, and 33 stacked together; field layer dielectric layer 3b is composed of dielectric sublayers 31, 32, and 33a stacked together; field layer dielectric layer 3c is composed of dielectric sublayers 31 and 32 stacked together. Dielectric sublayer 33a is formed by partially etching dielectric sublayer 33.

[0074] In other embodiments, an additional dielectric sublayer can be added, that is, the dielectric sublayer 33 can be replaced with two dielectric sublayers, so that the dielectric sublayer 33a in the field plate dielectric layer 3b is the dielectric sublayer retained after removing the top dielectric sublayer in the dielectric sublayer 33.

[0075] In other embodiments, the trench field plate may include more than three stepped polysilicon field plates. With the depth of the gate trench 102 and the height of the final trench field plate remaining constant, a higher number of stepped polysilicon field plates allows for more precise control of the electric field strength in the drift region, resulting in higher control accuracy. However, this also increases the process cost.

[0076] like Figure 4 The diagram shown is a structural schematic of the SGT device according to the third embodiment of the present invention. The difference between the SGT device and the SGT device according to the second embodiment of the present invention is that in the SGT device of the third embodiment of the present invention: a second inter-electrode dielectric layer is formed on the top surface of at least one stepped polysilicon field plate; the electrodes connected to the two stepped polysilicon field plates isolated by the second inter-electrode dielectric layer are independent of each other.

[0077] The material of the dielectric layer between the second electrodes includes an oxide layer, which is formed by deposition or by directly oxidizing the top surface of the stepped polycrystalline silicon field plate.

[0078] Figure 4 In the trench field plate, the number of stepped polycrystalline silicon field plates included is 3, namely stepped polycrystalline silicon field plates 4a, 4b and 4c; there is a second inter-electrode dielectric layer 13a between stepped polycrystalline silicon field plates 4a and 4b, and there is a second inter-electrode dielectric layer 13b between stepped polycrystalline silicon field plates 4b and 4c.

[0079] The bottom-level stepped polycrystalline silicon field plate 4a is connected to the source.

[0080] The potential of the electrodes connected to each stepped polysilicon field plate that is not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 at the side of the gate trench 102.

[0081] In the third embodiment of the present invention, since the processes of each layer of stepped polysilicon field plate are independent of each other, a second inter-electrode dielectric layer can be further formed between each layer of stepped polysilicon field plate to achieve isolation between adjacent stepped polysilicon field plates. In this way, the adjacent stepped polysilicon field plates in the second inter-electrode dielectric layer can be independently connected to the corresponding electrodes. By applying voltage to each electrode independently to each stepped polysilicon field plate, voltage can be applied to each stepped polysilicon field plate according to the need to optimize the electric field intensity distribution in the drift region, so that the electric field intensity distribution in the drift region can be further optimized. In the third embodiment of the present invention, a capacitor structure is formed between the stepped polysilicon field plate, the field plate dielectric layer and the drift region. At the depth position corresponding to the gate trench, the voltage applied to the stepped polysilicon field plate is also coupled to the drift region through the capacitor, thereby changing the potential of the drift region and finally changing the electric field strength at the corresponding position. Thus, by applying different voltages to the stepped polysilicon field plate at different positions, the electric field strength of the drift region at the corresponding position can also be adjusted, thereby further optimizing the electric field strength distribution of the drift region.

[0082] like Figures 6A to 6J The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the SGT device according to the first embodiment of the present invention. The manufacturing method of the SGT device according to the first embodiment of the present invention includes the following steps: Step 1, such as Figure 6A As shown, a first epitaxial layer 2 is provided, which is doped with a first conductivity type.

[0083] In the method of the first embodiment of the present invention, the first epitaxial layer 2 is formed on the surface of a semiconductor substrate 1 heavily doped with a first conductivity type, such as a silicon substrate, and the material of the first epitaxial layer 2 also includes silicon.

[0084] The first epitaxial layer 2 serves as a withstand voltage layer. The higher the doping concentration of the first epitaxial layer 2 and the lower its thickness, the lower the breakdown voltage that the device can withstand. The doping concentration of the first epitaxial layer 2 can be uniform, multi-layered, two-layered, three-layered, or gradually varied.

[0085] like Figure 6B As shown, a gate trench 102 is formed in the first epitaxial layer 2 doped with the first conductivity type.

[0086] In the method of the first embodiment of the present invention, a hard mask layer 101 is also used.

[0087] First, a hard mask layer 101 is formed on the top surface of the first epitaxial layer 2. The hard mask layer 101 is typically a SiO2 or SiO2+Si4N3+SiO2 stacked structure.

[0088] Next, photolithography is performed to define the formation region of the gate trench 102.

[0089] The hard mask layer 101 and the first epitaxial layer 2 are then etched sequentially to form the gate trench 102. The etching depth of the gate trench 102 depends on the breakdown voltage of the device; the higher the breakdown voltage required by the device, the deeper the etching depth.

[0090] After the gate trench 102 is etched, the process also includes: Sacrificial oxide (SAC) growth and removal are performed to repair the morphology of the etched silicon surface. Common SAC oxide conditions are to grow a 200 Å or 250 Å oxide layer at 900 °C; then remove the oxide; and then remove the hard mask layer 101.

[0091] Step Two, as follows Figure 6C As shown, a field plate dielectric layer 3a, which is the lowest layer of a stepped polysilicon field plate formed by stacking multiple dielectric sublayers, is formed on the inner surface of the gate trench 102; the materials between adjacent dielectric sublayers are different and selective etching can be achieved.

[0092] The method of the first embodiment of the present invention is to manufacture Figure 2 The first embodiment of the present invention, exemplified by the SGT device, is described below. Figure 6C The field plate dielectric layer 3a formed therein is composed of dielectric sublayers 31, 32 and 33 stacked together. The field plate dielectric layer 3a also extends to the surface outside the gate trench 102. In other embodiments, the dielectric sublayer structures of the field plate dielectric layer 3a can also be configured according to actual needs.

[0093] In the first embodiment of the method of the present invention, the stacked structure of each dielectric sublayer of the field plate dielectric layer is composed of alternating dielectric sublayers of two different materials. The first dielectric sublayer includes an oxide layer, and the second dielectric sublayer includes a nitride layer. For example, in some embodiments, dielectric sublayers 31 and 33 are both oxide layers, and dielectric sublayer 32 is a nitride layer. In other embodiments, dielectric sublayers 31 and 33 may also be both oxide layers, and dielectric sublayer 32 may also use a dielectric material with a different etching rate than the oxide layer.

[0094] Step 3, as follows Figure 6D As shown, a stepped polysilicon field plate of the current layer is formed in the gate trench 102 by polysilicon deposition and etch-back; the stepped polysilicon field plate formed by the first polysilicon deposition and etch-back is the bottommost stepped polysilicon field plate 4a.

[0095] Step 4, as follows Figure 6EAs shown, field plate dielectric etching removes all or part of the thickness of the topmost dielectric sublayer in the field plate dielectric layer above the top surface of the current layer's stepped polysilicon field plate, and uses the etched field plate dielectric layer as the field plate dielectric layer corresponding to the next layer's stepped polysilicon field plate.

[0096] Figure 6E In this embodiment, the dielectric sublayer 33 above the top surface of the stepped polycrystalline silicon field plate 4a is completely removed. In other embodiments, it can also be configured such that the dielectric sublayer 33 above the top surface of the stepped polycrystalline silicon field plate 4a is partially removed, depending on actual needs.

[0097] Step 5: Repeat steps 3 and 4 to obtain a trench field formed by stacking multiple stepped polycrystalline silicon field plates; Step 4 after step 3 for the topmost stepped polycrystalline silicon field plate is omitted.

[0098] like Figure 6F As shown, in the method of the first embodiment of the present invention, the stepped polycrystalline silicon field plate has two layers. The stepped polycrystalline silicon field plate 4b formed in the second step three is the topmost stepped polycrystalline silicon field plate, and the subsequent step four does not need to be repeated.

[0099] From the bottom to the top of the gate trench 102, the number of dielectric sublayers contained in the field plate dielectric layer corresponding to each stepped polysilicon field plate gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each stepped polysilicon field plate gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 at the side of the gate trench 102.

[0100] Step Six, as Figure 6H As shown, a first inter-electrode dielectric layer 5 is formed on the top surface of the trench field plate.

[0101] In the method of the first embodiment of the present invention, the first inter-electrode dielectric layer 5 is an oxide layer.

[0102] like Figure 6G As shown, an oxide layer 5a is first formed using an oxide deposition process, such as HDP CVD, to completely fill the gate trench 102. Typically, CMP is performed after the oxide deposition process to remove the oxide layer 5a outside the gate trench 102.

[0103] like Figure 6H As shown, the oxide layer 5a is etched to form the first inter-electrode dielectric layer 5.

[0104] In other embodiments, the method may also involve oxidizing the topmost stepped polycrystalline silicon field plate to form a first inter-electrode dielectric layer 5.

[0105] Step 7, as follows Figure 6IAs shown, the dielectric layer remaining on the side of the gate trench 102 above the top surface of the first inter-electrode dielectric layer 5 is removed to form the gate dielectric layer 6.

[0106] In the method of the first embodiment of the present invention, the gate dielectric layer 6 is an oxide layer, which is formed by a thermal oxidation process.

[0107] Step 8, as Figure 6J As shown, the gate conductive material layer 7 is filled into the gate trench 102 above the top surface of the first inter-electrode dielectric layer 5.

[0108] In the method of the first embodiment of the present invention, the gate conductive material layer 7 is a polysilicon gate.

[0109] It also includes the following steps: like Figure 2 As shown, a channel region 8 doped with a second conductivity type is also formed in the surface region of the first epitaxial layer 2, and the gate conductive material layer 7 extends longitudinally through the channel region 8; the drift region is formed by the first epitaxial layer 2 at the bottom of the channel region 8.

[0110] A source region 9, heavily doped with a first conductivity type, is formed in the surface region of the channel region 8, and the source region 9 is aligned with the side of the gate trench 102.

[0111] An interlayer film 10, a contact hole 11, and a front metal layer 12 are formed. The front metal layer 12 is patterned to form a gate and a source. A gate conductive material layer 7 is connected to the gate. A source region 9 is connected to the source.

[0112] SGT devices are SGT MOSFETs. After the front-side process is completed, the following back-side process is also included: The first epitaxial layer 2 is formed on the semiconductor substrate 1, which is heavily doped with a first conductivity type. The semiconductor substrate 1 is thinned, and the thinned semiconductor substrate 1 forms the drain region. Alternatively, after thinning the semiconductor substrate 1, a backside implantation with heavy doping of the first conductivity type is performed to form the drain region.

[0113] A drain electrode (not shown) consisting of a back metal layer is then formed on the back side of the drain region.

[0114] In the method of the first embodiment of the present invention, the stepped polycrystalline silicon field plates of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source.

[0115] The thickness of the dielectric layer of each stepped polysilicon field plate is set according to the voltage of the first epitaxial layer 2 at the corresponding position when the SGT device is reverse biased. The greater the voltage of the first epitaxial layer 2 at the corresponding position when the SGT device is reverse biased, the greater the thickness of the dielectric layer of the corresponding field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 on the side of the gate trench 102.

[0116] In some embodiments, when the operating voltage of the SGT device is 25V, the thickness of the dielectric layer corresponding to the bottommost stepped polysilicon field plate is 700Å to 900Å.

[0117] When the operating voltage of the SGT device is 200V, the thickness of the dielectric layer corresponding to the bottommost stepped polysilicon field plate is on the order of µm.

[0118] In SGT devices with operating voltages between 25V and 200V, the thickness of the dielectric layer of the bottommost stepped polysilicon field plate can be set between 700Å and 900Å and in the µm range.

[0119] like Figure 7 The diagram shown is a schematic representation of the device structure after the formation of the first inter-electrode dielectric layer in the manufacturing method of the SGT device according to the second embodiment of the present invention. The difference between this method and the manufacturing method of the SGT device according to the first embodiment of the present invention is that in the manufacturing method of the SGT device according to the second embodiment of the present invention: step four and step three are added in step five, ultimately forming three stepped polysilicon field plates, namely stepped polysilicon field plates 4a, 4b, and 4c; the corresponding three field plate dielectric layers are field plate dielectric layers 3a, 3b, and 3c. Field plate dielectric layer 3a is formed by stacking dielectric sublayers 31, 32, and 33; field plate dielectric layer 3b is formed by stacking dielectric sublayers 31, 32, and 33a; field plate dielectric layer 3c is formed by stacking dielectric sublayers 31 and 32. Dielectric sublayer 33a is formed by partially etching dielectric sublayer 33.

[0120] like Figure 8 The diagram shown is a schematic diagram of the device structure after the formation of the first inter-electrode dielectric layer in the manufacturing method of the SGT device of the third embodiment of the present invention. The difference between this method and the manufacturing method of the SGT device of the second embodiment of the present invention is that, in the manufacturing method of the SGT device of the second embodiment of the present invention, after the completion of step four corresponding to at least one stepped polysilicon field plate, a second inter-electrode dielectric layer is further formed on the top surface of the stepped polysilicon field plate.

[0121] The material of the dielectric layer between the second electrodes includes an oxide layer, which is formed by deposition or by directly oxidizing the top surface of the stepped polycrystalline silicon field plate.

[0122] Figure 8 In the trench field plate, the number of stepped polycrystalline silicon field plates included is 3, namely stepped polycrystalline silicon field plates 4a, 4b and 4c; there is a second inter-electrode dielectric layer 13a between stepped polycrystalline silicon field plates 4a and 4b, and there is a second inter-electrode dielectric layer 13b between stepped polycrystalline silicon field plates 4b and 4c.

[0123] like Figure 4As shown, after the front metal layer is patterned, the electrodes connected to the two stepped polysilicon field plates separated by the second electrode dielectric layer are independent of each other. Figure 4 In this design, the trench field plate includes three stepped polysilicon field plates: 4a, 4b, and 4c. A second inter-electrode dielectric layer 13a is located between stepped polysilicon field plates 4a and 4b, and a second inter-electrode dielectric layer 13b is located between stepped polysilicon field plates 4b and 4c. The bottommost stepped polysilicon field plate 4a is connected to the source electrode.

[0124] The potential of the electrodes connected to each stepped polysilicon field plate that is not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer 2 at the side of the gate trench 102.

[0125] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An SGT device, characterized in that, include: The gate trench is formed in the first epitaxial layer doped with a first conductivity type; A trench field plate, composed of multiple stepped polycrystalline silicon field plates, is formed in the gate trench. Each layer of stepped polycrystalline silicon field plate and the corresponding gate trench are separated by a field plate dielectric layer, and each field plate dielectric layer is composed of multiple dielectric sublayers stacked together. The width of each stepped polysilicon field plate is defined by the thickness of the corresponding field plate dielectric layer. From the bottom to the top of the gate trench, the number of dielectric sub-layers contained in the field plate dielectric layer of each stepped polysilicon field plate gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each stepped polysilicon field plate gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench. The materials between two adjacent dielectric sublayers are different and selective etching can be achieved. The dielectric layer of the field plate corresponding to each layer of the stepped polysilicon field plate after removing all or part of the thickness of the topmost dielectric sublayer above the top surface of the stepped polysilicon field plate is used as the dielectric layer of the next layer of the stepped polysilicon field plate. A first inter-electrode dielectric layer is formed on the top surface of the trench field plate; A gate conductive material layer is filled in the gate trench above the top surface of the first inter-electrode dielectric layer, and a gate dielectric layer is spaced between the gate conductive material layer and the sidewalls of the gate trench.

2. The SGT device as described in claim 1, characterized in that: A channel region doped with a second conductivity type is also formed in the surface region of the first epitaxial layer, and the gate conductive material layer extends longitudinally through the channel region; The drift region is formed by the first epitaxial layer at the bottom of the channel region; A source region of a first conductivity type is formed in the surface region of the channel region, and the source region is aligned with the side of the gate trench. The gate conductive material layer is connected to the gate, which is composed of a front metal layer group. The source region is connected to the source electrode, which is composed of the front metal layer.

3. The SGT device as described in claim 2, characterized in that: The stepped polysilicon field plates of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source electrode.

4. The SGT device as described in claim 2, characterized in that: At least one of the stepped polysilicon field plates has a second inter-electrode dielectric layer formed on its top surface; the electrodes connected to the two stepped polysilicon field plates separated by the second inter-electrode dielectric layer are independent of each other.

5. The SGT device as described in claim 4, characterized in that: The bottommost stepped polycrystalline silicon field plate is connected to the source electrode; The potential of the electrodes connected to each of the stepped polysilicon field plates that are not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

6. The SGT device as described in claim 1, characterized in that: The thickness of the dielectric layer of the stepped polysilicon field plate corresponding to each layer is set according to the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased. The greater the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased, the greater the thickness of the dielectric layer of the corresponding field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

7. The SGT device as described in claim 6, characterized in that: When the operating voltage of the SGT device is 25V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is 700Å to 900Å. When the operating voltage of the SGT device is 200V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is on the order of µm.

8. The SGT device as claimed in claim 1, characterized in that: The dielectric sublayer of the field plate dielectric layer is composed of dielectric sublayers made of two different materials stacked alternately.

9. The SGT device as described in claim 8, characterized in that: The dielectric sublayer of the first material includes an oxide layer, and the dielectric sublayer of the second material includes a nitrided layer.

10. The SGT device as claimed in claim 1, characterized in that: The number of layers of the stepped polycrystalline silicon field plate included in the trench field plate includes two or three or more layers.

11. A method for manufacturing an SGT device, characterized in that, Includes the following steps: Step 1: Form a gate trench in the first epitaxial layer doped with the first conductivity type; Step 2: Form a field plate dielectric layer corresponding to the lowest layer of the stepped polysilicon field plate, which is composed of multiple dielectric sublayers stacked together, on the inner surface of the gate trench; the materials between adjacent dielectric sublayers are different and selective etching can be achieved; Step 3: Use polysilicon deposition and etch-back to form the current layer's stepped polysilicon field plate in the gate trench; the stepped polysilicon field plate formed by the first polysilicon deposition and etch-back is the bottommost stepped polysilicon field plate; Step 4: Perform field plate dielectric etching to remove all or part of the thickness of the topmost dielectric sublayer in the field plate dielectric layer above the top surface of the current layer of the stepped polysilicon field plate, and use the field plate dielectric layer after the field plate dielectric etching as the field plate dielectric layer corresponding to the next layer of the stepped polysilicon field plate. Step 5: Repeat steps 3 and 4 to obtain a trench field plate formed by stacking multiple layers of the stepped polycrystalline silicon field plates; Step 4 after step 3 for the topmost stepped polycrystalline silicon field plate is omitted. From the bottom to the top of the gate trench, the number of dielectric sublayers contained in the field plate dielectric layer corresponding to each of the stepped polysilicon field plates gradually decreases, the thickness of the field plate dielectric layer gradually decreases, and the width of each of the stepped polysilicon field plates gradually increases, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench. Step 6: Form a first inter-electrode dielectric layer on the top surface of the trench field plate; Step 7: Remove all the dielectric layer remaining on the side of the gate trench above the top surface of the first inter-electrode dielectric layer and form a gate dielectric layer; Step 8: Fill the gate trench above the top surface of the first inter-electrode dielectric layer with a gate conductive material layer.

12. The method for manufacturing the SGT device as described in claim 11, characterized in that, It also includes the following steps: A channel region doped with a second conductivity type is formed in the surface region of the first epitaxial layer, and the gate conductive material layer extends longitudinally through the channel region; a drift region is formed by the first epitaxial layer at the bottom of the channel region; A source region of a first conductivity type is formed in the surface region of the channel region, and the source region is aligned with the sidewall of the gate trench; An interlayer film, contact holes, and a front metal layer are formed; the front metal layer is patterned to form a gate and a source; the gate conductive material layer is connected to the gate. The source region is connected to the source electrode.

13. The method for manufacturing the SGT device as described in claim 12, characterized in that: The stepped polysilicon field plates of the trench field plate are in contact with each other to form an integral structure, and the trench field plate is connected to the source electrode.

14. The method for manufacturing the SGT device as described in claim 12, characterized in that: After step four is completed for at least one of the stepped polysilicon field plates, a second inter-electrode dielectric layer is formed on the top surface of the stepped polysilicon field plate; the electrodes connected to the two stepped polysilicon field plates separated by the second inter-electrode dielectric layer are independent of each other.

15. The method for manufacturing the SGT device as described in claim 14, characterized in that: The bottommost stepped polycrystalline silicon field plate is connected to the source electrode; The potential of the electrodes connected to each of the stepped polysilicon field plates that are not in contact with the bottommost stepped polysilicon field plate is equal to, greater than or less than the potential of the source electrode, in order to optimize the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

16. The method for manufacturing the SGT device as described in claim 11, characterized in that: The thickness of the dielectric layer of the stepped polysilicon field plate corresponding to each layer is set according to the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased. The greater the voltage of the first epitaxial layer at the corresponding position when the SGT device is reverse biased, the greater the thickness of the dielectric layer of the corresponding field plate, thereby optimizing the longitudinal distribution of the electric field intensity in the first epitaxial layer at the side of the gate trench.

17. The method for manufacturing the SGT device as described in claim 16, characterized in that: When the operating voltage of the SGT device is 25V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is 700Å to 900Å. When the operating voltage of the SGT device is 200V, the thickness of the dielectric layer of the bottommost stepped polycrystalline silicon field plate is on the order of µm.

18. The method for manufacturing the SGT device as described in claim 11, characterized in that: The dielectric sublayer of the field plate dielectric layer is composed of dielectric sublayers made of two different materials stacked alternately.

19. The method for manufacturing the SGT device as described in claim 18, characterized in that: The dielectric sublayer of the first material includes an oxide layer, and the dielectric sublayer of the second material includes a nitrided layer.

20. The method for manufacturing the SGT device as described in claim 11, characterized in that: The number of layers of the stepped polycrystalline silicon field plate included in the trench field plate includes two or three or more layers.

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