A back contact cell, cell assembly and photovoltaic system

Abstract

The application relates to the technical field of solar cells, and particularly discloses a back contact cell, a cell assembly and a photovoltaic system, which comprises a substrate comprising a first surface and a second surface arranged oppositely; a doped layer arranged on the first surface, wherein the doped layer comprises a plurality of first doped layers and second doped layers arranged alternately and having opposite polarities, and at least one adjacent first doped layer and second doped layer have a stacking area stacked with each other, at the stacking area, the second doped layer comprises a stacking segment arranged on a side of the first doped layer away from the first surface; and a cavity arranged between the stacking segment and the first surface at the stacking area, wherein one end of the cavity away from the stacking segment is a bottom end, and the bottom end extends to the inside of the first doped layer at least. The back contact cell can effectively improve the photo-generated current density, and in turn effectively improve the conversion efficiency of the cell. Meanwhile, the problems of fragments and surface film layer peeling caused by the difficulty in stress release of the anti-hot-spot structure in the prior art are avoided, and in turn the long-term stability and reliability of the cell are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a back-contact battery, battery module, and photovoltaic system. Background Technology

[0002] Back-contact (BC) solar cells are a type of solar cell that has gained widespread application in recent years. Their key feature is the presence of alternating N-type and P-type doped layers on the back of the cell, with the positive and negative electrode grids also arranged alternately on the back. This prevents the front of the cell from being blocked by the grids, thus reducing optical losses and improving conversion efficiency. However, in actual operation, back-contact solar cells are prone to localized heating due to the hotspot effect. This heating not only reduces the photoelectric conversion efficiency but also easily leads to localized overheating, potentially damaging the cell structure.

[0003] In the prior art, a common approach to reduce the risk of hot spots is to locally stack adjacent N-type doped layers and P-type doped layers to achieve local recombination contact between the N-type and P-type doped layers, thereby forming an anti-hot spot structure.

[0004] The drawbacks of this heat-resistant structure are twofold. On the one hand, the smooth back surface of the substrate where the stacked region is located results in excessive reflection, leading to poor light utilization at that location. On the other hand, compared to the non-stacked region, the stacked region generates greater local stress under conditions such as heating. Furthermore, the inner doped layer exhibits a smooth, uniform, and continuous morphology, and the doped layer is completely bonded to its adjacent material layer, making it difficult to release stress. This can easily lead to stress concentration, resulting in problems such as fragmentation and surface film peeling. Summary of the Invention

[0005] The purpose of this invention is to provide a back contact battery, battery module and photovoltaic system in light of the existing technology.

[0006] The back-contact battery of this invention can effectively increase the photocurrent density, thereby effectively improving the battery conversion efficiency. At the same time, it avoids problems such as fragmentation and surface film peeling that are easily caused by the difficulty in releasing stress in the anti-hot spot structure of existing technologies, thus effectively improving the long-term stability and reliability of the battery.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: On one hand, the present invention provides a back contact battery, comprising: The substrate includes a first surface and a second surface disposed opposite to each other; A doped layer is disposed on the first surface. The doped layer includes a plurality of alternating first doped layers and second doped layers with opposite polarities, and at least one adjacent first doped layer and second doped layer have a stacked region between them. In the stacked region, the second doped layer includes a stacked segment, which is disposed on the side of the first doped layer facing away from the first surface. A cavity is provided in the stacked region and between the stacked segment and the first surface. The end of the cavity away from the stacked segment is the bottom end, which extends at least into the interior of the first doped layer.

[0008] In some embodiments, the end of the cavity away from the first surface is at least covered by the stacked segment.

[0009] In some embodiments, in the thickness direction of the substrate, the width of the cavity decreases in a direction away from the laminate segment.

[0010] In some embodiments, the bottom end of at least one of the cavities extends through the first doped layer.

[0011] In some embodiments, an insulating dielectric layer is further included, which is at least partially disposed between the first doped layer and the stacked segment.

[0012] In some embodiments, the insulating dielectric layer includes pores, and the orthographic projection of the pores onto the first surface in the thickness direction of the substrate at least partially coincides with the orthographic projection of the cavity onto the first surface.

[0013] In some embodiments, at least a portion of the inner wall of at least one cavity is covered with a first inner deposition layer, wherein the first inner deposition layer is a stack of any one or more of a third interface passivation layer, a third doping layer, and a mixed doping layer, wherein the polarity of the third doping layer is the same as that of the second doping layer, and the mixed doping layer is a silicon material layer doped with N-type doping elements and P-type doping elements.

[0014] In some embodiments, the pores are filled with a fourth doped layer, the polarity of which is the same as that of the second doped layer; or... The hole contains unfilled voids.

[0015] In some embodiments, at least one of the cavities is covered with a second inner deposition layer at one end near the stacked segment. The second inner deposition layer is a stack of one or more of a fifth doped layer and a co-doped layer. The polarity of the fifth doped layer is the same as that of the second doped layer. The co-doped layer is a silicon material layer doped with N-type dopant and P-type dopant.

[0016] In some embodiments, within the orthogonal projection range of the laminated segment in the thickness direction of the substrate, a single unit area of ​​10μm×10μm contains 1 to 64 cavities.

[0017] In some embodiments, a first interface passivation layer is provided between the first doped layer and the first surface.

[0018] In some embodiments, the bottom end of at least one of the cavities penetrates the first doped layer and extends at least into the interior of the first interface passivation layer.

[0019] In some embodiments, the bottom end of at least one of the cavities penetrates the first doped layer and extends at least to the first surface.

[0020] In some embodiments, the bottom end of at least one of the cavities penetrates the first doped layer and the first surface, and extends into the interior of the substrate.

[0021] In some embodiments, the cavity has a sidewall, and the angle α between the extension line of the sidewall and the surface where the stacked segment is located is 3°≤α≤90°.

[0022] In some embodiments, the depth of the cavity is 100nm~300nm.

[0023] In some embodiments, the width of the cavity on the side near the stacked segment is 0.1 μm to 3 μm.

[0024] In some embodiments, the first surface includes a plurality of alternating first regions and second regions, wherein a groove is formed in the second region; The first doped layer includes a substrate portion and an epitaxial portion. The substrate portion is disposed in the first region, and the projection of the epitaxial portion on the first surface falls at a predetermined position of the groove. The second doped layer includes a main body segment and a leakage channel segment connected to each other. The main body segment at least covers the bottom of the groove. At a predetermined position in the groove, the leakage channel segment wraps around the surface of the epitaxial portion facing the groove and is electrically connected to the epitaxial portion.

[0025] In some embodiments, an insulating dielectric layer is further included, the insulating dielectric layer including an overlapping section and a capping section, the overlapping section being disposed between the first doped layer and the stacked section, and in the thickness direction of the substrate, the projection of the capping section on the first surface falls outside the projection range of the first doped layer on the first surface and falls within the range of the groove. The second doped layer includes a connecting segment that extends from the side of the cap brim segment away from the first surface to the side of the cap brim segment facing the first surface, and the two ends of the connecting segment are respectively connected to the stacked segment and the leakage channel segment.

[0026] In some embodiments, a second interface passivation layer is also included. The second interface passivation layer is at least partially disposed between the leakage current channel segment and the epitaxial portion; and / or, The second interface passivation layer is at least partially disposed between the main body segment and the first surface.

[0027] Secondly, the present invention also provides a battery assembly including the aforementioned back contact battery.

[0028] Furthermore, the present invention also provides a photovoltaic system including the aforementioned battery module.

[0029] The beneficial effects of this invention are as follows: In this embodiment of the invention, a cavity is provided in the stacked region between the first doped layer and the second doped layer, and the cavity is located between the stacked segment and the first surface, with the bottom end of the cavity extending at least into the interior of the first doped layer.

[0030] On the one hand, during use, after light penetrates the substrate, some of the light can enter the hollow cavity. The inner wall of the cavity can reflect the light from the substrate in multiple directions, redirecting the light back to the substrate side, thereby increasing the number of scattering and reflections of light inside the battery. This effect helps to improve the battery's absorption rate of different wavelengths of light, increase back reflection, enhance the absorption of local photogenerated carriers, thereby increasing the photogenerated current density and effectively improving the battery's conversion efficiency.

[0031] On the other hand, since the bottom of the cavity extends at least into the interior of the first doped layer, the structure can release local stress generated under conditions such as heating, avoiding problems such as fragmentation and surface film peeling that are easily caused by the difficulty in releasing stress, thereby effectively improving the long-term stability and reliability of the battery. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a back contact battery (including a first type of cavity and a fourth type of cavity) according to an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the structure of a back contact battery (including a second type of cavity and a third type of cavity) according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the structure of a back contact battery (with a first inner deposition layer inside the cavity) according to an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the cavity structure according to an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of the structure of a cavity (with a first inner deposition layer and a second inner deposition layer) according to an embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram of the structure of a cavity (with a first inner deposition layer inside the cavity) according to an embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of the structure of a cavity (with a first inner deposition layer inside the cavity) according to an embodiment of the present invention.

[0039] Figure 8 This is a cross-sectional SEM image of the stacked region of the battery according to an embodiment of the present invention.

[0040] In the picture: Base 1; First doped layer 21, substrate 211, epitaxial layer 212; Second doped layer 22, stacked segment 221, main body segment 222, leakage channel segment 223, connection segment 224; Fourth doped layer 23; Cavity 3, first type cavity 3a, second type cavity 3b, third type cavity 3c, fourth type cavity bottom end 31, side wall 32; Insulating dielectric layer 4, hole 41, overlapping section 42, cap brim section 43; First inner deposition layer 5, third interface passivation layer 51, third doped layer 52, mixed doped layer 53; Second inner sedimentary layer 6; First interface passivation layer 71, second interface passivation layer 72; Groove 8. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0042] In the description of this invention, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," "fourth," etc., may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" or "a number" means two or more, unless otherwise explicitly specified.

[0043] In the description of this invention, unless otherwise expressly specified and limited, the term "above" or "below" the second feature may include direct contact between the first and second features, or contact between the first and second features not in direct contact but through another feature between them.

[0044] On the one hand, see Figures 1 to 3 , Figure 8 As shown, the present invention provides a back contact battery, comprising: The substrate 1 includes a first surface and a second surface disposed opposite to each other; A doped layer is disposed on the first surface. The doped layer includes a plurality of alternating first doped layers 21 and second doped layers 22 with opposite polarities. At least one adjacent first doped layer 21 and second doped layer 22 have a stacked region between them. In the stacked region, the second doped layer 22 includes a stacked segment 221, which is disposed on the side of the first doped layer 21 facing away from the first surface. Cavity 3 is located in the stacked region and between the stacked segment 221 and the first surface. The end of cavity 3 away from the stacked segment 221 is the bottom end 31, which extends at least into the interior of the first doped layer 21.

[0045] Understandably, the stacked segment 221 is part of the second doped layer 22, and in the thickness direction, the orthographic projection of the stacked segment 221 coincides with a portion of the first doped layer 21 in the stacked region.

[0046] Understandably, in this embodiment of the invention, the cavity 3 extends at least into the interior of the first doped layer 21. The interior of the cavity 3 is not filled by the material layer stacked on the side of the first doped layer 21 away from the substrate 1 (i.e., the material layer prepared after the first doped layer 21), but retains a partially hollow structure.

[0047] In this embodiment of the invention, a cavity 3 is provided in the stacked region between the first doped layer 21 and the second doped layer 22, and the cavity 3 is located between the stacked segment 221 and the first surface, with the bottom end 31 of the cavity 3 extending at least into the interior of the first doped layer 21.

[0048] On the one hand, during use, after light penetrates the substrate 1, some of the light can enter the hollow cavity 3. The inner wall of the cavity 3 can reflect the light from the substrate 1 in multiple directions, redirecting the light back to the substrate 1 side, thereby increasing the number of scattering and reflections of light inside the battery. This effect helps to improve the battery's absorption rate of light of different wavelengths, increase the back reflection effect, enhance the absorption of local photogenerated carriers, thereby increasing the photogenerated current density and effectively improving the battery conversion efficiency.

[0049] On the other hand, since the bottom end 31 of the cavity 3 extends at least into the interior of the first doped layer 21, the structure can release the local stress generated under conditions such as heating, and avoid problems such as fragmentation and surface film peeling that are easily caused by the difficulty in releasing stress, thereby effectively improving the long-term stability and reliability of the battery.

[0050] Understandably, substrate 1 has a first surface and a second surface disposed opposite to each other, wherein one is the light-receiving surface (usually referred to as the front surface of substrate 1) and the other is the back surface (usually referred to as the back surface of substrate 1). In this specification, the first surface is referred to as the back surface and the second surface as the light-receiving surface. The light-receiving surface generally refers to the side that receives light. Its surface may also be provided with passivation layers, anti-reflection layers, etc., which are common in the art, but are not limited thereto. It should be noted that in some embodiments, the back surface may also absorb the light incident through the back surface, thereby generating photocurrent. In practical applications, the embodiments of the present invention do not specifically limit the material and conductivity type of substrate 1. For example, substrate 1 can be a silicon substrate, such as monocrystalline silicon, microcrystalline silicon, polycrystalline silicon, or amorphous silicon, or it can be a germanium-silicon substrate, germanium substrate, or gallium arsenide substrate, but is not limited thereto. Its conductivity type can be N-type or P-type. Preferably, substrate 1 is a silicon substrate.

[0051] Understandably, in this embodiment of the invention, the bottom end 31 of the cavity 3 extends at least into the interior of the first doped layer 21. That is, based on the extension position of the bottom end 31 of the cavity 3, the type of the cavity 3 can be: Type I cavity 3a (see Figure 1 (As shown): The bottom end 31 of the cavity 3 extends into the interior of the first doped layer 21; Type II cavity 3b (see also) Figure 2 As shown): The bottom end 31 of the cavity 3 penetrates the first doped layer 21 and extends into at least one material layer between the first doped layer 21 and the first surface of the substrate 1; Class III cavity 3c (see Figure 2 As shown): The bottom end 31 of the cavity 3 penetrates the first doped layer 21 and just penetrates the material layer between the first doped layer 21 and the first surface of the substrate 1; Type IV cavity 3D (see Figure 1As shown): After penetrating the first doped layer 21, the bottom end 31 of the cavity 3 continues to extend into the interior of the substrate 1.

[0052] In the same solar cell, any one of the above-mentioned cavity types 3 may exist, and at least two of the above-mentioned cavity types 3 may exist simultaneously.

[0053] Preferably, at least two types of cavities 3 mentioned above exist in the same battery cell. By cooperating with each other, a better light absorption rate and stress release effect can be achieved.

[0054] For example, cavity 3 can be fabricated by processes such as laser etching or wet chemical methods, but is not limited thereto.

[0055] Understandably, in terms of conductivity type, the polarity of the first doped layer 21 and the polarity of the second doped layer 22 can be the same as or opposite to the polarity of the substrate 1, as long as the polarity of the first doped layer 21 is opposite to that of the second doped layer 22. Either the first doped layer 21 and / or the second doped layer 22 is made of monocrystalline silicon, microcrystalline silicon, polycrystalline silicon, or amorphous silicon doped with a P-type dopant element (e.g., group III elements such as B, Ga, or In), and the other is made of monocrystalline silicon, microcrystalline silicon, polycrystalline silicon, or amorphous silicon doped with an N-type dopant element (e.g., group V elements such as P, As, or Sb). Preferably, the first doped layer 21 and / or the second doped layer 22 are polycrystalline silicon.

[0056] In some embodiments, the end of the cavity 3 away from the first surface is at least covered by the stacked segment 221.

[0057] That is, the interior of the cavity 3 is not filled by the material layer stacked on the side of the first doped layer 21 away from the substrate 1 (i.e., the material layer prepared after the first doped layer 21), but retains a partially hollow structure. The end of the cavity 3 away from the first surface is covered by at least the stacked segment 221. For example, the material layer covering the end of the cavity 3 away from the first surface can be any one or more of the following: insulating dielectric layer 4, fourth doped layer 23 with the same polarity as the second doped layer 22, stacked segment 221, and passivation layer disposed on the side of the second doped layer 22 away from the insulating dielectric layer 4, but is not limited to these.

[0058] Understandably, in the thickness direction of the substrate 1, the width of the cavity 3 may increase, decrease, or remain constant along the direction away from the laminate segment 221.

[0059] In some embodiments, preferably, see Figure 1 and Figure 4 As shown, in the thickness direction of the substrate 1, the width of the cavity 3 decreases in the direction away from the laminate segment 221.

[0060] This results in the cavity 3 being located near one end of the stacked section 221, with a larger surface area on its inner wall, which allows for better multi-directional reflection of light from the substrate 1, thus increasing the number of times light is scattered and reflected inside the battery.

[0061] In some embodiments, see Figure 1 and Figure 2 As shown, at least one cavity 3 has its bottom end 31 penetrating the first doped layer 21.

[0062] The bottom end 31 of the cavity 3 penetrates the first doped layer 21, which helps to improve the stress release effect in the stacked area and effectively improve the long-term stability and reliability of the battery.

[0063] In some embodiments, see Figure 1 As shown, it also includes an insulating dielectric layer 4, which is at least partially disposed between the first doped layer 21 and the stacked segment 221.

[0064] The insulating dielectric layer 4 serves as an electrical insulator, which can limit the conductive connection area between the first doped layer 21 and the second doped layer 22 in the stacked region. This ensures that the battery has anti-hot spot performance while reducing the adverse effects on battery conversion efficiency caused by excessive conductive connection area in the unshielded state, thus balancing the long-term reliability and photoelectric performance of the battery.

[0065] For example, the insulating dielectric layer 4 may be any one or more of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), etc., but is not limited thereto.

[0066] In some embodiments, see Figure 3 and Figure 4 As shown, the insulating dielectric layer 4 includes a hole 41, and in the thickness direction of the substrate 1, the orthographic projection of the hole 41 on the first surface at least partially coincides with the orthographic projection of the cavity 3 on the first surface.

[0067] Understandably, the holes 41 in the insulating dielectric layer 4 completely penetrate the insulating dielectric layer 4 along its thickness direction.

[0068] The cavity 3 can be prepared after the insulating dielectric layer 4 is prepared. Specifically, after the insulating dielectric layer 4 is prepared, holes 41 are etched by laser. During this process, the position, density, number, and size of the holes 41 can be set as needed. Then, with the help of chemical etching and other methods, a corresponding cavity 3 is formed on the side of the holes 41 close to the substrate 1. Thus, by setting holes 41 in the insulating dielectric layer 4 and the subsequent etching process, the position, density, number, and size of the cavity 3 can be controlled.

[0069] In some embodiments, see Figure 3 , Figures 5 to 7As shown, at least a portion of the inner wall of at least one cavity 3 is covered with a first inner deposition layer 5. The first inner deposition layer 5 is a stack of any one or more of the third interface passivation layer 51, the third doped layer 52 and the mixed doped layer 53. The polarity of the third doped layer 52 is the same as that of the second doped layer 22. The mixed doped layer 53 is a silicon material layer doped with N-type dopant and P-type dopant.

[0070] The size of the voids inside the cavity 3 can be adjusted by covering the inner wall with a first inner deposition layer 5.

[0071] In some embodiments, within the orthogonal projection range of the laminated segment 221 in the thickness direction of the substrate 1, a single unit area contains 1 to 64 cavities 3, with a unit area of ​​10μm × 10μm.

[0072] By controlling the distribution density of cavity 3, the photocurrent absorption of the battery can be effectively increased, optical transmission loss reduced, and the photoelectric conversion efficiency improved. The distribution density of cavity 3 should not be too high; excessively dense cavities can easily increase the surface state density of the battery, causing surface recombination and affecting the photoelectric conversion efficiency.

[0073] In some embodiments, see Figure 5 As shown, the hole 41 is filled with a fourth doped layer 23, and the polarity of the fourth doped layer 23 is the same as that of the second doped layer 22.

[0074] In some embodiments, the hole 41 has an unfilled void.

[0075] At this time, the inner wall of the hole 41 can also provide more scattering and reflection paths for light, which, together with the cavity 3, further increases the number of times light is scattered and reflected inside the battery.

[0076] In some embodiments, see Figure 6 As shown, inside the cavity 3, the end near the stacked section 221 is covered by a second inner deposition layer 6. The second inner deposition layer 6 is a stack of one or more of the fifth doped layer and the co-doped layer. The polarity of the fifth doped layer is the same as that of the second doped layer 22. The co-doped layer is a silicon material layer doped with N-type doping elements and P-type doping elements.

[0077] It is understandable that the polarity of the third doped layer 52, the fourth doped layer 23, and the fifth doped layer is the same as that of the second doped layer 22. Their materials can be the same as or different from those of the second doped layer 22. It is only necessary to ensure that the polarity of the third doped layer 52, the fourth doped layer 23, and the fifth doped layer is the same as that of the second doped layer 22. Preferably, the materials of the third doped layer 52, the fourth doped layer 23, and the fifth doped layer are the same as those of the second doped layer 22. In this case, the third doped layer 52 and the second doped layer 22 can be prepared simultaneously in the same step during the preparation process, which simplifies the process flow.

[0078] In some embodiments, the material of either the mixed-doped layer 53 and / or the co-doped layer can be monocrystalline silicon, microcrystalline silicon, polycrystalline silicon, or amorphous silicon co-doped with a P-type dopant (e.g., group III elements such as B, Ga, or In) and an N-type dopant (e.g., group V elements such as P, As, or Sb). Preferably, the mixed-doped layer 53 and / or the co-doped layer is polycrystalline silicon.

[0079] Understandably, the cavity 3 near the stacked section 221 is covered with a second inner deposition layer 6, which is arranged perpendicular to the thickness direction of the substrate 1 to seal the cavity 3 near the stacked section 221.

[0080] The size of the voids inside the cavity 3 can be adjusted by covering the inner wall with a second inner deposition layer 6.

[0081] In some embodiments, see Figure 1 As shown, a first interface passivation layer 71 is provided between the first doped layer 21 and the first surface.

[0082] By setting the first interface passivation layer 71, the passivation effect and carrier transport effect can be improved, which is beneficial to improving the conversion efficiency of the battery.

[0083] For example, the first interface passivation layer 71 may be an intrinsic amorphous silicon layer or a tunneling oxide layer (such as silicon oxide, titanium oxide, etc.), but is not limited thereto.

[0084] Understandably, the material of the first interface passivation layer 71 can be selected based on the material of the first doped layer 21. For example, when the material of the first doped layer 21 is polycrystalline silicon, the first interface passivation layer 71 can be a tunneling oxide layer; when the material of the first doped layer 21 is intrinsic amorphous silicon, the first interface passivation layer 71 can be an intrinsic amorphous silicon layer.

[0085] In some embodiments, see Figure 1 and Figure 2 As shown, at least one cavity 3 has its bottom end 31 penetrating through the first doped layer 21 and extending at least into the interior of the first interface passivation layer 71.

[0086] In some embodiments, see Figure 1 and Figure 2 As shown, the bottom end 31 of at least one cavity 3 penetrates the first doped layer 21 and extends at least to the first surface.

[0087] In some embodiments, see Figure 1 and Figure 2 As shown, the bottom end 31 of at least one cavity 3 penetrates the first doped layer 21 and the first surface, and extends into the interior of the substrate 1.

[0088] At this time, cavity 3 is the fourth type of cavity 3d mentioned above. The bottom end 31 of cavity 3 extends into the interior of substrate 1, which can better release the local stress generated under heating and other conditions, and further improve the long-term stability and reliability of the battery.

[0089] An appropriate number of the aforementioned fourth type of cavity 3d can be set in the stacked area to increase the stress relief effect.

[0090] In some embodiments, see Figure 1 and Figure 4 As shown, the cavity 3 is provided with a sidewall 32, and the angle α between the extension line of the sidewall 32 and the surface where the stacked section 221 is located is 3°≤α≤90°.

[0091] For example, the included angle α can be 3°, 5°, 8°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, or 90°, but is not limited thereto.

[0092] In some embodiments, see Figure 4 As shown, the depth H of cavity 3 is 100nm~300nm.

[0093] For example, the depth of cavity 3 is 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, or 300nm, but is not limited thereto.

[0094] If the depth of cavity 3 is too small, it is difficult for cavity 3 to achieve a good stress release effect and light utilization improvement effect. If the depth of cavity 3 is too large, it is easy to increase the surface state density of the battery, causing surface recombination of the battery and affecting the photoelectric conversion efficiency.

[0095] In some embodiments, see Figure 4 As shown, the width W of the cavity 3 on the side near the stacked section 221 is 0.1μm~3μm.

[0096] For example, the width of the cavity 3 on the side near the stacked segment 221 is 0.1μm, 0.2μm, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm or 3μm, but is not limited thereto.

[0097] If the width of the cavity 3 on the side closest to the stacked section 221 is too small, the cavity 3 will not be able to achieve a good stress relief effect and improve light utilization. If the width of the cavity 3 on the side closest to the stacked section 221 is too large, it will easily increase the surface state density of the battery, causing surface recombination and affecting the photoelectric conversion efficiency.

[0098] In some embodiments, see Figure 3 As shown, the first surface includes several alternating first regions and second regions, and a groove 8 is formed in the second region; The first doped layer 21 includes a substrate 211 and an epitaxial layer 212. The substrate 211 is disposed in the first region, and the projection of the epitaxial layer 212 on the first surface falls at a preset position in the groove 8. The second doped layer 22 includes a main body segment 222 and a leakage channel segment 223 connected to each other. The main body segment 222 at least covers the bottom of the groove 8. At a predetermined position in the groove 8, the leakage channel segment 223 wraps around the surface of the epitaxial portion 212 facing the groove 8 and is electrically connected to the epitaxial portion 212.

[0099] It is understandable that the conductive connection between the epitaxial portion 212 of the first doped layer 21 and the leakage channel segment 223 of the second doped layer 22 means that there is no insulation between the two. The electrical connection can be achieved through direct contact or indirect contact through other conductive material layers.

[0100] The preset position of the groove 8 can be the entire groove 8 or a part of the groove 8. Preferably, the preset position of the groove 8 is a part of the groove 8. The same groove 8 can contain one or more preset positions arranged at intervals.

[0101] In this embodiment, by setting the groove 8, and at a preset position of the groove 8, the leakage channel segment 223 is wrapped around the surface of the epitaxial portion 212 facing the groove 8 and electrically connected to the epitaxial portion 212, thereby reducing the negative impact of edge recombination caused by the recombination contact between the first doped layer 21 and the second doped layer 22. At the same time, the surface of the epitaxial portion 212 facing the groove 8 has a side surface and a bottom surface, and the leakage channel segment 223 is wrapped around the surface of the epitaxial portion 212 facing the groove 8, thereby ensuring that the two have a sufficiently large recombination contact area. This recombination contact structure enables the battery to have both good anti-hot spot performance and high photoelectric conversion efficiency.

[0102] In areas outside the preset position of the groove 8, the first doped layer 21 and the second doped layer 22 can be physically isolated directly by the groove 8, or by means of setting an insulating material between them, etc., without any specific restrictions.

[0103] In some embodiments, see Figure 1 and Figure 3 As shown, it also includes an insulating dielectric layer 4, which includes an overlapping section 42 and a capping section 43. The overlapping section 42 is disposed between the first doped layer 21 and the stacked section 221. In the thickness direction of the substrate 1, the projection of the capping section 43 on the first surface falls outside the projection range of the first doped layer 21 on the first surface and falls within the range of the groove 8. The second doped layer 22 includes a connecting segment 224, which is wound around from the side of the cap edge segment 43 away from the first surface to the side of the cap edge segment 43 facing the first surface, and the two ends of the connecting segment 224 are respectively connected to the stacked segment 221 and the leakage channel segment 223.

[0104] Understandably, the epitaxial portion 212 of the first doped layer 21 and the cap edge portion 43 of the insulating dielectric layer 4 together form a stepped structure. The composite contact position of the first doped layer 21 and the second doped layer 22 is located within the orthogonal projection range of the overlapping portion 42 and the cap edge portion 43 in the thickness direction of the substrate 1. When depositing the second doped layer 22, due to the shielding effect of the insulating dielectric layer 4, the thickness of the second doped layer 22 at the composite contact position is smaller than the thickness of the second doped layer 22 at other positions. This can avoid excessive parasitic conductivity when there is no shielding, so that the battery can have both good hot spot resistance and high photoelectric conversion efficiency.

[0105] In some embodiments, see Figure 1 and Figure 3 As shown, it also includes a second interface passivation layer 72. The second interface passivation layer 72 is at least partially disposed between the leakage current channel segment 223 and the extension portion 212; and / or, The second interface passivation layer 72 is at least partially disposed between the main body segment 222 and the first surface.

[0106] By setting a second interface passivation layer 72, the passivation effect and carrier transport effect can be improved, which is beneficial to improving the conversion efficiency of the battery.

[0107] For example, the second interface passivation layer 72 may be an intrinsic amorphous silicon layer or a tunneling oxide layer (such as silicon oxide, titanium oxide, etc.), but is not limited to these.

[0108] Understandably, the material of the second interface passivation layer 72 can be selected based on the material of the second doped layer 22. For example, when the material of the second doped layer 22 is polycrystalline silicon, the second interface passivation layer 72 can be a tunneling oxide layer; when the material of the second doped layer 22 is intrinsic amorphous silicon, the second interface passivation layer 72 can be an intrinsic amorphous silicon layer.

[0109] Secondly, the present invention also provides a battery assembly including the aforementioned back contact battery.

[0110] Furthermore, the present invention also provides a photovoltaic system including the aforementioned battery module.

[0111] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0112] The present invention will be further described below with reference to embodiments and experiments: Example 1 This embodiment discloses a back contact battery, comprising: The substrate includes a first surface and a second surface disposed opposite to each other; A doped layer is disposed on a first surface. The doped layer includes a plurality of alternating first doped layers and second doped layers with opposite polarities, and at least one adjacent first doped layer and second doped layer have a stacked region between them. In the stacked region, the second doped layer includes a stacked segment, which is disposed on the side of the first doped layer facing away from the first surface. A cavity is provided in the stacked region and between the stacked section and the first surface. The end of the cavity away from the stacked section is the bottom end, which extends at least into the interior of the first doped layer.

[0113] Within the orthogonal projection range of the laminated segment in the thickness direction of the substrate, with a unit area of ​​10μm×10μm, a single unit area contains 30±5 cavities.

[0114] Comparative Example 1 The difference between this comparative example and Example 1 is that no cavity is provided in the stacked area.

[0115] The solar cells prepared in Example 1 and Comparative Example 1 were used to test their respective breakage rates and photoelectric properties. The test results are as follows:

[0116] Experimental results show that the back-contact battery of the present invention can effectively increase the photocurrent density, thereby effectively improving the battery conversion efficiency. At the same time, it avoids problems such as fragmentation and surface film peeling that are easily caused by the difficulty in releasing stress in the anti-hot spot structure of the prior art, thus effectively improving the long-term stability and reliability of the battery.

[0117] In the description of this specification, references to terms such as "some embodiments," "exemplary," "example," or "for example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A back-contact battery, characterized in that, include: The substrate includes a first surface and a second surface disposed opposite to each other; A doped layer is disposed on the first surface. The doped layer includes a plurality of alternating first doped layers and second doped layers with opposite polarities, and at least one adjacent first doped layer and second doped layer have a stacked region between them. In the stacked region, the second doped layer includes a stacked segment, which is disposed on the side of the first doped layer facing away from the first surface. A cavity is provided in the stacked region and between the stacked segment and the first surface. The end of the cavity away from the stacked segment is the bottom end, which extends at least into the interior of the first doped layer. The inner wall of the cavity can reflect light from the substrate and redirect the light to the substrate side.

2. A back contact battery according to claim 1, characterized in that, The end of the cavity away from the first surface is at least covered by the stacked segment.

3. A back contact battery according to claim 1, characterized in that, In the thickness direction of the substrate, the width of the cavity decreases in the direction away from the laminate segment.

4. A back contact battery according to claim 1, characterized in that, At least one of the cavities extends through the first doped layer at its bottom end.

5. A back contact battery according to claim 1, characterized in that, It also includes an insulating dielectric layer, which is at least partially disposed between the first doped layer and the stacked segment.

6. A back contact battery according to claim 5, characterized in that, The insulating dielectric layer includes pores, and in the thickness direction of the substrate, the orthographic projection of the pores onto the first surface at least partially coincides with the orthographic projection of the cavity onto the first surface.

7. A back contact battery according to claim 6, characterized in that, At least one of the cavities has at least a portion of its inner wall covered with a first inner deposition layer, the first inner deposition layer being a stack of any one or more of a third interface passivation layer, a third doping layer, and a mixed doping layer, the polarity of the third doping layer being the same as that of the second doping layer, and the mixed doping layer being a silicon material layer doped with N-type doping elements and P-type doping elements.

8. A back contact battery according to claim 6, characterized in that, The pores are filled with a fourth doped layer, the polarity of which is the same as that of the second doped layer; or... The hole contains unfilled voids.

9. A back contact battery according to claim 6, characterized in that, Inside at least one of the cavities, a second inner deposition layer is covered at one end near the stacked segment. The second inner deposition layer is a stack of one or more of a fifth doped layer and a co-doped layer. The polarity of the fifth doped layer is the same as that of the second doped layer. The co-doped layer is a silicon material layer doped with N-type dopant and P-type dopant.

10. A back contact battery according to claim 5, characterized in that, Within the orthogonal projection range of the laminated segment in the thickness direction of the substrate, with a unit area of ​​10μm×10μm, a single unit area contains 1 to 64 cavities.

11. A back contact battery according to claim 1, characterized in that, A first interface passivation layer is provided between the first doped layer and the first surface.

12. A back contact battery according to claim 11, characterized in that, At least one of the cavities has its bottom end penetrating the first doped layer and extending at least into the interior of the first interface passivation layer.

13. A back contact battery according to claim 1, characterized in that, At least one of the cavities has its bottom end penetrating the first doped layer and extending at least to the first surface.

14. A back contact battery according to claim 13, characterized in that, At least one of the cavities has its bottom end penetrating the first doped layer and the first surface, and extending into the interior of the substrate.

15. A back contact battery according to claim 1, characterized in that, The cavity has a sidewall, and the angle α between the extension line of the sidewall and the surface where the stacked section is located is 3°≤α≤90°.

16. A back contact battery according to claim 1, characterized in that, The depth of the cavity is 100nm~300nm.

17. A back contact battery according to claim 1, characterized in that, The width of the cavity on the side closest to the stacked section is 0.1 μm to 3 μm.

18. A back contact battery according to claim 1, characterized in that, The first surface includes a plurality of alternating first regions and second regions, wherein a groove is formed in the second region; The first doped layer includes a substrate portion and an epitaxial portion. The substrate portion is disposed in the first region, and the projection of the epitaxial portion on the first surface falls at a predetermined position of the groove. The second doped layer includes a main body segment and a leakage channel segment connected to each other. The main body segment at least covers the bottom of the groove. At a predetermined position in the groove, the leakage channel segment wraps around the surface of the epitaxial portion facing the groove and is electrically connected to the epitaxial portion.

19. A back contact battery according to claim 18, characterized in that, It also includes an insulating dielectric layer, which includes an overlapping section and a capping section. The overlapping section is disposed between the first doped layer and the stacked section. In the thickness direction of the substrate, the projection of the capping section on the first surface falls outside the projection range of the first doped layer on the first surface and falls within the range of the groove. The second doped layer includes a connecting segment that extends from the side of the cap brim segment away from the first surface to the side of the cap brim segment facing the first surface, and the two ends of the connecting segment are respectively connected to the stacked segment and the leakage channel segment.

20. A back contact battery according to claim 18, characterized in that, It also includes a second interface passivation layer. The second interface passivation layer is at least partially disposed between the leakage current channel segment and the epitaxial portion; and / or, The second interface passivation layer is at least partially disposed between the main body segment and the first surface.

21. A battery assembly, characterized in that, Includes the back contact battery according to any one of claims 1 to 20.

22. A photovoltaic system, characterized in that, Includes the battery assembly according to claim 21.

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