A low noise biasing circuit for a voltage controlled oscillator and applications thereof

Abstract

The application relates to the technical field of radio frequency integrated circuits, and discloses a low-noise bias circuit for a voltage-controlled oscillator and application thereof; the circuit is coupled through an inductive intermediate tap between a bias circuit and a core circuit of the voltage-controlled oscillator, realizes feedback and self-elimination of low-frequency noise, significantly improves phase noise performance, integrates a peak detection circuit and a digital logic control circuit, monitors an oscillation amplitude in real time and dynamically adjusts a bias current, realizes adaptive calibration of the amplitude, and ensures that the voltage-controlled oscillator works in an optimal state under different process corners and temperatures. The application has low noise, low power consumption, high stability and strong process adaptability, and is suitable for high-integration radio frequency chips such as 5G, the Internet of Things and Bluetooth.

Description

Technical Field

[0001] This invention relates to radio frequency integrated circuits, and in particular to a low-noise bias circuit for voltage-controlled oscillators and its applications. Background Technology

[0002] A voltage-controlled oscillator (VCO) is one of the core components of a radio frequency (RF) communication system, widely used in various RF transceiver chips such as wireless communication, radar, satellite navigation, IoT devices, Bluetooth, Wi-Fi, 5G terminals, and base stations. In modern wireless communication systems, the VCO is responsible for generating high-frequency carrier signals, the frequency of which varies with the input control voltage. It is a key module for realizing functions such as frequency synthesis, modulation / demodulation, and channel selection.

[0003] In practical applications, the performance of the VCO directly affects the quality of the entire communication system. Especially in high-frequency, high-speed, and highly integrated RF chips, the phase noise of the VCO is a crucial indicator of its signal purity. Excessive phase noise can lead to a decrease in the signal-to-noise ratio of the communication link, an increase in the bit error rate, and exacerbated interference from adjacent channels, potentially even causing communication interruptions or data loss. Therefore, improving the phase noise performance of the VCO is one of the key technical challenges in RF chip design.

[0004] Traditional VCOs typically employ current-biased or voltage-biased structures, such as Figure 7 and Figure 8 As shown. These traditional structures have the following technical problems in practical applications:

[0005] Technical Issue 1: Low-frequency noise introduced by the bias circuit: Traditional LDO or current mirror bias circuits themselves output noise, which is coupled to the VCO core circuit through the power line or bias node. In particular, low-frequency noise components are capacitance modulated through the variable capacitor or the parasitic diode of the MOSFET, which is equivalent to frequency modulation (FM) of the oscillation signal, thus severely degrading the phase noise.

[0006] Technical issue two: direct injection of noise from cross-coupled transistors: During the start-up and oscillation process, the cross-coupled NMOS / PMOS transistors in the VCO core will generate thermal noise and flicker noise (1 / f noise). This noise will be directly injected into the LC resonant tank and further converted into phase noise through the modulation effect of variable capacitance or parasitic capacitance.

[0007] The third technical problem is the lack of amplitude stability control: Traditional VCOs typically use a fixed bias current or voltage, which cannot adjust the oscillation amplitude in real time according to process deviations, temperature changes, power supply fluctuations, etc. If the bias current is set too high, although it can ensure oscillation and stable oscillation, it will lead to excessive power consumption; if it is set too low, it may lead to insufficient oscillation amplitude or even stop oscillation, affecting the reliability and consistency of the system.

[0008] Technical Issue 4: Performance fluctuations caused by process corner and temperature variations: During mass production, due to the inherent deviations of semiconductor processes and changes in operating temperature, the oscillation frequency and amplitude of the VCO will fluctuate significantly. Traditional fixed bias methods are difficult to maintain optimal performance across all process corners and temperature ranges, resulting in a decrease in product yield and consistency.

[0009] In summary, those skilled in the art urgently need a low-noise bias circuit and application scheme that integrates noise feedback and digital amplitude calibration. Summary of the Invention

[0010] The core technical problem to be solved by this invention is: how to effectively suppress the deterioration of VCO phase noise by low-frequency noise introduced by bias circuit and cross-coupled transistors, and achieve adaptive calibration of oscillation amplitude at different process angles and temperatures, so as to ensure low phase noise while taking into account power consumption, stability and mass production consistency.

[0011] To address the aforementioned core technical challenges, this invention integrates the bias circuit and the VCO core circuit into a single design. It extracts low-frequency noise components from the oscillation signal via the center tap of an LC resonant inductor and feeds them back to the noise cancellation path in the bias circuit, achieving self-cancellation of noise. Simultaneously, the system integrates a peak detection circuit and a digital logic control circuit to monitor the oscillation amplitude in real time and dynamically adjust the bias current through digital closed-loop control, stabilizing the oscillation amplitude within a preset target range. This solution not only significantly reduces phase noise (improving by approximately 4dB) but also ensures that the VCO operates optimally under various process angles and temperatures through an adaptive calibration mechanism, achieving a balance between performance, power consumption, and reliability.

[0012] The technical solution of the present invention to achieve the above objectives is a low-noise bias circuit for a voltage-controlled oscillator, comprising:

[0013] Bias circuit, used to provide bias voltage for the core circuit of voltage-controlled oscillator;

[0014] The bias circuit is connected to the core circuit of the voltage-controlled oscillator via the center tap of an inductor, which is used to feed back low-frequency noise in the core circuit of the voltage-controlled oscillator to the bias circuit to reduce phase noise.

[0015] The bias circuit includes:

[0016] Digitally controlled current mirror ( );

[0017] Multiple NMOS transistors ( , , , , ) and capacitor ( , The cascaded mirror image and noise cancellation path is formed by the following:

[0018] in, The gate is connected to the center tap of the inductor.

[0019] Also includes:

[0020] A peak detection circuit is used to detect the oscillation amplitude of the core circuit of the voltage-controlled oscillator;

[0021] A digital logic control circuit is used to adjust the current value of the digital control current mirror according to the output signal of the peak detection circuit.

[0022] The peak detection circuit includes:

[0023] Input coupling capacitor ( , );

[0024] A threshold-adjustable comparison path, via a resistor string ( to ) and switch ( , ) generates an optional threshold voltage ( );

[0025] Mirror pair tube ( to , to The signal amplification and filtering structure is composed of .

[0026] The digital logic control circuit performs the following steps:

[0027] Initialize the current control word to its minimum value;

[0028] Detect the output level of the peak detection circuit;

[0029] If the output is low, the current control word is gradually increased until the output is high or reaches the maximum value.

[0030] A voltage-controlled oscillator, comprising:

[0031] The low-noise bias circuit;

[0032] The core circuit of the voltage-controlled oscillator includes a cross-coupled PMOS pair ( , ), NMOS pair ( , ),inductance( ) and variable capacitor ( );

[0033] Among them, the inductor ( The center tap of the circuit is connected to the bias circuit.

[0034] The output of the voltage-controlled oscillator core circuit is connected to the input of the peak detection circuit to form a closed-loop amplitude control.

[0035] A noise cancellation method for a voltage-controlled oscillator includes the following steps:

[0036] The low-frequency noise voltage in the core circuit of the voltage-controlled oscillator is extracted by the center tap of the LC resonant inductor.

[0037] The noise voltage is fed back to the gate of the feedback MOS transistor in the low-noise bias circuit to generate a canceling current;

[0038] The cancellation current reduces the noise current flowing into the core circuit of the voltage-controlled oscillator.

[0039] An amplitude calibration method for a voltage-controlled oscillator includes the following steps:

[0040] Detect the peak voltage of the oscillation signal;

[0041] The peak voltage is compared with the adjustable threshold voltage;

[0042] Based on the comparison results and by dynamically adjusting the bias current using the low-noise bias circuit, the oscillation amplitude is brought close to the target threshold.

[0043] A radio frequency communication chip, which integrates the voltage-controlled oscillator described above.

[0044] Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0045] First, this application adopts an inductor tap noise feedback structure, directly connecting the center tap of the LC resonant inductor to the feedback MOS transistor in the bias circuit. The gate is used to extract the low-frequency noise voltage contained in the core circuit of the VCO and generate a cancellation current in the bias circuit through the feedback path to achieve noise self-cancellation. This structure has never appeared in traditional VCO design.

[0046] Second, this application utilizes an integrated circuit for noise cancellation and bias generation. The bias circuit is not a separate module, but shares some components with the VCO core (such as...). The cascaded mirror structure forms a composite circuit that combines bias generation, noise sampling and cancellation functions. This integrated design simplifies the circuit structure while reducing noise.

[0047] Third, this application employs a digital closed-loop amplitude calibration mechanism, which outputs the oscillation amplitude status signal in real time through a peak detection circuit. The digital logic circuit dynamically adjusts the current mirror based on this signal. ) control word ( This method achieves adaptive calibration of oscillation amplitude by organically combining analog oscillation control with digital logic control, thereby improving the intelligence and stability of the system.

[0048] Fourth, this application constructs a peak detection circuit with a programmable threshold, wherein the peak detection circuit is configured with a resistor series and a switch ( , The adjustable threshold voltage () constitutes This allows for flexible setting of the target oscillation amplitude according to actual application requirements, enhancing the applicability and configurability of the circuit.

[0049] Fifth, this application employs a resistance tuning mechanism in the alternative solution, which involves inserting an adjustable resistor in the feedback path. The bias voltage is adjusted to achieve amplitude calibration, which provides another implementation path for noise feedback structures and expands the implementation flexibility of the present invention.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. This invention can significantly reduce phase noise. Through the inductor tap noise feedback mechanism, it effectively suppresses low-frequency noise introduced by the bias circuit and cross-coupled transistors. The measured phase noise performance is improved by about 4dB compared with the traditional structure, thus improving the signal quality and communication reliability of the RF system.

[0052] 2. This invention achieves adaptive amplitude stabilization and integrates a digital amplitude calibration closed loop, enabling the VCO to automatically adjust to the optimal oscillation amplitude under different process angles, temperatures, and power supply voltage changes. This avoids the risk of oscillation stoppage due to insufficient amplitude and prevents power consumption waste due to overdrive.

[0053] 3. This invention improves the consistency and yield of mass production. By compensating for process deviations through a calibration mechanism, it significantly reduces VCO performance fluctuations caused by process dispersion, thereby improving the consistency and yield of chip mass production and reducing production costs.

[0054] 4. This invention can achieve both low power consumption and high performance. The calibrated VCO operates at a bias point that precisely meets the oscillation conditions, avoiding the problem of excessive biasing in traditional designs to maintain stability. It achieves power consumption optimization while ensuring low phase noise.

[0055] 5. The circuit designed in this invention has the characteristics of compact structure and easy integration. The noise feedback and bias circuit are integrated into one design, eliminating the need for external complex filtering or compensation networks. It is suitable for high-frequency, highly integrated CMOS RF chip design. Attached Figure Description

[0056] Figure 1 This is a circuit diagram of the voltage-controlled oscillator described in this invention;

[0057] Figure 2 This is a flowchart of the noise cancellation method for the voltage-controlled oscillator described in this invention;

[0058] Figure 3 This is a flowchart of the amplitude calibration method for the voltage-controlled oscillator described in this invention;

[0059] Figure 4 This is a circuit diagram of the peak detection circuit described in this invention;

[0060] Figure 5 This is a flowchart of the digital logic control circuit described in this invention;

[0061] Figure 6 This is a circuit diagram of the amplitude calibration method for a voltage-controlled oscillator based on resistance calibration as described in this invention;

[0062] Figure 7 This is a circuit diagram of the bias circuit of the conventional current-type voltage-controlled oscillator described in this invention;

[0063] Figure 8 This is a circuit diagram of the bias circuit of the conventional voltage-controlled oscillator described in this invention. Detailed Implementation

[0064] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings;

[0065] Example 1:

[0066] A low-noise bias circuit for voltage-controlled oscillators, such as Figure 1 The section marked in red in the middle includes:

[0067] Bias circuit, used to provide bias voltage for the core circuit of voltage-controlled oscillator;

[0068] The bias circuit is connected to the core circuit of the voltage-controlled oscillator via the center tap of an inductor, which is used to feed back low-frequency noise in the core circuit of the voltage-controlled oscillator to the bias circuit to reduce phase noise.

[0069] The bias circuit includes:

[0070] Digitally controlled current mirror ( );

[0071] Multiple NMOS transistors ( , , , , ) and capacitor ( , The cascaded mirror image and noise cancellation path is formed by the following:

[0072] in, The gate is connected to the center tap of the inductor.

[0073] Also includes:

[0074] A peak detection circuit is used to detect the oscillation amplitude of the core circuit of the voltage-controlled oscillator;

[0075] A digital logic control circuit is used to adjust the current value of the digital control current mirror according to the output signal of the peak detection circuit.

[0076] The peak detection circuit includes:

[0077] Input coupling capacitor ( , );

[0078] A threshold-adjustable comparison path, via a resistor string ( to ) and switch ( , ) generates an optional threshold voltage ( );

[0079] Mirror pair tube ( to , to The signal amplification and filtering structure is composed of .

[0080] Example 2:

[0081] A voltage-controlled oscillator, such as Figure 1As shown in the overall diagram, it cleverly combines the bias circuit and the voltage-controlled oscillator (VCO). The DC voltage of the VCO and the low-frequency noise superimposed from the LC oscillation slots are fed back to the bias circuit through the center tap of the inductor, thereby reducing the VCO noise. The VCO amplitude peak detection circuit detects the oscillation amplitude of the VCO. By setting an amplitude threshold, it outputs an indication signal indicating whether the VCO amplitude is greater than or less than the threshold to the digital logic control circuit. Based on this indication signal, the digital logic control circuit outputs a current control signal to increase or decrease the current in the bias circuit. The magnitude of the current in the current mirror is adjusted to bring the oscillation amplitude of the voltage-controlled oscillator (VCO) close to the target threshold amplitude, thus achieving an optimal balance between the VCO's performance and power consumption.

[0082] The voltage-controlled oscillator consists of a bias circuit, a voltage-controlled oscillator core circuit, a peak detection circuit, and a digital logic control circuit.

[0083] Bias circuit has Digitally controlled current mirror, NMOS transistor , , , , ,capacitance , Composition; of which and The gate, Drain, capacitor The positive electrode, The current outputs are connected together. The source pole and The gate and drain are connected together. The source pole and The gate and drain are connected together. The source pole, negative electrode and The source electrode is grounded. Source capacitor Positive output voltage Connect the power supply to the core circuit of the voltage-controlled oscillator. The negative terminal is grounded.

[0084] The core circuit of a voltage-controlled oscillator includes: a PMOS transistor. , NMOS transistor , ,inductance Variable capacitor . and The source pole is connected together . gate connection Drain, Inductance One end can be capacitive One end, The drain electrode, The gate of the circuit. Its output is a signal. And output to the input terminal of the peak detection circuit. gate connection Drain, Inductance On the other end, a capacitor On the other end, The drain electrode, The gate of the circuit. Its output is a signal. The output is then fed to the other input of the peak detection circuit. Connect the input to the digital logic control circuit, and connect the output of the digital logic control circuit to... The mirror current control terminal. Inductor The center tap is connected to the bias circuit. The gate of the transistor.

[0085] Peak detection circuit such as Figure 4 As shown. Input oscillator signal. , Connect capacitors respectively , The positive end. The negative terminal is connected to the NMOS transistor. gate and resistor One end. The negative terminal is connected to the NMOS transistor. gate and resistor One end. and The other end received together . It is a resistor string , , , The partial pressure. , The drain of the PMOS transistor is connected together with the drain of the PMOS transistor. The gate and drain, and The gate, and A mirror image relationship is formed. and Source Street Power Supply . The drain of the PMOS transistor is connected to the PMOS transistor. The gate of the NMOS transistor drain and capacitor One end of the capacitor is a capacitor, and the other end of the capacitor is grounded for filtering. , , The source poles are connected together, and the streets The drain of the NMSOS transistor. , , A mirror image relationship is formed. , , gate and The drains are connected together and connected to the bias current. superior. , , The source electrode is grounded. Drain and The drains are connected together, street inverter The input terminal is connected to the output terminal. Resistance One end is grounded, and the other end is connected to Simultaneously output Voltage, The other end connects , The other end connects , The other end connects . Two switches were connected to each end. , . and The other end is connected together for output street The gate voltage serves as the threshold voltage for the peak detection circuit. and The voltage across the resistor string is selected, thereby adjusting the oscillation amplitude of the voltage-controlled oscillator. This design employs an additional threshold selection option, but the number of resistors and switches can be increased to expand the threshold options.

[0086] Amplitude calibration methods such as Figure 5 As shown; after the oscillator starts working, amplitude calibration is performed first. Configure it to "0" to make The current is minimized. After a certain waiting time, the oscillator stabilizes; in this design, this is 1µs. The peak detection circuit checks the output level. .

[0087] When the value is "0", it indicates that the oscillation amplitude of the oscillator is less than the target amplitude, making... Increment the value by one, wait 1µs, and then recheck. This cycle repeats until... =1 or Once the value reaches 15, exit the loop and end the calibration. A value of "1" indicates that the oscillation amplitude of the oscillator is greater than the target amplitude.

[0088] Example 3:

[0089] A noise cancellation method for a voltage-controlled oscillator, such as Figure 2 As shown, this method is applied to Example 2 (i.e. Figure 1 In the circuit system shown, the method is implemented as follows:

[0090] Extraction of low-frequency noise voltage: Cross-coupled transistors in the core circuit of a voltage-controlled oscillator (VCO) , During operation, it will generate inherent thermal noise and flicker noise. Noise). This noise modulates the LC resonant tank (due to inductance). With variable capacitor The resonant characteristics of the structure;

[0091] This method utilizes inductance. The middle tap is used as a noise sampling point, and this tap node (labeled as...) The potential of the LC tank not only contains the DC operating point information of the LC tank circuit, but also superimposed the low-frequency noise voltage fluctuation component injected by the core circuit and reflected on the LC tank circuit.

[0092] Noise voltage feedback and cancellation current generation: Using the inductor center tap Directly connected to a specially designed feedback MOSFET in the bias circuit The gate;

[0093] when When the voltage at a node fluctuates due to noise disturbances, this fluctuation will directly affect the... The gate; and and capacitors Together they form a cascaded mirror image and noise cancellation path;

[0094] Specifically, Variations in the gate noise voltage modulate its drain current. This current variation is transmitted through the gate's noise voltage. The current mirror structure is used for transmission and mirroring, ultimately at the output node. A compensation current is generated on the bias voltage that powers the VCO core circuit, which is out of phase with the original injected noise current.

[0095] Self-cancellation of noise: The above process forms a local negative feedback loop. Noise is generated from the VCO core and coupled to the power line. The noise current on, and through Feedback path in The counteracting currents generated by the nodes interact.

[0096] Through precise design Size, The capacitance value and the ratio of the current mirror can make the canceling current close to the noise current in amplitude but opposite in phase, thus achieving... Effective cancellation of noise current is achieved at the node.

[0097] because This is the power supply for the VCO core circuit. After the noise on it is significantly suppressed, the impact on the variable capacitor through the power supply path is directly reduced. This reduces noise sources that are modulated by transistor parasitic capacitance, thereby fundamentally reducing the degradation of phase noise.

[0098] The core of this method lies in using a clever feedback path (inductor tap → ...) to isolate noise energy, which is traditionally considered harmful and needs to be isolated. The noise is converted into a useful signal that can cancel itself out, thus achieving "self-cancellation" of noise.

[0099] Example 4:

[0100] An amplitude calibration method for a voltage-controlled oscillator, such as Figure 3 As shown, this method combines Figure 1 The voltage-controlled oscillator shown Figure 4 The peak detection circuit shown and Figure 5 The digital control logic is shown; the specific implementation process of the method is as follows:

[0101] Initialization phase: When the chip powers on or the VCO starts, the digital logic control circuit first sets up the 4-bit digital control word that controls the magnitude of the bias current. Set to the minimum value "0000". At this time, the digitally controlled current mirror... Output its minimum available bias current ;

[0102] The system waits for a preset stabilization time (e.g., 1 microsecond) to allow the VCO to attempt to start oscillate and reach an initial stable state under minimum current.

[0103] Oscillation Amplitude Detection and Comparison:

[0104] Peak detection: Peak detection circuit ( Figure 4 Continuously monitor the two differential outputs of the VCO. and (Right now and ); through capacitor , Coupling, resistance , and transistors , The envelope detector is constructed to extract the peak voltage of the oscillation signal;

[0105] Threshold comparison: The extracted peak voltage is compared with a programmable threshold voltage. Comparison, Voltage divider network (by resistor) ) is generated and can be switched , By selecting different voltage divider points, the target oscillation amplitude can be flexibly set. The comparison results are then amplified, filtered, and inverted. Shaping, outputting a clear digital signal. ;

[0106] Logical judgment: A logic '0' indicates that the current oscillation amplitude is below the target threshold. ; A logic '1' indicates that the current oscillation amplitude has reached or exceeded the target threshold. .

[0107] Closed-loop dynamic adjustment:

[0108] Handling insufficient amplitude: If insufficient amplitude is detected The digital logic control circuit's judgment amplitude is insufficient. It will... The value is increased by 1 (e.g., from "0000" to "0001"), thus commanding... Increase the output current to the bias circuit by a step size;

[0109] Iteration and Stabilization: After increasing the current, wait another 1 microsecond for the VCO to stabilize, and then re-detect. This process of "detection-judgment-increase current-redetection" is repeated cyclically, forming a digital closed-loop control;

[0110] Calibration complete: The cycle terminates under any of the following conditions:

[0111] a) The change to '1' indicates that the oscillation amplitude has reached the target, and the calibration is successful. The value is locked;

[0112] b) Reaching the maximum value "1111" (corresponding to 15) indicates that even if the bias current has increased to the maximum, it still cannot reach the target amplitude (possibly due to extreme process angles or abnormal loads). The system is operating at maximum current and may trigger an alarm.

[0113] This method achieves adaptive calibration of VCO oscillation amplitude through digital closed-loop control. It automatically compensates for the effects of process variations, temperature changes, and power supply fluctuations, ensuring that each chip automatically adjusts to the optimal power-performance balance point under any operating conditions, greatly improving product consistency and reliability.

[0114] Example 5:

[0115] A method for calibrating the amplitude of a voltage-controlled oscillator (VCO) is proposed, which modifies the VCO calibration scheme in Example 4 to a resistance calibration method, such as... Figure 6 As shown, Add a switching adjustable resistor to the source of the transistor. Amplitude calibration is achieved by adjusting... The magnitude of the voltage changes the bias voltage of the voltage-controlled oscillator. This changes the oscillation amplitude of the oscillator.

[0116] Example 6:

[0117] The specific implementation process of a radio frequency communication chip is as follows:

[0118] Chip integration: Using standard CMOS technology (such as 40nm or 28nm RF CMOS), the complete voltage-controlled oscillator described in Example 2 (including low-noise bias circuit, VCO core, peak detection circuit, and digital logic control circuit) is integrated as a macro module into a radio frequency system-on-a-chip (RF SoC) or radio frequency transceiver chip.

[0119] This VCO module serves as the core oscillation source for the on-chip phase-locked loop (PLL) frequency synthesizer, and its voltage-controlled terminal (connected to...) tuning voltage It receives control voltage from the loop filter in the PLL to generate the required precise high-frequency signal;

[0120] Chip-level workflow:

[0121] Power-on and calibration: After the chip is powered on, the RF control logic first initiates the VCO amplitude calibration process (i.e., the method described in Example 4). Within tens of microseconds, the VCO automatically completes the amplitude calibration and locks the optimal bias current.

[0122] Normal operation: After calibration, the VCO enters a stable operating state with low phase noise. The pure local oscillator signal it generates can be used directly for modulation of the transmit path or mixing of the receive path, and can also provide a clock for digital circuits through a frequency divider.

[0123] Continuous noise suppression: Throughout the entire operation, the noise cancellation method described in Example 3 works continuously online, suppressing bias and core circuit noise in real time, ensuring that the phase noise performance is always superior to that of the traditional structure across all channels and temperature ranges.

[0124] This RF communication chip can be specifically used in:

[0125] The radio frequency front-end module of 5G smartphones provides the core local oscillator for Sub-6GHz band transceivers;

[0126] Internet of Things (IoT) terminal chips, such as communication chips that support Bluetooth 5.2 or Zigbee, benefit from the amplitude calibration function of the VCO, while the excellent phase noise improves the receiving sensitivity.

[0127] Wi-Fi 6 / 6E client access points require VCOs with extremely low phase noise to suppress adjacent channel interference in high-throughput multi-channel environments.

[0128] The radio frequency communication chip in this embodiment, by integrating an innovative VCO with "noise self-cancellation" and "amplitude self-calibration" capabilities, achieves the following system-level advantages:

[0129] 1) Superior communication quality (high receiver sensitivity, low bit error rate);

[0130] 2) Higher production yield and temperature stability;

[0131] 3) Longer battery life (optimized power consumption);

[0132] 4) Smaller peripheral circuit requirements (high integration), thus providing a significant technological advantage in the competition of high-end RF markets such as 5G and IoT.

[0133] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts therein embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A low-noise bias circuit for a voltage-controlled oscillator, characterized in that, include: Bias circuit, used to provide bias voltage for the core circuit of voltage-controlled oscillator; The bias circuit is connected to the core circuit of the voltage-controlled oscillator via the center tap of an inductor, which is used to feed back low-frequency noise in the core circuit of the voltage-controlled oscillator to the bias circuit in order to reduce phase noise. The bias circuit includes: Digitally controlled current mirror ; First NMOS transistor Second NMOS transistor Third NMOS transistor Fourth NMOS transistor Fifth NMOS transistor First capacitor Second capacitor The cascaded mirror image and noise cancellation path are formed; The current output terminal of the digitally controlled current mirror MIRIB is connected to the gate of the first NMOS transistor NM1, the gate of the fourth NMOS transistor NM4, the drain of the fifth NMOS transistor NM5, and one end of the first capacitor C1, respectively. The drain of the first NMOS transistor NM1 is connected to the current output terminal of the digitally controlled current mirror MIRIB, and the source of the first NMOS transistor NM1 is shorted to the gate of the second NMOS transistor NM2 and the drain of the second NMOS transistor NM2, respectively. The source of the second NMOS transistor NM2 is shorted to the gate and drain of the third NMOS transistor NM3, respectively. The source of the third NMOS transistor NM3, the other end of the first capacitor C1, and the source of the fifth NMOS transistor NM5 are all grounded. The source of the fourth NMOS transistor NM4 serves as the voltage output terminal Vreg, which is connected to the power supply terminal of the core circuit of the voltage-controlled oscillator. The source of the fourth NMOS transistor NM4 is connected to one end of the second capacitor C2, and the drain of the fourth NMOS transistor NM4 is connected to the system power supply VDD. The other end of the second capacitor C2 is grounded; Among them, the fifth NMOS transistor The gate is connected to the center tap of the inductor; Also includes: A peak detection circuit is used to detect the oscillation amplitude of the core circuit of the voltage-controlled oscillator; A digital logic control circuit is used to adjust the current value of the digital control current mirror according to the output signal of the peak detection circuit.

2. The low-noise bias circuit according to claim 1, characterized in that, The peak detection circuit includes: First input coupling capacitor Second input coupling capacitor ; One end of the first input coupling capacitor C11 is connected to a differential output signal Vcon of the voltage-controlled oscillator core circuit, and the other end of the first input coupling capacitor C11 is connected to the gate of the fourteenth NMOS transistor NM14 and one end of the ninth resistor R18. One end of the second input coupling capacitor C12 is connected to another differential output signal Vcop of the voltage-controlled oscillator core circuit, and the other end of the second input coupling capacitor C12 is connected to the gate of the fifteenth NMOS transistor NM15 and one end of the tenth resistor R19 respectively. The other end of the ninth resistor R18 and the other end of the tenth resistor R19 are respectively connected to the voltage VBIAS. The threshold-adjustable comparison path uses a resistor string consisting of a first resistor R10, a second resistor R11, a third resistor R12, and a fourth resistor R13 connected in series with a first switch. Second switch Generates an optional threshold voltage ; The first resistor R10, the second resistor R11, the third resistor R12, and the fourth resistor R13 are connected in series. One end of the first resistor R10 is grounded, and the other end of the first resistor R10 is connected to one end of the second resistor R11 and leads out the voltage VBIAS. The other end of the second resistor R11 is connected to one end of the third resistor R12, the other end of the third resistor R12 is connected to one end of the fourth resistor R13, and the other end of the fourth resistor R13 is connected to the system power supply VDD. One end of the first switch S1 is connected to one end of the third resistor R12; the other end of the first switch S1 is short-circuited with one end of the second switch S2, and together they output a threshold voltage VTH, which is connected to the gate of the thirteenth NMOS transistor NM13. The other end of the second switch S2 is connected to the other end of the third resistor R12; Composed of the tenth PMOS transistor Eleventh PMOS transistor First mirror pair tube and including the tenth NMOS transistor Eleventh NMOS transistor 12th NMOS transistor The signal amplification and filtering structure is formed by the second mirror pair of transistors; The source of the tenth PMOS transistor PM10 is connected to the system power supply VDD. The gate of the tenth PMOS transistor PM10 is shorted to the drain of the tenth PMOS transistor PM10. The drain of the tenth PMOS transistor PM10 is connected to the gate of the eleventh PMOS transistor PM11, the drain of the fourteenth NMOS transistor NM14, and the drain of the fifteenth NMOS transistor NM15, respectively. The source of the eleventh PMOS transistor PM11 is connected to the system power supply VDD, and the drain of the eleventh PMOS transistor PM11 is connected to the gate of the twelfth PMOS transistor PM12 and the drain of the thirteenth NMOS transistor NM13. The gate of the tenth NMOS transistor NM10 is shorted to the drain of the tenth NMOS transistor NM10 and connected to the system power supply VDD; the source of the tenth NMOS transistor NM10 is grounded, and the gate of the tenth NMOS transistor NM10 is connected to the gate of the eleventh NMOS transistor NM11 and the gate of the twelfth NMOS transistor NM12 respectively. The source of the eleventh NMOS transistor NM11 is grounded, and the drain of the eleventh NMOS transistor NM11 is connected to the source of the fourteenth NMOS transistor NM14, the source of the fifteenth NMOS transistor NM15, and the source of the thirteenth NMOS transistor NM13, respectively. The drain of the twelfth NMOS transistor NM12 is connected to the drain of the twelfth PMOS transistor PM12, serving as the output terminal of the peak detection circuit. The output terminal of the peak detection circuit is connected to the input terminal of the inverter INV11. The source of the twelfth NMOS transistor NM12 is grounded; The source of the twelfth PMOS transistor PM12 is connected to the system power supply VDD.

3. The low-noise bias circuit according to claim 1, characterized in that, The digital logic control circuit performs the following steps: Initialize the current control word to its minimum value; Detect the output level of the peak detection circuit; If the output is low, the current control word is gradually increased until the output is high or reaches the maximum value.

4. A voltage-controlled oscillator, characterized in that, include: The low-noise bias circuit according to any one of claims 1 to 3; The core circuit of the voltage-controlled oscillator includes a cross-coupled first PMOS transistor. Second PMOS transistor The PMOS pair consists of a sixth NMOS transistor. 7th NMOS transistor The NMOS pair and inductor are formed and variable capacitor ; The source of the first PMOS transistor PM1 is shorted to the source of the second PMOS transistor PM2 and a bias voltage Vreg is applied. The gate of the first PMOS transistor PM1 is connected to the drain of the second PMOS transistor PM2, one end of the inductor L1, one end of the variable capacitor VAR1, the drain of the sixth NMOS transistor NM6, and the gate of the seventh NMOS transistor NM7. The drain of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, the other end of the inductor L1, the other end of the variable capacitor VAR1, the drain of the seventh NMOS transistor NM7, and the gate of the sixth NMOS transistor NM6. The source of the sixth NMOS transistor NM6 is grounded; The source of the seventh NMOS transistor NM7 is grounded; The center tap of the inductor L1 is led out separately and connected to the gate of the fifth NMOS transistor NM5; Wherein, the inductor The center tap is connected to the bias circuit.

5. The voltage-controlled oscillator according to claim 4, characterized in that, The output of the voltage-controlled oscillator core circuit is connected to the input of the peak detection circuit to form a closed-loop amplitude control.

6. A noise cancellation method for a voltage-controlled oscillator, characterized in that, Includes the following processes: The low-frequency noise voltage in the core circuit of the voltage-controlled oscillator is extracted by the center tap of the LC resonant inductor. The noise voltage is fed back to the gate of the feedback MOS transistor of the low-noise bias circuit according to any one of claims 1 to 3 to generate a canceling current; The cancellation current reduces the noise current flowing into the core circuit of the voltage-controlled oscillator.

7. A method for calibrating the amplitude of a voltage-controlled oscillator, characterized in that, Includes the following processes: Detect the peak voltage of the oscillation signal; The peak voltage is compared with the adjustable threshold voltage; Based on the comparison results and by dynamically adjusting the bias current using the low-noise bias circuit described in any one of claims 1 to 3, the oscillation amplitude is brought close to the target threshold.

8. A radio frequency communication chip, characterized in that, It integrates the voltage-controlled oscillator as described in claim 4 or 5.

Images