A method for implementing a variable power rail based on ATE power supplies and digital board cards

Abstract

The present application relates to the technical field of power supply control of ATE (Automatic Test Equipment), in particular to a variable power rail implementation method based on ATE power supply and digital board card, which outputs a basic voltage through a MCU-controlled DAC chip with self-shutdown function, connects a FB pin of a DC-DC chip after dynamic adjustment of amplification multiple by an operational amplifier, switches the voltage regulation mode and shutdown mode in cooperation with an analog switch module, and adds a real-time voltage calibration step to correct errors, thereby realizing the functions of wide-range, high-precision and automatic voltage regulation of the DC-DC power rail, adapting to the voltage requirements of different DUTs in the ATE tester, and significantly improving the shutdown reliability and test accuracy.

Description

Technical Field

[0001] This invention relates to the field of power control technology for ATE (Automatic Test Equipment) systems, specifically a method for implementing variable power rails based on ATE power supplies and digital boards. Background Technology

[0002] In batch testing scenarios of ATE (Automatic Test Equipment) automated test equipment, power supplies and digital boards need to provide stable and compatible voltages for DUTs of different specifications. DC-DC chips are general-purpose power supply chips, but the output voltage range of traditional DC-DC power rails is fixed by hardware voltage divider resistors, which cannot flexibly respond to the diverse needs of DUTs. Existing inventions for adjusting the DC-DC output voltage (VOUT) mainly include manual variable resistor voltage regulation schemes, MCU / FPGA-PWM voltage regulation schemes, and ordinary DAC voltage regulation schemes. Among them, the manual variable resistor voltage regulation scheme replaces the voltage divider resistor of the DC-DC chip's FB pin with a variable resistor and manually adjusts the voltage division ratio to change VOUT. This method relies on the operator's technical experience and has low voltage regulation accuracy. If a multi-level resistor switching is used, continuous voltage regulation cannot be achieved. Moreover, ATE boards are mostly sealed packages, and manual adjustment requires disassembling the board, which compromises the integrity of the equipment and is inefficient.

[0003] The MCU / FPGA-PWM voltage regulation scheme uses the IO pins of the MCU / FPGA to output a PWM wave, which is then filtered by RC and connected to the FB pin of the DC-DC chip. The FB voltage is adjusted by the idle ratio. However, most MCU / FPGA IO output voltages have a low upper limit, resulting in a low adjustable voltage range of the FB pin. This, in turn, compresses the output voltage range of the DC-DC chip, making it unable to meet the testing requirements of high-voltage DUTs.

[0004] A typical DAC voltage regulation scheme outputs an analog voltage through the DAC chip and connects it to the FB pin. However, most ordinary DACs do not have a self-turn-off function. When there is no control signal from the MCU / FPGA, the DAC still outputs a residual voltage, which causes overvoltage or undervoltage fluctuations when the DC-DC converter starts up, affecting the accuracy of the DUT test results.

[0005] In summary, existing inventions for adjusting DC-DC output voltage (VOUT) cannot simultaneously meet the ATE test equipment's requirements for "wide range, high precision, high reliability, and automation" of DC-DC power rails. Therefore, this invention provides a method for implementing variable power rails based on ATE power supplies and digital boards. Summary of the Invention

[0006] This invention aims to provide a variable power rail implementation method based on ATE power supply and digital board. The method is based on a hardware architecture of MCU + self-turn-off multi-channel DAC + dynamic amplification operational amplifier + analog switch + voltage calibration module. It solves the problem that existing inventions for adjusting DC-DC output voltage (VOUT) cannot simultaneously meet the requirements of ATE test equipment for wide range, high precision, high reliability and automation of DC-DC power rail.

[0007] This invention solves the above-mentioned technical problems through the following method: a variable power rail implementation method based on ATE power supply and digital board, comprising the following steps:

[0008] S1. System initialization: The MCU controls analog switches S1 to open and S2 to close, grounding the output of the operational amplifier circuit, sending a shutdown command to the multi-channel DAC chip with self-turn-off function to make it enter a high-impedance state, configuring the initial output voltage of the DC-DC chip, and starting the voltage calibration module to calculate the ADC calibration factor.

[0009] S2, DUT voltage requirement processing: Receive the DUT target voltage VOUT sent by the AET system, calculate the target output voltage Vamp of the amplifier circuit based on the DC-DC output voltage, and then, in combination with the current amplification factor A of the operational amplifier circuit, calculate the target output voltage Vdac of the DAC chip.

[0010] S3, Voltage Regulation Mode Switching: The MCU controls the analog switch S2 to open and S1 to close, sending an SPI command to the DAC chip to make it output the target voltage Vdac. After being amplified by the operational amplifier circuit, it is connected to the FB pin of the DC-DC chip, and the DC-DC chip dynamically adjusts the output voltage.

[0011] S4. Real-time voltage calibration: The voltage calibration module acquires the output voltage of the operational amplifier circuit and the DC-DC output voltage, and corrects the actual voltage value using the ADC calibration factor. If the deviation between the actual voltage and the target voltage is >0.1%, the amplification factor of the operational amplifier circuit and the DAC output voltage are adjusted until the deviation is ≤0.1%.

[0012] S5, Shutdown Mode Switching: After the DUT test is completed, the MCU controls S1 to open and S2 to close, the DAC chip enters the self-shutdown mode, and the DC-DC chip restores the initial output voltage.

[0013] The positive and progressive effects of this invention are as follows:

[0014] 1. By combining operational amplifier dynamic amplification with DAC (0~5V) output, the operational amplifier output voltage covers 0~15V, thereby enabling the DC-DC output voltage to cover 0.8V~36V. This allows for compatibility with various DUT specifications, including low-voltage and high-voltage models, solving the problem of limited range in existing solutions. By employing a 12-bit DAC (accuracy ±0.05%) and a real-time calibration module, the DC-DC output voltage deviation is ≤0.1%, and the voltage regulation accuracy is far higher than that of manual adjustment solutions and ordinary DAC solutions.

[0015] 2. The combination of the DAC's self-turn-off mode and the S2 grounding design ensures that there are no abnormal voltage fluctuations in the DC-DC converter when there is no control signal, significantly improving startup stability. Moreover, the entire process is controlled by the MCU through SPI communication without manual intervention. The voltage regulation response time is <10ms, making it suitable for batch testing scenarios of ATE and greatly improving testing efficiency. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of a manual variable resistor voltage regulation scheme in the prior art.

[0017] Figure 2 This is a circuit diagram of an existing MCU / FPGA-PWM voltage regulation scheme.

[0018] Figure 3 This is a circuit diagram of a common DAC voltage regulation scheme in the prior art.

[0019] Figure 4 The circuit diagram is shown for the DC-DC variable power rail implementation method based on the self-turn-off DAC+ operational amplifier circuit provided by the present invention.

[0020] Figure 5 This is a schematic diagram of the internal structure and switching control of the DAC chip provided in Embodiment 1 of the present invention.

[0021] Figure 6 This is a schematic diagram of the internal structure and switching control of the DAC chip provided in Embodiment 2 of the present invention. Detailed Implementation

[0022] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments.

[0023] Example 1:

[0024] See Figures 1 to 5 A method for implementing variable power rails based on ATE power supplies and digital boards includes the following steps:

[0025] S1. System initialization: The MCU controls analog switches S1 to open and S2 to close, grounding the output of the operational amplifier circuit, sending a shutdown command to the multi-channel DAC chip with self-turn-off function to make it enter a high-impedance state, configuring the initial output voltage of the DC-DC chip, and starting the voltage calibration module to calculate the ADC calibration factor.

[0026] The DAC chip is a DAC53508, with a resolution of at least 12 bits, supporting 8-channel output, output current of less than 1 microamp in shutdown mode, and linearity error of less than 0.05%.

[0027] The voltage calibration module includes a standard voltage source and an ADC module of the MCU. The standard voltage source is REF5050 with an output accuracy of ±0.1%. The formula for calculating the ADC calibration factor K is: K = standard voltage source output value / ADC module acquisition value.

[0028] S2, DUT voltage requirement processing: Receive the DUT target voltage VOUT sent by the AET system, calculate the target output voltage Vamp of the amplifier circuit based on the DC-DC output voltage, and then, in combination with the current amplification factor A of the operational amplifier circuit, calculate the target output voltage Vdac of the DAC chip.

[0029] The formula for the DC-DC output voltage is:

[0030] ;

[0031] Where Vamp is the operational amplifier output voltage, Vref is the fixed reference voltage inside the DC-DC chip, VOUT is the DC-DC output voltage, and R3, RFB1 and RFB2 are all preset fixed resistors in the circuit;

[0032] The amplification factor A of the operational amplifier circuit is dynamically adjusted through an adjustable feedback resistor network, which includes a fixed resistor Rf1 and a digital potentiometer Rf2. The amplification factor formula is: A=1+(Rf1+Rf2) / Ri, where Ri is the input resistance of the operational amplifier circuit, and the amplification factor A ranges from 1 to 5.

[0033] like Figure 5 As shown in the figure, SCLK is the serial clock signal, SDI is the serial data input, SYNC is the synchronization signal, LDAC is the DAC register load signal, CLR is the clear signal, AGND is the analog ground, VREFIN is the reference voltage input, VOUTA corresponds to the analog voltage output of channel A, and VOUTH corresponds to the analog voltage output of channel H. The multi-channel DAC chip simultaneously provides output voltage to at least two sets of DC-DC power rails. Each set of DC-DC power rails corresponds to independent analog switches S1 and S2 and operational amplifier circuits, realizing parallel testing of multiple DUTs.

[0034] S3, Voltage Regulation Mode Switching: The MCU controls the analog switch S2 to open and S1 to close, sending an SPI command to the DAC chip to make it output the target voltage Vdac. After being amplified by the operational amplifier circuit, it is connected to the FB pin of the DC-DC chip, and the DC-DC chip dynamically adjusts the output voltage.

[0035] The analog switches S1 and S2 are ADG715 single-pole double-throw switches with an on-resistance of less than 5 ohms, a switching speed of less than 100 milliseconds, and support a working voltage range of 0-15V.

[0036] The MCU sends commands to the DAC chip via SPI communication. The SPI communication rate is ≥10MHz. The commands include channel selection commands and digital output voltage commands. The digital values ​​are calculated from Vdac and the DAC output range, and the calculation formula is as follows: Vdac max D is the upper limit of the DAC output voltage. max This is the maximum digital value of the DAC.

[0037] S4. Real-time voltage calibration: The voltage calibration module acquires the output voltage of the operational amplifier circuit and the DC-DC output voltage, and corrects the actual voltage value using the ADC calibration factor. If the deviation between the actual voltage and the target voltage is >0.1%, the amplification factor of the operational amplifier circuit and the DAC output voltage are adjusted until the deviation is ≤0.1%.

[0038] The specific process of the real-time voltage calibration is as follows:

[0039] S41: The ADC module of the MCU acquires the output voltage Vamp of the operational amplifier circuit and the DC-DC output voltage VOUT;

[0040] S42: Correction using ADC calibration factor K, the correction formula satisfies: Vamp 实际 =Vamp 采集 ×K, VOUT 实际 =VOUT 采集 ×K;

[0041] S43: If |VOUT 实际 -VOUT 目标 If the deviation is greater than 0.1, first adjust the digital potentiometer Rf2 to correct the amplification factor A, and then fine-tune the digital value of the DAC output voltage until the deviation is ≤0.1%.

[0042] S5, Shutdown Mode Switching: After the DUT test is completed, the MCU controls S1 to open and S2 to close, the DAC chip enters the self-shutdown mode, and the DC-DC chip restores the initial output voltage.

[0043] After the DAC chip enters the self-shutdown mode, the MCU also controls the DC-DC chip to enter the standby mode to reduce the power consumption of the AET power supply and the digital board. If the next DUT needs to be tested, repeat S2-S4.

[0044] Example 2:

[0045] Please see Figure 6 In addition, a self-shutdown DAC is selected to ensure that the output voltage is 0V when uncontrolled, which will not affect the subsequent load. Through the calibrated circuit, the output voltage value is adjustable, ensuring high-precision output for the DUT.

[0046] Variable power rail output unit: The MCU sets the output value for the DAC, and the DAC adjusts the voltage value of the DC-DC chip FB by proportionally adjusting the output voltage through the voltage divider resistors, thereby achieving adjustable DC-DC voltage output. The specific DC-DC output voltage formula is as follows:

[0047] ;

[0048] V dac The output voltage value of the DAC and the clamping protection circuit unit are connected to the DC-DC output terminal through a comparator and a diode. The positive input of the comparator is the output of the DC-DC, and the negative input is the preset maximum / minimum voltage value. When the DC-DC is working, the output voltage VOUT will be compared with the preset Vmax and Vin. Once the preset value is exceeded, the circuit will automatically clamp the VOUT voltage to the set voltage value, thereby protecting the subsequent circuit.

[0049] This invention revolves around an integrated power rail output and calibration protection structure for automatic testing equipment. The overall structure comprises a variable power rail output unit, a clamping protection circuit unit, and a voltage calibration unit, with the control unit uniformly handling setting, sampling, calculation, compensation, and status determination. The variable power rail output unit generates the target output voltage and maps it to a control quantity; the clamping protection circuit unit implements hardware-level limiting of the output node when abnormal overvoltage or undervoltage trends occur; and the voltage calibration unit parametrically corrects the gain and zero-point deviations between the acquisition and output links, establishing a stable and consistent correspondence between the control settings and the actual output, and between the sampled readings and the true voltage.

[0050] The variable power rail output unit employs a closed-loop path of digital setting—analog control—feedback adjustment. The control unit first generates a digital setting code based on the target output voltage and sends it to the digital-to-analog converter (DAC). The DAC outputs an analog voltage corresponding to the digital setting code. This analog voltage enters a proportional network composed of voltage divider resistors. After transformation by the proportional network, it is applied to the feedback terminal of the DC-DC converter chip, ensuring the feedback voltage falls within the closed-loop adjustment range of the chip's internal reference voltage. The DC-DC converter chip adjusts the power stage duty cycle accordingly, thereby forming a voltage rail at the output terminal consistent with the target output. The above mapping relationship is parameterized during the circuit design phase: the DC-DC converter chip's internal reference voltage is taken from the chip's technical datasheet; the resistance values ​​of the voltage divider resistors are determined by the design selection and remain consistent after assembly; the control unit, based on the internal reference voltage and the voltage divider network ratio, first calculates the target feedback voltage corresponding to the target output voltage, then reverse-engineers the analog voltage required for the DAC output, ultimately obtaining the DAC's digital setting code.

[0051] To prevent the control quantity from exceeding the device's operating boundary, the control unit performs boundary trimming before generating the digital setting code: if the target output exceeds the upper limit allowed by the power rail, the target is limited to the upper limit; if the target output is lower than the lower limit allowed, the target is limited to the lower limit. The upper and lower limits are taken from the withstand voltage index of the downstream test object, the withstand voltage index of the interface protection device, and the stable operating range of the DC-DC converter chip, and allowances are reserved for manufacturing deviations and temperature drift. The allowance is a fixed percentage value within the range of 5% to 10% of the withstand voltage index of the downstream stage, and the specific percentage is determined by the system's target accuracy and reliability level.

[0052] The clamping protection circuit unit employs a hardware link of comparison judgment—amplitude limiting conduction—output constraint, directly connected to the output of the DC-DC converter chip to form fast protection. The non-inverting input of the comparator is connected to the output voltage sampling point, and the inverting input is connected to the preset maximum or minimum voltage threshold node. The threshold node is generated by the control unit providing the set voltage and passing it through a voltage divider network, or by a dedicated reference source and an adjustable voltage divider network. During operation, the output voltage is continuously compared with the maximum and minimum thresholds: when the output voltage is higher than the maximum threshold, the comparator output flips and drives the clamping branch to conduct, suppressing the output voltage to near the threshold through a diode conduction path or a controlled clamping device; when the output voltage is lower than the minimum threshold and triggers the undervoltage clamping strategy, the comparator drives the corresponding branch to apply controlled traction to the output node or triggers a shutdown linkage, keeping the output node within a controlled range not lower than the minimum threshold, thereby preventing the subsequent stage from entering an abnormal operating point.

[0053] To suppress frequent switching caused by jitter near the threshold, a hysteresis network is introduced on the comparator input side to create hysteresis. The hysteresis is set to 2 to 3 times the peak-to-peak value of the output noise. The peak-to-peak value of the output noise is obtained statistically by the sampling circuit under both no-load and typical load conditions, and the larger value of the two conditions is taken as the design benchmark. To suppress transient spike false triggering, a shortest decision time window is introduced on the comparator output side. The time window is set to more than 10 times one switching cycle of the switching power supply, so that spikes within a single cycle do not trigger clamping action. After clamping action occurs, the control unit reads the comparator status and enters the fault handling procedure. The procedure includes reducing the target output, freezing the target update, and recording the number of triggers and the trigger duration. The number of triggers and the duration are used to distinguish between occasional spikes and continuous anomalies. The threshold for the number of triggers is 3, and the threshold for the duration is 5 milliseconds. If either of them is met, it is determined to be a continuous anomaly, and a protection shutdown strategy is executed.

[0054] The voltage calibration unit comprises two parts: acquisition circuit calibration and output circuit calibration. The calibration sequence is uniformly arranged by the control unit and forms two calibration paths with the analog switch: the reference path injects a standard voltage into the acquisition circuit, and the output path sends the output voltage of the DC-DC converter chip into the sampling link to form a closed-loop acquisition. Acquisition circuit calibration is performed under no-load conditions at the output. The control unit first switches the calibration switch to the reference voltage source path, with the reference voltage source outputting 5V. This value originates from the system's nominal reference voltage and covers the upper end of the sampling range. Subsequently, the control unit switches the calibration switch to the ground potential path, with ground potential corresponding to 0V and covering the lower end of the sampling range. The control unit acquires the raw sampling readings at 0V and 5V respectively, and constructs ideal reading reference values ​​on the calculation side. The ideal reading reference value is 0V at 0V and 5V at 5V. Based on this, the control unit calculates the proportional coefficient and bias coefficient of the acquisition link: the proportional coefficient is the ideal voltage difference divided by the actual sampling voltage difference, and the bias coefficient is the ideal zero point minus the proportional coefficient multiplied by the actual zero point reading. The proportional coefficient is used to correct the gain deviation of the sampling reading, and the bias coefficient is used to correct the zero point deviation of the sampling reading. After calibration, each time the sampling link generates a raw reading, the control unit first performs bias correction on the raw reading, and then performs proportional correction to obtain the calibrated sampling voltage value. To ensure the effectiveness of the two-point acquisition, the acquisition stability criterion adopts continuous sampling consistency verification: 10 consecutive acquisitions are made at each injection point. If the difference between the maximum and minimum values ​​does not exceed 2 millivolts, the injection point is considered stable. The 2 millivolts is determined based on the equivalent uncertainty of the quantization resolution of the sampling device and the input noise, and twice its upper limit is taken as the stability threshold, thus balancing speed and reliability.

[0055] Output circuit calibration corrects the mapping error between the software preset voltage and the actual output voltage. The calibration process relies on the calibrated sampling link to avoid the superposition of sampling errors and output errors. The control unit switches the calibration switch to the DC-DC converter chip output path, sequentially issues preset voltages according to a multi-point sequence covering the range, and completes output stability determination. The multi-point sequence is constructed in a step-by-step manner, with a step size of 0.5 volts, starting with the minimum output and ending with the maximum output, ensuring sufficient density of points within the range to support linear fitting and cover endpoint deviations. At each point, the control unit first generates the digital-to-analog setting code corresponding to the target preset voltage and drives the output. After the output enters the stable range, the sampling link reads the actual output voltage value. The stability criterion is consistent with the acquisition calibration, using the condition that the maximum and minimum difference between 10 consecutive samples does not exceed 2 millivolts. The control unit pairs the actual output voltage value of each point with the corresponding preset voltage value and performs least-squares fitting on all data points to obtain the proportional coefficient and bias coefficient of the output link. The least squares fitting calculation process unfolds in the following data processing order: first, sum the actual output voltages of all points; then, sum the preset voltages of all points; finally, sum the squares of the actual output voltages of all points; and then sum the products of the actual output voltages and preset voltages of all points. The summation results are then substituted into the normal solution steps of linear fitting to obtain the proportional coefficient and bias coefficient that minimize the overall squared error. The proportional coefficient is used to correct the proportional error of the output link, and the bias coefficient is used to correct the zero-point error of the output link. To prevent single-point anomalies from affecting the fitting, the control unit calculates the residual for each data point. The residual is the difference between the preset voltage and the estimated preset voltage derived from the fitting relationship. When the absolute value of the residual exceeds 20 millivolts, the point is determined to be abnormal and resampling is triggered. The resampling is performed twice; if the point is still abnormal, it is removed, and the reason for removal is recorded. The 20 millivolt threshold is determined by superimposing twice the target output accuracy of 10 millivolts with the sampling uncertainty, forming a robust judgment boundary for anomalies.

[0056] After entering the actual testing phase, the control unit maintains the calibration switch in the DC-DC converter chip output path, increasing the voltage from the lowest preset voltage to the highest preset voltage in 0.5-volt increments. Before each output step, the control unit first performs pre-compensation on the preset voltage using the proportional coefficient and bias coefficient of the output link, and then the digital-to-analog converter drives the DC-DC converter chip to form the compensated output. After the output stabilizes, the sampling link first uses the proportional coefficient and bias coefficient of the acquisition link to calibrate the original sampling reading, and then compares the calibrated sampling voltage with the current preset voltage to determine the error. The error judgment threshold is set at 10 millivolts. The determination of 10 millivolts is based on the system's target accuracy index and the allowable deviation of the subsequent sensitive circuit, and a margin is given in combination with the comprehensive uncertainty of sampling resolution, noise, and temperature drift to ensure repeatability of the judgment. When the error exceeds 10 millivolts, the control unit enters a secondary adjustment process. The secondary adjustment process fine-tunes the compensation amount at the current point according to the proportional coefficient and measures it again. The fine-tuning step size is the equivalent digital-to-analog setting code increment corresponding to 1 millivolt, and the upper limit of the number of fine-tunings is 10. If the error still exceeds the upper limit, it is judged as hardware drift or load abnormality and the protection strategy is triggered.

[0057] To enhance engineering robustness, this invention further introduces three collaborative mechanisms and embeds them into the aforementioned data processing link. First, a threshold self-calibration linkage mechanism: the maximum and minimum voltage thresholds are recalculated after acquisition and output calibration, aligning the clamping threshold with the calibrated true output reference and preventing protection misjudgments caused by threshold source errors. Second, a load-related compensation mechanism: the control unit synchronously acquires the output current or load indication after each output stabilization and manages the compensation parameters in groups according to load ranges. A set of proportional coefficients and bias coefficients are maintained for light and heavy load ranges respectively. A hysteresis strategy is used when switching ranges, with the hysteresis width being three times the peak-to-peak value of the load noise, thereby reducing voltage drop errors caused by load changes. Third, a periodic self-check mechanism: the control unit performs a rapid verification of the 0V and 5V reference path once at a preset cycle. The verification is only collected three times, and the median value is used as the judgment value. When the verification error exceeds 5 millivolts, a complete two-point calibration is triggered to suppress long-term drift at low cost and improve long-term consistency. The aforementioned collaborative mechanism, together with the existing output regulation, clamping protection, and calibration compensation, forms a closed-loop system, enabling the variable power rail to have higher output accuracy, anomaly suppression capability, and long-term stability in automatic testing equipment scenarios.

[0058] This invention is not limited to the embodiments described above. Any changes in shape or structure shall fall within the protection scope of this invention. The protection scope of this invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of this invention, but all such changes and modifications shall fall within the protection scope of this invention.

Claims

1. A method for implementing variable power rails based on ATE power supply and digital board, characterized in that, Includes the following steps: S1. System Initialization: The MCU connects to the DAC chip via the SPI bus and controls the first analog switch S1 and the second analog switch S2. S1 and S2 are single-pole double-throw switches. One end of S1 is connected to the output of the operational amplifier circuit, and the other end of S1 is connected to the FB pin of the DC-DC chip and one end of S2. The other end of S2 is grounded. The feedback pin FB of the DC-DC chip is connected to the output of the operational amplifier circuit through resistor R3, connected to the voltage output VOUT of the DC-DC chip through resistor RFB1, and grounded through resistor RFB2. The input of the DC-DC chip is connected to a fixed voltage VIN, and the output VOUT provides the power supply voltage to the device under test (DUT). The MCU controls analog switch S1 to open and S2 to close, grounding the output of the operational amplifier circuit, sending a shutdown command to the multi-channel DAC chip with self-turn-off function to put it into a high-impedance state, configuring the initial output voltage of the DC-DC chip, and starting the voltage calibration module to calculate the ADC calibration factor. The voltage calibration module in S1 includes a standard voltage source and an ADC module of the MCU. The standard voltage source is REF5050 with an output accuracy of ±0.1%. The calculation formula for the ADC calibration factor K is: K = standard voltage source output value / ADC module acquisition value. S2, DUT Voltage Demand Processing: Receives the DUT target voltage VOUT from the ATE system. set The operational amplifier output voltage Vamp of the amplifier circuit is calculated based on the DC-DC output voltage. Then, combined with the current amplification factor A of the operational amplifier circuit, the target output voltage Vdac of the DAC chip is calculated in reverse. The formula for the DC-DC output voltage in S2 is: ； Where Vamp is the operational amplifier output voltage, Vref is the internal fixed reference voltage of the DC-DC chip, VOUT is the DC-DC output voltage, and R3, RFB1, and RFB2 are all preset fixed resistors in the circuit; the target voltage VOUT set The preset output voltage of the DC-DC chip supplied to the DUT by the ATE system is used; the actual voltage is the real output voltage of the DC-DC chip after being acquired by the ADC and corrected by the calibration factor. S3, Voltage Regulation Mode Switching: The MCU controls the analog switch S2 to open and S1 to close, sending an SPI command to the DAC chip to make it output the target voltage Vdac. After being amplified by the operational amplifier circuit, it is connected to the FB pin of the DC-DC chip, and the DC-DC chip dynamically adjusts the output voltage. In S3, the MCU sends commands to the DAC chip via SPI communication. The SPI communication rate is ≥10MHz. The commands include channel selection commands and output voltage digital commands. The digital values ​​are calculated from Vdac and the DAC output range, and the calculation formula is as follows: Vdac max D is the upper limit of the DAC output voltage. max This is the maximum digital value of the DAC; S4. Real-time voltage calibration: The voltage calibration module acquires the output voltage of the operational amplifier circuit and the DC-DC output voltage, and corrects the actual voltage value using the ADC calibration factor. If the deviation between the actual voltage and the target voltage is >0.1%, the amplification factor of the operational amplifier circuit and the DAC output voltage are adjusted until the deviation is ≤0.1%. S5, Shutdown Mode Switching: After the DUT test is completed, the MCU controls S1 to open and S2 to close, the DAC chip enters the self-shutdown mode, and the DC-DC chip restores the initial output voltage.

2. The method for implementing a variable power rail based on an ATE power supply and a digital board as described in claim 1, characterized in that: The DAC chip in S1 is a DAC53508 with a resolution of at least 12 bits, supporting 8-channel output, output current of less than 1 microamp in shutdown mode, and linearity error of less than 0.05%.

3. The method for implementing variable power rails based on ATE power supply and digital board as described in claim 1, characterized in that: The analog switches S1 and S2 in S3 are ADG715 single-pole double-throw switches with an on-resistance of less than 5 ohms, a switching speed of less than 100 milliseconds, and support a working voltage range of 0-15V.

4. The method for implementing variable power rails based on ATE power supply and digital board as described in claim 1, characterized in that: After the DAC chip in S5 enters the self-shutdown mode, the MCU also controls the DC-DC chip to enter the standby mode, reducing the power consumption of the ATE power supply and the digital board.

5. The method for implementing a variable power rail based on an ATE power supply and a digital board as described in claim 1, characterized in that: The multi-channel DAC chip in S2 simultaneously provides output voltage to at least two sets of DC-DC power rails. Each set of DC-DC power rails corresponds to independent analog switches S1 and S2 and operational amplifier circuits, enabling parallel testing of multiple DUTs.

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