A parallel adaptive presynchronization device

Abstract

This application provides a parallel adaptive pre-synchronization device, including a parallel pre-synchronization module and a feedforward timing synchronization module. The parallel pre-synchronization module includes a control calculation unit, a power calculation unit, a decision unit, a signal output unit, and a buffer. It separates the calculation input signal from multiple parallel signals based on decision parameters and stores the multiple parallel signals in the buffer. It calculates the signal power and sample point position information based on the calculation input signal. It updates the decision parameters based on the comparison result between the signal power and a preset signal power. It reads multiple candidate samples from the multiple parallel signals in the buffer based on the sample point position information. It selects the target sample point based on the multiple candidate samples using a parallel synchronization algorithm. This effectively improves the timing synchronization performance, enabling the device to support a larger dynamic range, better meeting the needs of practical use, and reducing hardware resource consumption.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a parallel adaptive pre-synchronization device. Background Technology

[0002] Broadband satellite communication systems, also known as multimedia satellite communication, refer to the processing and transmission of voice, data, images, and video via satellite. The main characteristics of broadband satellite communication include large signal bandwidth, large short-time data volume, high requirements for the real-time processing capabilities of the receiver, system complexity, and high hardware resource consumption. For long-term stable communication, broadband satellite communication systems require high-performance timing synchronization strategies that support large dynamic ranges.

[0003] In broadband satellite communication systems, timing synchronization strategies typically employ a feedback-based timing synchronization algorithm. This algorithm first performs symbol synchronization before proceeding to frame / bit synchronization. Specifically, it corrects and calculates multiple samples within a symbol acquired by the ADC to obtain a time deviation. Then, it recovers the input samples, continuing the correction calculation while simultaneously outputting an optimal sample for frame / bit synchronization according to certain rules. This process is repeated point by point until the starting position of frame synchronization is found.

[0004] During actual testing, the following issues were found with the scheduled synchronization strategy: The feedback-based timing synchronization strategy can only find the frame start position normally when the signal amplitude is stable. During long-term operation of the device, due to signal fluctuations, even slightly large fluctuations can cause the frame synchronization module to fail to find the frame start position. This is because the time deviation calculation in the feedback-based timing synchronization algorithm has a memory component. When the signal magnitude changes significantly, the time deviation calculation will have a large error, which accumulates over time and may far exceed the original time deviation value. This situation results in a very small dynamic range of signals supported by the device, which does not meet the needs of actual use. Because the timing synchronization strategy with feedback is a memory system, it is greatly affected by previous signals when correcting the best sample. Therefore, when the signal amplitude or frequency changes, the timing synchronization strategy with feedback will no longer be able to correct multiple samples within a symbol to the correct sample. This will cause the demodulator to be unable to find the frame start position and requires manual reset of the demodulator to operate normally, which will also reduce the convenience of using the equipment. Often, the accuracy of timing deviation calculations during timing synchronization is much lower than that of high-performance temperature-controlled clock chips due to limitations in algorithms and quantization during FPGA implementation. This results in a deterioration in the final timing synchronization performance. In actual testing, analysis of the ADC-acquired samples revealed that the order of the sample points for each symbol was inconsistent after each device startup, indicating that the ADC-acquired signal sampling points were not arranged in a fixed order. Assuming a feedforward timing synchronization scheme is used instead of a feedback-based timing synchronization strategy, using all samples in parallel to search for the true optimal physical layer data sample position for timing synchronization at different symbol rate levels would consume significant hardware resources. If a large amount of data is stored, the optimal sample position is directly extracted before searching for the start position of the physical layer data frame, requiring enormous hardware data storage space due to the large IQ data bit width, short bandwidth, and large data volume. Extracting only a portion of the samples for timing synchronization can effectively reduce resource consumption, but the problem of not extracting the optimal sample may still occur. Summary of the Invention

[0005] The following is an overview of the topics described in detail in this article.

[0006] The purpose of this application is to at least partially solve one of the technical problems existing in the related technologies. The embodiments of this application provide a parallel adaptive pre-synchronization device that can effectively improve synchronization performance and reduce resource consumption.

[0007] An embodiment of this application provides a parallel adaptive pre-synchronization device, comprising a parallel pre-synchronization module and a feedforward timing synchronization module; The parallel pre-synchronization module includes a control calculation unit, a power calculation unit, a decision-making unit, a signal output unit, and a buffer; The control calculation unit and the signal output unit receive multiple parallel signals. The control calculation unit separates the calculation input signal from the multiple parallel signals according to the current decision parameters. The signal output unit stores the multiple parallel signals into the buffer according to the current decision parameters. The power calculation unit calculates the signal power and sample point location information based on the calculation input signal; The decision unit updates the decision parameters based on the comparison result between the signal power and the preset signal power; The signal output unit reads multiple candidate sample points from the multi-channel parallel signal in the buffer according to the sample point position information; The feedforward timing synchronization module selects the target sample point based on multiple candidate sample points using a parallel synchronization algorithm.

[0008] According to certain embodiments of this application, the decision parameters include a signal computation length parameter; separating the computation input signal from the multi-parallel signals based on the current decision parameters includes: The multi-channel parallel signals are grouped according to the signal length parameter to separate the calculation input signal; The number of groups is related to the symbol rate, and the number of sampling points within a group is related to the signal computation length parameter.

[0009] According to certain embodiments of this application, signal power and sample location information are calculated based on the input signal, including: The first power of each sample point is calculated based on the input signal, and the second power is obtained by adding the first power of each set of sample points. The signal power and the corresponding sample location information are determined by comparing multiple second powers.

[0010] According to certain embodiments of this application, when the device is powered on or in operation, the input signal of the device has no valid signal and only noise. The decision unit updates the signal calculation time parameter based on the changes of the multiple parallel signals.

[0011] According to certain embodiments of this application, when the device is powered on, the signal calculation time parameter is set to the device power-on time; when a reset signal sent from the outside is received, the signal calculation time parameter is set to the reset end time; when the comparison result between the signal power and the preset signal power is that the signal power is less than the preset signal power, the signal calculation time parameter is set to the power comparison end time.

[0012] According to certain embodiments of this application, the decision parameters include a signal calculation length parameter; storing the multi-channel parallel signals into the cache according to the current decision parameters includes: The multiple parallel signals are stored in the buffer, and the buffer size is determined by the signal calculation length parameter and the bit width of the multiple parallel signals.

[0013] According to certain embodiments of this application, a target sample point is selected based on multiple candidate sample points using a parallel synchronization algorithm, including: The relevant peak values ​​are calculated based on the candidate sample points and the local pilot sequence. The average power is calculated based on the candidate sample points; Compare the peak-to-average power ratio (PAPR) of the relevant peak power with the average power and the preset threshold. Candidate sample points with the largest peak-to-average ratio (PAR) and PAR greater than a preset threshold are selected as target sample points.

[0014] According to certain embodiments of this application, the feedforward timing synchronization module determines the position of the target sample point as the starting position of the physical layer data frame, and outputs the physical layer data frame according to the starting position of the physical layer data frame.

[0015] According to certain embodiments of this application, the device further includes a sampling module and a filtering module. The input terminal of the sampling module is connected to the receiving antenna, the output terminal of the sampling module is connected to the filtering module, and the output terminal of the filtering module is connected to the input terminal of the parallel pre-synchronization module. The sampling module is used to perform ADC sampling on the input signal of the device, and the filtering module is used to perform polyphase filtering on the ADC-sampled signal.

[0016] According to certain embodiments of this application, the device further includes a carrier synchronization module and a demodulation decoding module, wherein the output of the feedforward timing synchronization module is connected to the input of the carrier synchronization module, and the output of the carrier synchronization module is connected to the input of the demodulation decoding module.

[0017] The above scheme has at least the following beneficial effects: it can adapt to signal fluctuations, greatly improving the dynamic range of signals supported by the device; the parallel pre-synchronization module monitors the signal in real time, eliminating the need for manual reset when the signal receiving frequency or amplitude changes, making the device more convenient to use; by selecting superior samples through the parallel pre-synchronization module, the feedforward timing module can select the best sample from the superior samples, avoiding the problem of clock error correction exceeding clock accuracy. It offers better synchronization performance compared to feedback-based timing synchronization schemes; it is suitable for situations where the ADC samples are not arranged in a fixed order, and the initial input signal does not need to be entirely sent to the feedforward timing synchronization module. Instead, it can first pass through the parallel pre-synchronization module to extract some superior samples, and then simultaneously find the best sample and the physical layer data frame position from among the superior samples, effectively improving synchronization performance and reducing resource consumption. Attached Figure Description

[0018] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0019] Figure 1 This is a structural diagram of the physical layer data frame of a broadband satellite communication system; Figure 2 This is a flowchart of typical signal processing at the receiving end; Figure 3 This is a flowchart of signal processing at the receiver of a broadband satellite communication system; Figure 4 The symbol rate is Waveforms of signal transmission at each channel sampling point of the ADC; Figure 5 The symbol rate is Waveforms of signal transmission at each channel sampling point of the ADC; Figure 6 The symbol rate is Waveforms of signal transmission at each channel sampling point of the ADC; Figure 7 This is a structural diagram of a parallel adaptive pre-synchronization device; Figure 8 This is a structural diagram of the parallel pre-synchronization module and the feedforward timing synchronization module; Figure 9 The symbol rate is Waveform of the sample points output by the time signal output unit; Figure 10 The symbol rate is Waveform of the sample points output by the time signal output unit; Figure 11 The symbol rate is Waveform of the sample points output by the time signal output unit; Figure 12 This is a flowchart of the feedforward timing synchronization module. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0022] The main characteristics of broadband satellite communication are large signal bandwidth, large short-term data volume, high requirements for receiver real-time processing capabilities, system complexity, and high hardware resource consumption. For broadband satellite communication systems to achieve stable communication over long periods, a high-performance timing synchronization strategy supporting large dynamic range is essential.

[0023] Typically, the physical layer data frame structure of a broadband satellite communication system mainly consists of pilot and data components.

[0024] Reference Figure 1A single signal frame has a total length of L symbols, including pilot signals and data. The pilot signal length is P, and the data length is D, so L = P + D. Pilot signals typically use pseudo-random sequences such as m-sequences, and common modulation methods are BPSK and π / 2-BPSK, often used for signal acquisition and frequency offset estimation. Broadband satellite communication systems can transmit physical layer data frames at different symbol rates. The data in these physical layer data frames uses different coding, modulation, and spread spectrum methods to support users in communicating at various information rates to suit different signal-to-noise ratio conditions.

[0025] The specific parameter settings for physical layer data frames are shown in Table 1.

[0026] Table 1 Physical Layer Data Frame Parameter Settings

[0027] The relationship between the symbol rate and the sampling rate is as follows: ; ; Sampling factor ≥4.

[0028] Reference Figure 2 The typical signal processing flow at the receiver is as follows: ADC sampling, matched filtering, timing synchronization, carrier synchronization, demodulation and decoding.

[0029] Reference Figure 3 The signal processing flow at the receiver of a broadband satellite communication system is as follows: ADC sampling, polyphase filtering, timing synchronization, carrier synchronization, demodulation and decoding.

[0030] In broadband satellite communication systems, the ADC performs analog-to-digital conversion and sampling filtering on the analog signals received from the antenna. Due to the high symbol rate, according to the sampling theorem, the sampling rate will be even higher. Since the received clock rate is lower than the sampling rate, the ADC needs to transmit signals in parallel.

[0031] In broadband satellite communication systems, timing synchronization strategies typically employ a feedback-based timing synchronization algorithm. This algorithm first performs symbol synchronization before proceeding to frame / bit synchronization. Specifically, it corrects and calculates multiple samples within a symbol acquired by the ADC to obtain a time deviation. Then, it recovers the input samples, continuing the correction calculation while simultaneously outputting an optimal sample for frame / bit synchronization according to certain rules. This process is repeated point by point until the starting position of frame synchronization is found.

[0032] In actual testing, the following problems were found with the commonly used feedback-based timed synchronization strategy: This timing synchronization strategy can only find the frame start position normally when the signal amplitude is stable. During long-term operation of the device, due to signal fluctuations, even slightly large fluctuations can cause the frame synchronization module to fail to find the frame start position. This is because the time deviation calculation in the feedback-based timing synchronization algorithm has a memory process. When the signal magnitude changes significantly, the time deviation calculation will have a large error, which accumulates over time and may far exceed the original time deviation value. This situation results in a very small dynamic range of signals supported by the device, which does not meet the needs of actual use. Because the timing synchronization strategy with feedback is a memory system, it is greatly affected by previous signals when correcting the best sample. Therefore, when the signal amplitude or frequency changes, the timing synchronization strategy with feedback will no longer be able to correct multiple samples within a symbol to the correct sample. This will cause the demodulator to be unable to find the frame start position and requires manual reset of the demodulator to operate normally, which will also reduce the convenience of using the equipment. Often, the accuracy of timing deviation calculations during timing synchronization is much lower than that of high-performance temperature-controlled clock chips due to limitations in algorithms and quantization during FPGA implementation. This results in a deterioration in the final timing synchronization performance. The ADC samples are not arranged in a fixed order. Assuming a feedforward timing synchronization scheme is used instead of a feedback-based timing synchronization strategy, if timing synchronization at different symbol rate levels uses all samples to search for the true optimal physical layer data sample position in parallel, it will consume a large amount of hardware resources. If a large amount of data is stored, the optimal sample position is directly extracted, and then the physical layer data frame start position is searched, a huge amount of hardware data storage space is required due to the large IQ data bit width, short bandwidth, and large data volume. If only a portion of the samples are extracted for timing synchronization, resource consumption can be effectively reduced, but the problem of not extracting the optimal sample may still occur.

[0033] To address the above issues, embodiments of this application provide a parallel adaptive pre-synchronization device.

[0034] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0035] Reference Figure 7 The parallel adaptive pre-synchronization device includes a sampling module, a filtering module, a parallel pre-synchronization module, a feedforward timing synchronization module, a carrier synchronization module, and a demodulation and decoding module.

[0036] The input of the sampling module is connected to the receiving antenna, and the output of the sampling module is connected to the filtering module. The output of the filtering module is connected to the input of the parallel pre-synchronization module. The sampling module is used to perform ADC sampling on the input signal of the device. The filtering module is used to perform polyphase filtering on the ADC-sampled signal. The output of the feedforward timing synchronization module is connected to the input of the carrier synchronization module, and the output of the carrier synchronization module is connected to the input of the demodulation and decoding module.

[0037] In this embodiment, the multiple parallel signals after ADC sampling and filtering enter the multiphase filtering process. The multiple parallel signals output by the multiphase filtering enter the pre-synchronization processing module. The parallel pre-synchronization module uses the corresponding processing strategy to extract the multiple parallel signals and enters the feedforward timing synchronization module to search for the optimal starting position of the physical layer data frame and outputs a physical layer data frame signal with the best sample point. After that, the signal is processed by carrier synchronization and demodulation decoding.

[0038] Reference Figure 4 , Figure 5 and Figure 6 Let the ADC clock be sys_clk, and its relationship with the symbol rate be... Consistent, ADC passed Each channel transmits the current signal samples in parallel to the FPGA for baseband signal processing. When the received signal symbol rate is... or At that time, ADC also through Each channel transmits signal samples. When the received signal symbol rate is... At that time, ADC's Each channel transmits one symbol under sys_clk. Sample points; when the received signal symbol rate is At that time, ADC's Each channel transmits one symbol under two sys_clk keys. Sample points; when the received signal symbol rate is At that time, ADC's Each channel transmits 1 symbol under four sys_clk keys. Sample points.

[0039] The actual hardware specifications of the device are as follows: the clock accuracy of the 10MHz clock reference source is ±10ppb, and the stability is less than 0.01ppb / s. Therefore, the calculated time offset range of this clock is -1. ns to 1 ns, the rate of change of time deviation is less than 1 When the actual clock frequency is 200MHz (5ns per clock cycle), the clock offset range is -2ns / s. ns to 2 ns, time deviation rate of change is less than 2 If the clock speed is ns / s, the clock offset is only 0.0004%, and the rate of change of the clock offset is just a tiny jitter value, which has minimal impact on the receiving system. However, commonly used timing synchronization tracking with feedback cannot achieve the clock accuracy of the clock chip, and since the clock offset only appears as jitter in actual use and does not accumulate, the timing offset error may accumulate due to correction errors during timing synchronization tracking, resulting in worse synchronization performance. Due to the sampling multiple... ≥4 is sufficient to fully satisfy the sampling theorem and the time offset is minimal. Therefore, considering the removal of the time offset calculation in the timing synchronization, a parallel pre-synchronization module is proposed. The feedforward timing synchronization scheme searches for the optimal starting position of the physical layer data frame in the extracted better sample points.

[0040] Reference Figure 8 The parallel pre-synchronization module includes a control calculation unit, a power calculation unit, a decision unit, a signal output unit, and a buffer.

[0041] The multi-channel parallel signals output by the multiphase filtering module serve as the initial input signals for the parallel pre-synchronization module.

[0042] The control calculation unit and signal output unit receive multiple parallel signals. The control calculation unit separates the calculation input signal from the multiple parallel signals according to the current decision parameters, and the signal output unit stores the multiple parallel signals into a buffer according to the current decision parameters. The power calculation unit calculates the signal power and sample location information based on the calculation input signal. The decision unit updates the decision parameters based on the comparison result of the signal power and the preset signal power. The signal output unit reads multiple candidate samples from the multiple parallel signals in the buffer according to the sample location information. The feedforward timing synchronization module selects the target sample based on the multiple candidate samples using a parallel synchronization algorithm. The main function of the parallel pre-synchronization module in the parallel pre-synchronization adaptive pre-synchronization scheme is to select several superior samples (e.g., four samples) from the ADC signal sampling points according to certain rules and send them in parallel to the feedforward timing synchronization. The proposed synchronization scheme uses a signal calculation mechanism, which mainly includes: start signal calculation time, signal calculation length, and signal calculation period. The start signal calculation time in the signal calculation mechanism mainly depends on three factors, two of which are external, including power-on startup and external reset, and one factor is internal to the decision-making unit.

[0043] The parallel pre-synchronization module starts working immediately upon power-on, with the start signal calculation time being the device's power-on moment. If a reset signal is provided externally during device operation, the start signal calculation time is updated to the reset end time. If the power of the signal transmitted by the power calculation unit is lower than the preset noise floor power of the decision unit, the start signal calculation time is updated to the power comparison end time. The parallel pre-synchronization module will re-enter the control calculation unit, power calculation unit, and decision unit into working state based on the start signal time flag.

[0044] In the signal calculation mechanism, the signal calculation length is determined by the decision unit based on the current operating scenario of the equipment, and then sent to the control calculation unit.

[0045] The signal calculation cycle is the calculation cycle after the equipment is operating normally; during the parallel pre-synchronization normal operation period, the signal calculation cycle is once. Because the symbol rate is... At this time, each symbol's sampling points are transmitted in parallel (4 points). Regardless of the order of the ADC sampling points, the optimal starting point position of the physical layer data frame can be found. Therefore, the symbol rate is... At this time, the signal can be directly sent to the feedforward timing synchronization module through the signal output unit. If the symbol rate is... When each symbol has more than 4 sampling points, the processing procedure is the same as that of other symbols.

[0046] For the control calculation unit, it mainly uses the calculation length information sent by the decision unit to separate the signal whose power needs to be calculated from the initial input signal of a certain length but different symbol rates according to certain rules. After the device is powered on, the parallel pre-synchronization module is in the working state by default. The control calculation unit separates the signal to be calculated from the initial input signal according to the start signal calculation time and signal calculation length parameters transmitted by the decision unit and sends it to the power calculation unit.

[0047] The decision parameters include the signal computation length parameter. Separating the computation input signal from the multi-channel parallel signals based on the current decision parameters specifically includes the following steps: grouping the multi-channel parallel signals according to the signal computation length parameter to separate the computation input signal; wherein, the number of groups is related to the symbol rate, and the number of sampling points within a group is related to the signal computation length parameter.

[0048] For example, based on different symbol rate sampling conditions, this module adjusts the symbol rate... and The signal is separated so that the power calculation unit can add the power of samples at the same location on different symbols. The reference symbol rate is... and The transmission status of signal sampling points in each channel of the ADC is as follows: signal separation is equivalent to grouping the ADC sampling points, with a symbol rate of... The sampling points can be divided into 8 groups, and the symbol rate is The sampling points can be divided into 16 groups, but for ease of implementation, they can be uniformly divided into 16 groups in the control calculation unit, namely: , ... Then the symbol rate is At that time, the positions of the first 8 groups and the last 8 groups of sample points are corresponding, and K represents the signal calculation length parameter input to the decision unit.

[0049] For the power calculation unit, the power calculation unit completes the power calculation of different grouped signals, and selects the optimal signal sample power and corresponding sample position information through a comparator, which are then input to the decision unit and the signal output unit respectively. After the grouped signals enter the power calculation unit, the power of each sample is first calculated by a multiplier, and then the power of each group of sample points is summed to obtain 16 groups of power values. This process uses pipelined computing processing in implementation.

[0050] The power calculation unit calculates the signal power and sample location information based on the calculation input signal, specifically including the following steps: calculating the first power of each sample point based on the calculation input signal, adding the first power of each group of sample points to obtain the second power; comparing multiple second powers to determine the signal power and the sample location information corresponding to the signal power.

[0051] For example, as shown by the grouping of sample points by the control computing unit, the unit uniformly divides the sample points into 16 groups, for a symbol rate of... At that time, the positions of the first 8 groups and the last 8 groups of samples correspond, meaning that the last 8 groups of data out of the 16 groups are the 8 samples of the next symbol. When the received signal symbol rate is... At that time, ADC's Each channel transmits one symbol under two sys_clk keys. Sample points; when the received signal symbol rate is At that time, ADC's Each channel transmits 1 symbol under four sys_clk keys. Sample points. Therefore, at a received signal symbol rate of... At that time, the power calculation unit adds the first 8 power values ​​to the last 8 power values, then divides the 8 power values ​​into two groups and uses a first-stage comparator to extract the 4 larger power values ​​and the corresponding sample point location information; when the received signal symbol rate is At that time, the power calculation unit divides the 16 power values ​​into 4 groups, uses a two-stage comparator to extract the 4 larger power values ​​and their corresponding sample location information. Then, the power calculation unit sends the optimal power value and its corresponding sample location information to the decision unit and signal output unit for further processing.

[0052] For the decision-making unit, the decision-making unit mainly implements some signal mechanism functions and transmits the start signal calculation time and signal calculation length to the control calculation unit.

[0053] The decision unit compares the signal power of the four sets of superior signals output by the power calculation unit with the preset noise floor level to determine whether the control calculation unit should restart the pre-synchronization process.

[0054] When the device is initially powered on, there is no valid input signal and only noise. Or, during the operation of the device, there is no valid signal and only noise for a period of time. The decision unit monitors the changes of multiple parallel signals and automatically updates the signal calculation time parameters to keep the pre-synchronization module in an effective working state.

[0055] When the device is powered on, the signal calculation time parameter is set to the device power-on time; when an externally sent reset signal is received, the signal calculation time parameter is set to the reset end time; when the comparison result between the signal power and the preset signal power is that the signal power is less than the preset signal power, the signal calculation time parameter is set to the power comparison end time.

[0056] The signal output unit primarily buffers the initial input signal and outputs it to the feedforward timing synchronization module according to certain rules. Based on the signal calculation length parameter transmitted by the decision unit, the signal output unit buffers multiple parallel signals. The buffer size is determined by the signal calculation length parameter and the bit width of the multiple parallel signals. Four parallel input signals are used, with four buffers. After storing the signal calculation length of data, data can be read from the buffers.

[0057] The signal output unit selects points from the read data based on the optimal sample point location information output by the power calculation unit, and outputs them in parallel to the feedforward timing synchronization module. (Refer to...) Figure 9 , Figure 10 and Figure 11 , Figure 9 The symbol rate is Waveform of the sample points output by the time signal output unit; Figure 10 The symbol rate is Waveform of the sample points output by the time signal output unit; Figure 11 The symbol rate is The waveform of the output sample points of the time signal output unit.

[0058] Reference Figure 12For the feedforward timing module, its main function is to search for the optimal starting position of the physical layer data frame. The feedforward timing module selects a target sample point from multiple candidate samples using a parallel synchronization algorithm. Specifically, this involves the following steps: calculating the relevant peak value based on the candidate samples and the local pilot sequence; calculating the average power based on the candidate samples; comparing the peak-to-average power ratio (PAPR) of the relevant peak value and the average power with a preset threshold to determine the synchronization position; and selecting the candidate sample point with the largest PAPR that is also greater than the preset threshold as the target sample point. The feedforward timing synchronization module determines the position of the target sample point as the starting position of the physical layer data frame and outputs the physical layer data frame based on this starting position.

[0059] The parallel adaptive pre-synchronization device is a memoryless system that can adapt to signal fluctuations, greatly improving the dynamic range of the signals supported by the device. Furthermore, the parallel pre-synchronization module monitors the signal in real time, eliminating the need for manual reset when the signal reception frequency or amplitude changes, making the device more convenient to use. By selecting superior samples through the parallel pre-synchronization module, the feedforward timing module can then select the best sample from among these superior samples, avoiding the problem of clock error correction exceeding clock accuracy. Compared to feedback-based timing synchronization schemes, it offers better synchronization performance. It is suitable for situations where the ADC samples are not arranged in a fixed order; the initial input signal does not need to be entirely sent to the feedforward timing synchronization module. Instead, it can first pass through the parallel pre-synchronization module to extract some superior samples, and then simultaneously find the best sample and the physical layer data frame position from among these superior samples, effectively improving synchronization performance and reducing resource consumption.

[0060] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A parallel adaptive pre-synchronization device, characterized in that, Includes a parallel pre-synchronization module and a feedforward timing synchronization module; The parallel pre-synchronization module includes a control calculation unit, a power calculation unit, a decision-making unit, a signal output unit, and a buffer; The control calculation unit and the signal output unit receive multiple parallel signals. The control calculation unit separates the calculation input signal from the multiple parallel signals according to the current decision parameters. The signal output unit stores the multiple parallel signals into the buffer according to the current decision parameters. The power calculation unit calculates the signal power and sample point location information based on the calculation input signal; The decision unit updates the decision parameters based on the comparison result between the signal power and the preset signal power; The signal output unit reads multiple candidate sample points from the multi-channel parallel signal in the buffer according to the sample point position information; The feedforward timing synchronization module selects the target sample point based on multiple candidate sample points using a parallel synchronization algorithm. The decision parameters include a signal computation length parameter; separating the computation input signal from the multi-parallel signals based on the current decision parameters includes: The multi-channel parallel signals are grouped according to the signal calculation length parameter to separate the calculation input signal. The number of groups is related to the symbol rate, and the number of sampling points in the group is related to the signal calculation length parameter. The target sample point is selected based on multiple candidate sample points using a parallel synchronization algorithm, including: The relevant peak values ​​are calculated based on the candidate sample points and the local pilot sequence. The average power is calculated based on the candidate sample points; Compare the peak-to-average power ratio (PAPR) of the relevant peak power with the average power and the preset threshold. Candidate sample points with the largest peak-to-average ratio (PAR) and PAR greater than a preset threshold are selected as target sample points.

2. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, The signal power and sample location information are calculated based on the input signal, including: The first power of each sample point is calculated based on the input signal, and the second power is obtained by adding the first power of each set of sample points. The signal power and the corresponding sample location information are determined by comparing multiple second powers.

3. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, When the device is powered on or in operation, the input signal of the device has no valid signal and only noise. The decision unit updates the signal calculation time parameter according to the changes of the multiple parallel signals.

4. The parallel adaptive pre-synchronization device according to claim 3, characterized in that, When the device is powered on, the signal calculation time parameter is set to the device power-on time; when a reset signal is received from an external source, the signal calculation time parameter is set to the reset end time; when the comparison result between the signal power and the preset signal power is that the signal power is less than the preset signal power, the signal calculation time parameter is set to the power comparison end time.

5. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, The decision parameters include a signal calculation length parameter; storing the multi-channel parallel signals into the buffer according to the current decision parameters includes: The multiple parallel signals are stored in the buffer, and the buffer size is determined by the signal calculation length parameter and the bit width of the multiple parallel signals.

6. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, The feedforward timing synchronization module determines the position of the target sample point as the starting position of the physical layer data frame, and outputs the physical layer data frame according to the starting position of the physical layer data frame.

7. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, The device also includes a sampling module and a filtering module. The input terminal of the sampling module is connected to the receiving antenna, the output terminal of the sampling module is connected to the filtering module, and the output terminal of the filtering module is connected to the input terminal of the parallel pre-synchronization module. The sampling module is used to perform ADC sampling on the input signal of the device, and the filtering module is used to perform polyphase filtering on the ADC-sampled signal.

8. The parallel adaptive pre-synchronization device according to claim 1, characterized in that, The device also includes a carrier synchronization module and a demodulation decoding module. The output of the feedforward timing synchronization module is connected to the input of the carrier synchronization module, and the output of the carrier synchronization module is connected to the input of the demodulation decoding module.

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