Circuit netlist optimization method and computer program product

Abstract

The application provides a circuit netlist optimization method and a computer program product, and relates to the technical field of circuit design automation. The method comprises the following steps: preprocessing an original circuit netlist to generate a netlist directed graph model; generating a subgraph candidate set based on the netlist directed graph model; identifying each subgraph in the subgraph candidate set to obtain an equivalent subgraph group; and reconstructing the original circuit netlist according to the equivalent subgraph group to generate an optimized circuit netlist. According to the application, the equivalent subgraph group is determined according to the directed graph model of the original netlist, the netlist is reconstructed based on the equivalent subgraph group, the original netlist is optimized, the comprehensiveness of equivalent subgraph identification is improved, and therefore, the redundancy of the netlist is effectively reduced, and the chip area and power consumption are optimized.

Description

Technical Field

[0001] This application relates to the field of circuit design automation technology, and more specifically, to a circuit netlist optimization method and computer program product. Background Technology

[0002] In the circuit design process, the netlist is the core carrier connecting the front-end logic design and the back-end physical implementation. The simplicity and regularity of the netlist directly affect the efficiency of subsequent placement and routing, chip area, and power consumption. One of the core goals of netlist optimization is to reduce redundant logic and lower design complexity by merging functionally equivalent cells or subgraphs.

[0003] Existing netlist cell merging techniques are mainly based on acyclic graph structure design and rely on the topological sorting of subgraphs for equivalence judgment. However, this method has the problem of incomplete identification of equivalent subgraphs, making it difficult to effectively optimize the netlist of actual circuits. Summary of the Invention

[0004] The purpose of this application is to provide a circuit netlist optimization method and computer program product, which determines equivalent subgraph groups based on the directed graph model of the original netlist, reconstructs the netlist based on the equivalent subgraph groups, and optimizes the original netlist. In this process, the comprehensiveness of equivalent subgraph identification is improved, thereby effectively reducing redundant units in the netlist and optimizing chip area and power consumption.

[0005] In a first aspect, embodiments of this application provide a circuit netlist optimization method, which includes: preprocessing the original circuit netlist to generate a directed graph model of the netlist; generating a subgraph candidate set based on the directed graph model of the netlist; identifying each subgraph in the subgraph candidate set to obtain an equivalent subgraph group; and reconstructing the original circuit netlist according to the equivalent subgraph group to generate an optimized circuit netlist.

[0006] In this embodiment, the original circuit netlist is preprocessed to obtain a directed graph model of the netlist. A candidate set of subgraphs is generated based on this model. Then, each subgraph in the candidate set is identified to obtain an equivalent subgraph group. The original circuit netlist is then reconstructed based on this equivalent subgraph group. In this process, the candidate set of subgraphs is first generated based on the directed graph model of the netlist, and then the equivalent subgraph group is identified from the candidate set, improving the comprehensiveness of equivalent subgraph identification. Based on this, the reconstruction and optimization of the original circuit netlist using the equivalent subgraph group effectively reduces redundant netlist cells, achieving the goal of optimizing chip area and power consumption.

[0007] In some embodiments, the subgraph includes multi-dimensional features; identifying each subgraph in the candidate subgraph set to obtain an equivalent subgraph group includes: generating a feature fingerprint of the corresponding subgraph based on the multi-dimensional features; grouping the subgraphs using the feature fingerprint to obtain an equivalent candidate group; and performing equivalence verification on the subgraphs in the equivalent candidate group to obtain an equivalent subgraph group.

[0008] In this embodiment, when identifying each subgraph in the candidate subgraph set to obtain an equivalent subgraph group, a corresponding feature fingerprint is first generated based on the multi-dimensional features of the subgraph. Then, the subgraphs are grouped based on the feature fingerprint to obtain an equivalent candidate group. Finally, the subgraphs in the equivalent candidate group are subjected to equivalence verification to obtain an equivalent subgraph group. In this process, because the feature fingerprint is unique, obviously inequivalent subgraphs can be quickly isolated, reducing the computational load of subsequent equivalence verification and significantly improving the identification efficiency and comprehensiveness of equivalent subgraphs.

[0009] In some embodiments, performing equivalence verification on subgraphs in the equivalence candidate group to obtain an equivalence subgraph group includes: performing ring structure equivalence verification on each subgraph in the equivalence candidate group to obtain a ring structure equivalence subgraph group; and performing input signal equivalence verification on each subgraph in the ring structure equivalence subgraph group to obtain an equivalence subgraph group.

[0010] In this embodiment, considering that in actual circuit design, due to requirements such as feedback control logic and state machine design, loop graph structures inevitably exist in the netlist, when performing equivalence verification on each subgraph in the equivalence candidate group, loop structure equivalence verification is first performed on each subgraph in the equivalence candidate group to obtain a group of loop structure equivalent subgraphs. Then, considering that the probability of input signal equivalence in circuit design is the lowest, input signal equivalence verification is finally performed on the group of loop structure equivalent subgraphs to obtain an equivalent subgraph group. In this process, the number of subgraphs that need to be verified for equivalence is reduced step by step in a progressive manner, which not only improves the comprehensiveness of subgraph recognition but also improves recognition efficiency.

[0011] In some embodiments, performing ring structure equivalence verification on each subgraph in the equivalence candidate group to obtain a ring structure equivalent subgraph group includes: using a ring structure feature library to perform ring feature verification on subgraphs containing ring structures; wherein, the ring structure feature library is generated based on a netlist directed graph model; if it is determined that there are multiple first target subgraphs with consistent ring types, consistent ring topology features, and consistent ring nesting relationships among the subgraphs containing ring structures, then a ring structure equivalent subgraph group is obtained based on the multiple first target subgraphs.

[0012] In this embodiment of the application, when performing ring structure equivalence verification on each subgraph in the equivalent candidate group, the ring structure feature library is used to perform ring feature verification on the subgraph. In this process, the ring structure equivalence of the subgraph is determined by verifying whether the ring type, ring topology features and ring nesting relationship are consistent, which improves the accuracy of ring structure equivalence verification and thus improves the comprehensiveness of the identification of equivalent subgraphs.

[0013] In some embodiments, input signal equivalence verification is performed on each subgraph in the ring structure equivalent subgraph group to obtain the equivalent subgraph group, including: if it is determined that there are multiple second target subgraphs in the ring structure equivalent subgraph group that have consistent input signal sources and consistent input signal timing relationships, then the equivalent subgraph group is obtained based on the multiple second target subgraphs.

[0014] In this embodiment, input signal equivalence verification is performed on each subgraph in the ring structure equivalent subgraph group, which further improves the comprehensiveness of the identification of equivalent subgraphs.

[0015] In some embodiments, the multi-dimensional features include unit type combination features, input / output port features, ring structure features, and logical function expressions. Based on the multi-dimensional features, the feature fingerprint of the corresponding subgraph is generated, including: normalizing the unit type combination features, input / output port features, ring structure features, and logical function expressions respectively to obtain standard unit type combination features, standard input / output port features, standard ring structure features, and standard logical function expressions; and using a hash algorithm, generating the feature fingerprint of the subgraph based on the standard unit type combination features, standard input / output port features, standard ring structure features, and standard logical function expressions.

[0016] In this embodiment, by normalizing the multi-dimensional features, the differences in dimensions and order between feature dimensions are eliminated, thereby improving the accuracy of feature fingerprints and laying a solid foundation for equivalent subgraph recognition.

[0017] In some embodiments, reconstructing the original circuit netlist based on the equivalent subgraph group to generate an optimized circuit netlist includes: performing a merge constraint check on each subgraph in the equivalent subgraph group; merging the equivalent subgraphs that pass the merge constraint check to reconstruct the original circuit netlist and generate an optimized circuit netlist.

[0018] In this embodiment of the application, when reconstructing the original circuit netlist based on the equivalent subgraph group, a merging constraint check is performed on each subgraph in the equivalent subgraph group to ensure that the merging operation does not violate the circuit physical design rules and timing requirements, thereby improving the accuracy of the optimized circuit netlist.

[0019] In some embodiments, a merge constraint check is performed on each subgraph in the equivalent subgraph group, including: a fan-out quantity constraint check, a timing constraint check, and a ring structure integrity constraint check on each subgraph in the equivalent subgraph group.

[0020] In this embodiment, by performing fan-out quantity constraint checks, timing constraint checks, and ring structure integrity constraint checks on each subgraph, the merging operation is ensured to not violate the circuit physical design rules and timing requirements, thereby improving the accuracy of the optimized circuit netlist.

[0021] In some embodiments, where the equivalent subgraphs include ring types; merging equivalent subgraphs that pass the merge constraint check to reconstruct the original circuit netlist and generate an optimized circuit netlist includes: determining a target merge strategy based on the ring type; and merging equivalent subgraphs that pass the merge constraint check based on the target merge strategy to reconstruct the original circuit netlist and generate an optimized circuit netlist.

[0022] In this embodiment, a target merging strategy is determined based on the ring type. The target merging strategy is then used to merge equivalent subgraphs that have passed the merging constraint check, thereby improving the accuracy of the merging and thus improving the accuracy of the optimized circuit netlist.

[0023] In some embodiments, the netlist directed graph model includes multiple nodes and directed edges connecting the nodes; based on the netlist directed graph model, generating a subgraph candidate set includes: taking each node as a starting point, determining a first adjacent node directly connected to the starting point according to the directed edges; wherein the starting point and the first adjacent node constitute a minimum subgraph; taking the first adjacent node as a new starting point, adding a second adjacent node directly connected to the first adjacent node into the minimum subgraph according to a preset expansion rule and directed edges, generating a new subgraph; taking the second adjacent node as a new starting point, gradually adding new adjacent nodes to the new subgraph according to a preset expansion rule until the new subgraph meets the preset subgraph requirements, generating a subgraph candidate set.

[0024] In this embodiment, each node is taken as the starting point and expanded using preset expansion rules to generate a candidate set of subgraphs, thereby covering all possible equivalent subgraphs in the netlist and laying a solid foundation for the subsequent identification of equivalent subgraphs.

[0025] In some embodiments, after reconstructing the original circuit netlist based on the equivalent subgraph set to generate an optimized circuit netlist, the method further includes: if it is determined that there is no equivalent subgraph in the directed graph model formed by the optimized circuit netlist, or the number of iterations reaches a preset number of iterations, then the optimized circuit netlist is used as the target circuit netlist for simulation verification, and a verification report is generated; otherwise, the optimized circuit netlist is preprocessed to generate a new netlist directed graph model, and a new optimized circuit netlist is generated based on the new netlist directed graph model, until there is no equivalent subgraph in the directed graph model formed by the new optimized circuit netlist, or the number of iterations reaches a preset number of iterations, a new optimized circuit netlist is output, and the new optimized circuit netlist is simulated and verified, and a verification report is generated.

[0026] In this embodiment, after generating the optimized circuit netlist, iterative optimization is performed, and the final generated circuit netlist is simulated and verified, which further improves the accuracy and functional consistency of the optimized circuit netlist.

[0027] In a second aspect, embodiments of this application provide an electronic device, including: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and the machine-readable instructions, when executed by the processor, are capable of performing the method steps of any embodiment of the first aspect.

[0028] Thirdly, embodiments of this application provide a computer-readable storage medium, including: computer program instructions stored on the computer-readable storage medium, wherein the computer program instructions are executed by a processor to perform the method steps of any embodiment of the first aspect.

[0029] Fourthly, embodiments of this application provide a computer program product, including: computer program instructions, which are executed by a processor to perform the method steps of any embodiment of the first aspect.

[0030] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic flowchart illustrating a circuit netlist optimization method provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram illustrating three types of rings as shown in the embodiments of this application;

[0034] Figure 3 A schematic diagram of a directed graph model of a circuit netlist provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the electronic device structure provided in an embodiment of this application. Detailed Implementation

[0036] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0037] It should be noted that all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0038] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0039] In the circuit design process, the netlist is the core carrier connecting the front-end logic design and the back-end physical implementation. The simplicity and regularity of the netlist directly affect the efficiency of subsequent placement and routing, chip area, and power consumption. One of the core goals of netlist optimization is to reduce redundant logic and lower design complexity by merging functionally equivalent cells or subgraphs.

[0040] Existing netlist cell merging techniques are primarily based on acyclic graph structures, relying on the topological sorting of subgraphs for equivalence determination. This method heavily depends on layer-by-layer consistency from the original input; if unmerged redundancies exist at lower levels, equivalent subgraphs at higher levels will also fail to be identified. Furthermore, this method cannot handle scenarios with cyclic graphs, and therefore cannot identify equivalent subgraphs containing cyclic graphs.

[0041] Therefore, existing technologies suffer from incomplete identification of equivalence subgraphs, making it difficult to effectively optimize actual circuit netlists.

[0042] To address this issue, this application provides a circuit netlist optimization method and computer program product, which determines equivalent subgraph groups based on the directed graph model of the original netlist, reconstructs the netlist based on the equivalent subgraph groups, optimizes the original netlist, improves the comprehensiveness of equivalent subgraph identification, thereby effectively reducing redundant netlist cells and optimizing chip area and power consumption.

[0043] Figure 1 This is a flowchart illustrating a circuit netlist optimization method provided in an embodiment of this application. It is understood that the circuit netlist optimization method provided in this embodiment can be applied to terminal devices (also known as electronic devices) and servers; the terminal device can specifically be a smartphone, tablet computer, computer, personal digital assistant (PDA), etc.; the server can specifically be an application server or a web server. To facilitate understanding of the technical solution provided in this embodiment, the application scenarios of the circuit netlist optimization method provided in this embodiment will be introduced below using a server as the execution subject as an example.

[0044] like Figure 1 As shown, the method includes:

[0045] Step S101: Preprocess the original circuit netlist to generate a directed graph model of the netlist.

[0046] The core elements of a circuit netlist include:

[0047] (1) Cell: The basic functional unit of a circuit, such as logic gates (AND, OR, NOT, etc.), registers (Flip-flop), macro modules (RAM, CPU core, etc.).

[0048] (2) Port (Pin): The input / output interface of the unit.

[0049] (3) Network: A wire that connects multiple unit ports, representing the electrical connection relationship.

[0050] In the above implementation process, the original circuit netlist format supports mainstream industry standards (such as Verilog, EDIF, etc.), and a dedicated parser performs line-by-line scanning and syntax analysis of the original circuit netlist content. Specifically:

[0051] (1) Unit identification: Extract the type (such as logic gate, register, flip-flop, etc.), ID and internal parameters (such as driving capability, delay parameters, etc.) of the basic functional units of the circuit.

[0052] (2) Port identification: Distinguish between input ports (such as clk, rst, data_in, etc.), output ports (such as data_out, etc.) and bidirectional ports of the circuit netlist, and record the port's direction, bit width and other attributes.

[0053] (3) Signal connection relationship analysis: sort out the signal transmission path between units and between units and ports, clarify the source node (signal sending end) and target node (signal receiving end) of each signal, and establish the mapping relationship between signals and nodes.

[0054] Based on the above analysis results, a directed graph model of the original circuit netlist is constructed. In this directed graph model, cells and ports are used as nodes, and signal transmission paths are used as directed edges, with the edge direction consistent with the signal flow direction. Attribute labels are added to each node and edge. Node attribute labels include node type, ID, parameters, etc., while edge attribute labels include signal name, transmission delay, etc.

[0055] Therefore, the directed graph model of a netlist is a data structure that abstracts a circuit netlist into a directed graph.

[0056] After generating the directed graph model of the netlist, considering that in actual circuit design, due to requirements such as feedback control logic and state machine design, the circuit netlist inevitably contains cyclic graph structures. The above-mentioned structure design based on acyclic graphs cannot handle scenarios with cyclic graphs, and therefore cannot identify equivalent subgraphs containing cyclic graphs.

[0057] Therefore, before performing equivalence subgraph recognition, the loop structure detection and extraction of the directed graph model of the netlist are performed to obtain the loop structure feature library of the circuit netlist.

[0058] In one implementation, a depth-first search algorithm is used to traverse the directed graph model of the netlist to achieve efficient detection of loop structures. The specific process is as follows:

[0059] (1) Starting from each node, perform a depth-first traversal along the directed edges and record the node sequence on the traversal path.

[0060] (2) When a node that already exists in the current path is encountered during the traversal, it is determined that a cycle structure is formed, and the sub-path from the repeated node to itself in the path is extracted as the node set and edge set of the cycle.

[0061] (3) To avoid repeated detection of the loop structure, the confirmed loop points are marked. If the node is encountered again during subsequent traversal and no new loop path is entered, the depth traversal of the node is skipped to improve detection efficiency.

[0062] To further understand the ring structure in the circuit netlist, the extracted ring structures are classified according to their topological characteristics and functional attributes. The specific classification criteria and labeling rules are as follows:

[0063] (1) Self-loop: A loop formed by a single node pointing to itself through directed edges is marked as "LOOP_SELF". For example, the output of a trigger is directly connected to its own input, forming a self-loop structure, which records the node ID and the attribute information of the edges.

[0064] (2) Simple cycle: A closed path formed by connecting n (n≥2) different nodes sequentially through directed edges, where the starting and ending nodes coincide and there are no other duplicate nodes. It is marked as "LOOP_SIMPLE-n" (where n is the number of nodes in the cycle). For example, node A→node B→node C→node A forms a 3-node simple cycle, marked as "LOOP_SIMPLE-3".

[0065] (3) Nested rings: All nodes of a ring are contained in the set of nodes of another larger ring, forming a hierarchical nested relationship, marked as "LOOP_NESTED-k" (k is the nesting level). For example, if the inner ring is node A→B→A (a simple ring with 2 nodes) and the outer ring is node A→B→C→A (a simple ring with 3 nodes), then the inner ring is marked as "LOOP_NESTED-1" and the outer ring is marked as "LOOP_NESTED-2".

[0066] Figure 2 The diagram shows three types of rings given in the embodiments of this application, where (a) is a self-loop, (b) is a simple loop, and (c) is a nested loop.

[0067] Each ring structure is assigned a unique ring ID. The ring type label, ring ID, node set, edge set, and ring depth (the number of nodes in the longest path in the ring, with a self-loop depth of 1, a simple ring depth of n, and a nested ring depth equal to the number of nodes in the outer ring) are stored in the ring structure feature library. At the same time, corresponding ring tags are added to the nodes and edges within the ring in the directed graph model of the netlist to facilitate subsequent subgraph feature extraction and equivalence verification.

[0068] For scenarios where nested loops may exist in complex circuit netlists, when detecting a loop structure, the traversal is not interrupted after a loop is detected. Instead, the path is backtracked to check if there is a larger loop structure containing the loop, ensuring that loop structures at all levels are completely captured.

[0069] It should be noted that when detecting and extracting loop structures in a directed graph model of a netlist, a breadth-first search algorithm can also be used. The specific method for detecting loop structures can be selected according to the actual scenario, and this application does not impose any specific limitations on it.

[0070] Through the above preprocessing, the directed graph model file of the netlist and the feature library file of the ring structure are obtained.

[0071] The directed graph model file contains node attributes, edge attributes, and cycle labeling information, supporting visualization and subsequent traversal analysis. The cycle structure feature library file records the classification, ID, node set, edge set, depth, and other feature information of all cycles in tabular form, providing a data query interface for subsequent steps.

[0072] Step S102: Generate a candidate set of subgraphs based on the directed graph model of the netlist.

[0073] In the above implementation process, for the directed graph model of the netlist, the candidate set of subgraphs is generated by the method of "bottom-up (from output to input) + sliding window" or "top-down (from input to output) + sliding window" to ensure that all possible equivalent subgraphs in the circuit netlist are covered.

[0074] A candidate subgraph set refers to the set of subgraphs in a directed graph model that satisfy predefined constraints.

[0075] In one implementation, a candidate set of subgraphs is generated using a bottom-up (from output to input) + sliding window approach, specifically:

[0076] (1) Window size definition: The number of nodes in the subgraph window ranges from 2 to 20 (which can be adaptively adjusted according to the size of the circuit netlist; the upper limit of the window can be increased when the size of the circuit netlist is large). The window starts from a single node and gradually expands to its predecessor node (signal input terminal).

[0077] (2) Expansion rules: Starting from each node, first include the node and its directly connected input node to form a minimum subgraph (2 nodes). Based on the minimum subgraph, for newly added input nodes, according to the preset expansion rules, add the directly connected adjacent nodes to the subgraph, thereby gradually expanding the subgraph window until the upper limit of the window size is reached or the circuit netlist input port is traversed.

[0078] The preset expansion rules can be set according to the actual situation. For example, each expansion may add only 1 node, or add 2 nodes each time, or add all adjacent nodes of the node to be expanded.

[0079] (3) Deduplication: The generated candidate set of subgraphs is deduplicated. If the node sets of two subgraphs are completely identical and the edge connection relationships are the same, they are considered as the same subgraph, and only one copy is kept to avoid duplicate calculation.

[0080] Based on the above, in some embodiments, the netlist directed graph model includes multiple nodes and directed edges connecting the nodes; generating a subgraph candidate set based on the netlist directed graph model includes: taking each node as the starting point, determining a first adjacent node directly connected to the starting point according to the directed edges; wherein the starting point and the first adjacent node constitute a minimum subgraph; taking the first adjacent node as a new starting point, adding a second adjacent node directly connected to the first adjacent node into the minimum subgraph according to a preset expansion rule and directed edges, generating a new subgraph; taking the second adjacent node as a new starting point, gradually adding new adjacent nodes to the new subgraph according to a preset expansion rule until the new subgraph meets the preset subgraph requirements, generating a subgraph candidate set.

[0081] The preset subgraph requirement is to "reach the upper limit of the window size or traverse to the input port of the circuit netlist".

[0082] In this process, each node is taken as the starting point and expanded using preset expansion rules to generate a candidate set of subgraphs, thereby covering all possible equivalent subgraphs in the netlist and laying a solid foundation for the subsequent identification of equivalent subgraphs.

[0083] To further understand the process of generating the candidate subgraph set, the following example is provided:

[0084] Figure 3 This application provides a schematic diagram of a directed graph model of a circuit netlist, for the purpose of illustrating this application. Figure 3 Taking nodes 7 and 8 in the circuit netlist as an example (bottom-up + sliding window), the subgraph expansion process is as follows:

[0085] (1) Minimum subgraph window (2 nodes): Node 7 and its direct input node 5 form subgraph G7-1={7,5}; Node 8 and its direct input node 6 form subgraph G8-1={8,6}.

[0086] (2) First expansion (4 nodes): G7-1 expansion includes the input nodes 2 and 3 of node 5, forming the subgraph G7-2={7,5,2,3} (the number of nodes here is 4, because node 5 has two input nodes, and the window size after expansion is 4); G8-1 expansion includes the input nodes 2 and 4 of node 6, forming the subgraph G8-2={8,6,2,4} (the number of nodes here is 4, because node 6 has two input nodes, and the window size after expansion is 4).

[0087] (3) Second expansion (5 nodes): The G7-2 expansion includes the input node 1 and node 7 of node 3. Since node 7 is a node related to the ring structure and already exists in G7-2, it is not added at this time. The final subgraph G7-3={7,5,2,3,1} is formed. G7-3 contains a simple 3-node ring (3→5→7→3). The G8-2 expansion includes the input node 1 and node 8 of node 4. Since node 8 is a node related to the ring structure and already exists in G8-2, it is not added at this time. The subgraph G8-3={8,6,2,4,1} is formed. G8-3 contains a simple 3-node ring (4→6→8→4).

[0088] After two expansions, a candidate set of subgraphs {G7-3, G8-3} is obtained, which includes two subgraphs, namely subgraph G7-3 and subgraph G8-3.

[0089] In one implementation, the subgraph candidate set can also be generated using a "top-down (from input to output) + sliding window" approach. It should be understood that the process of generating the subgraph candidate set using the "top-down (from input to output) + sliding window" approach is the same as the example above, except that the window starts from a single node and gradually expands towards its successor nodes (signal output terminals). The smallest subgraph includes the starting point and one directly connected output node. The preset requirement for the subgraph is "reaching the upper limit of the window size or traversing to the output port of the circuit netlist."

[0090] In one implementation, a subgraph candidate set can also be generated in a manner that involves "simultaneous forward and backward expansion + sliding window".

[0091] Step S103: Identify each subgraph in the subgraph candidate set to obtain an equivalent subgraph group.

[0092] Step S104: Based on the equivalent subgraph group, reconstruct the original circuit netlist to generate an optimized circuit netlist.

[0093] After obtaining the candidate set of subgraphs, each subgraph in the candidate set is identified to obtain an equivalent subgraph group.

[0094] An equivalent subplot is a set of subplots in a circuit netlist that are equivalent to each other in terms of function, structure, and specific attributes.

[0095] After obtaining the equivalent subgraph set, the original circuit netlist is reconstructed to generate an optimized circuit netlist.

[0096] In this embodiment, the original circuit netlist is preprocessed to obtain a directed graph model of the netlist. A candidate set of subgraphs is generated based on this model. Then, each subgraph in the candidate set is identified to obtain an equivalent subgraph group. The original circuit netlist is then reconstructed based on this equivalent subgraph group. In this process, the candidate set of subgraphs is first generated based on the directed graph model of the netlist, and then the equivalent subgraph group is identified from the candidate set, improving the comprehensiveness of equivalent subgraph identification. Based on this, the reconstruction and optimization of the original circuit netlist using the equivalent subgraph group effectively reduces redundant netlist cells, achieving the goal of optimizing chip area and power consumption.

[0097] In some embodiments, the subgraph includes multi-dimensional features; identifying each subgraph in the candidate subgraph set to obtain an equivalent subgraph group includes: generating a feature fingerprint of the corresponding subgraph based on the multi-dimensional features; grouping the subgraphs using the feature fingerprint to obtain an equivalent candidate group; and performing equivalence verification on the subgraphs in the equivalent candidate group to obtain an equivalent subgraph group.

[0098] In the above implementation process, multi-dimensional features include unit type combination features, input and output port features, ring structure features, and logical function expressions.

[0099] In some embodiments, generating feature fingerprints of corresponding subgraphs based on multi-dimensional features includes: normalizing the unit type combination features, input / output port features, ring structure features, and logical function expressions respectively to obtain standard unit type combination features, standard input / output port features, standard ring structure features, and standard logical function expressions; and generating feature fingerprints of subgraphs based on the standard unit type combination features, standard input / output port features, standard ring structure features, and standard logical function expressions using a hash algorithm.

[0100] In the above implementation process, the specific extraction rules for each feature are as follows:

[0101] (1) Unit type combination characteristics: Record the types of all units according to the topological order of the nodes in the subgraph (which can be from input to output or from output to input) to form a type sequence. For example, taking the topological order from output to input as an example, if subgraph G7-3 contains units CELL2 (node ​​7), CELL1 (node ​​5), and AND2 (node ​​3), then the type combination is [CELL2, CELL1, AND2].

[0102] (2) Input and output port characteristics: The number of input ports, the number of output ports, the port bit width and the signal type of the statistical subgraph are used to form a feature group. For example, the input port of G7-3 is node 1 (bit width 1, digital signal), the number of input ports is 1, the output port is node 7 (bit width 1, digital signal), the number of output ports is 1, and the feature group is [number of inputs: 1, number of outputs: 1, input bit width: 1, output bit width: 1, signal type: digital].

[0103] (3) Ring structure features: If the subgraph contains a ring structure, query the corresponding ring type label, ring depth and number of nodes from the ring structure feature library to form a ring feature group. For example, G7-3 contains a "LOOP_SIMPLE-3" ring, with a ring depth of 3 and a number of nodes of 3. The ring feature group is [Ring type: LOOP_SIMPLE-3, Ring depth: 3, Number of nodes: 3]; if the subgraph does not have a ring structure, the ring feature group is [Ring type: NONE, Ring depth: 0, Number of nodes: 0].

[0104] (4) Logical function expression: Based on the logical function and signal connection relationship of the cells in the subgraph, derive the input-output mapping expression of the subgraph. For example, in subgraph G7-3, the signal of node 1 is in1, the signal of node 2 is in2, the output of node 3 (AND2) is in1&out7, the output of node 5 (CELL1) is the result of (in1&out7, in2) after CELL1 logic processing, and the output of node 7 (CELL2) is the result of CELL1 output after CELL2 logic processing. The final logical function expression is out7=CELL2(CELL1(in1&out7,in2)) (assuming CELL1 is a dual-input cell).

[0105] To eliminate the influence of dimensional differences and order among feature dimensions, the extracted feature vectors are normalized:

[0106] (1) Normalization of unit type combinations: Sort the units by lexicographical order to ensure that the characteristics of subgraphs with the same type combination but different order are consistent. For example, the type combination [CELL1,CELL2] and [CELL2,CELL1] are normalized to [CELL1,CELL2].

[0107] (2) Normalization of input and output port features: Convert numerical features such as the number of ports and bit width into standardized values. For example, the conversion is performed using the formula x'=(x-min) / (max-min), where min is the minimum value of the feature, max is the maximum value, x is the feature value to be converted, and x' is the normalized feature value.

[0108] (3) Normalization of ring structure features: Convert the ring type into encoded values, such as NONE=0, LOOP_SELF=1, LOOP_SIMPLE-n=2+n, LOOP_NESTED-k=10+k, and standardize the ring depth and number of nodes.

[0109] (4) Normalization of logical function expressions: Remove redundant parentheses and unify the operator format (e.g., "&&" is unified to "&") to ensure that equivalent logical expressions have a consistent string form.

[0110] After normalizing the feature vectors, the SHA-256 hash algorithm is used to calculate the normalized feature vectors, generating a fixed-length (e.g., 256-bit) feature fingerprint. Specifically, the normalized multi-dimensional features are concatenated into a string in the order of "unit type combination features → input / output port features → ring structure features → logical function expression," which serves as the input to the hash algorithm. The output hash value is the feature fingerprint of the subgraph.

[0111] After generating the feature fingerprints, the feature fingerprints of all subgraphs are stored in a hash table, and a fingerprint index is constructed using the feature fingerprint as the key and the subgraph ID as the value.

[0112] Since feature fingerprints are unique, if the feature fingerprints of two subgraphs are the same, it indicates that their core features are highly similar and they are potential equivalent subgraph sets.

[0113] Therefore, by traversing the hash table, subgraphs with the same characteristic fingerprints are grouped into the same candidate group, while subgraphs with different characteristic fingerprints are directly determined to be unequal. This allows for the rapid filtering of obviously unequal subgraphs.

[0114] Finally, for subgraphs within the same equivalent candidate group, equivalence verification is performed again for precise validation to obtain an equivalent subgraph group.

[0115] It should be noted that for each equivalence candidate group, if the number of subgraphs in the equivalence candidate group is greater than 1, then the subsequent equivalence verification process needs to be performed.

[0116] In this embodiment, when identifying each subgraph in the candidate subgraph set to obtain an equivalent subgraph group, a corresponding feature fingerprint is first generated based on the multi-dimensional features of the subgraph. Then, the subgraphs are grouped based on the feature fingerprint to obtain an equivalent candidate group. Finally, the subgraphs in the equivalent candidate group are subjected to equivalence verification to obtain an equivalent subgraph group. In this process, because the feature fingerprint is unique, obviously inequivalent subgraphs can be quickly isolated, reducing the computational load of subsequent equivalence verification and significantly improving the identification efficiency and comprehensiveness of equivalent subgraphs.

[0117] In some embodiments, performing equivalence verification on subgraphs in the equivalence candidate group to obtain an equivalence subgraph group includes: performing ring structure equivalence verification on each subgraph in the equivalence candidate group to obtain a ring structure equivalence subgraph group; and performing input signal equivalence verification on each subgraph in the ring structure equivalence subgraph group to obtain an equivalence subgraph group.

[0118] In the above implementation process, the ring structure equivalence of subgraphs within the same equivalent candidate group is verified one by one to ensure that the ring structure features are completely consistent. The verification process is as follows:

[0119] (1) Cycle existence verification: If one subgraph contains a cycle structure and the other subgraph does not contain a cycle structure, then they are considered not equivalent.

[0120] (2) Ring classification consistency verification: Check whether the ring types contained in the subgraph pair are completely consistent (e.g., both are LOOP_SIMPLE-3). If the classification labels are different, they are determined to be inequivalent.

[0121] (3) Ring topology feature verification: compare the ring depth, number of nodes, signal flow direction and attributes of the edges (such as transmission delay). If there is any difference, it is determined to be inequivalent.

[0122] (4) Validation of nested ring relationship: If the subgraph contains nested rings, it is necessary to verify whether the nesting level and the attributes of shared nodes / edges are consistent. If they are inconsistent, they are determined to be inequivalent.

[0123] It should be understood that the above verification process can be performed sequentially or simultaneously, and this application does not make any specific restrictions on this.

[0124] Taking subgraphs G7-3 and G8-3 corresponding to nodes 7 and 8 as examples:

[0125] (1) Both subgraphs contain LOOP_SIMPLE-3 cycles, with a cycle depth of 3 and a cycle number of 3.

[0126] (2) The signal flow direction inside the ring is clockwise (3→5→7→3 and 4→6→8→4), and the transmission delay and other properties are the same.

[0127] (3) Although nodes 3 and 4 in the ring are different nodes, the topological characteristics of the ring (type, depth, number of nodes, signal flow direction) are completely consistent, so the ring structure is verified as equivalent.

[0128] Therefore, in some embodiments, performing ring structure equivalence verification on each subgraph in the equivalent candidate group to obtain a ring structure equivalent subgraph group includes: using a ring structure feature library to perform ring feature verification on the subgraph containing ring structures; wherein, the ring structure feature library is generated based on a netlist directed graph model; if it is determined that there are multiple first target subgraphs with consistent ring types, consistent ring topology features, and consistent ring nesting relationships among the subgraphs containing ring structures, then a ring structure equivalent subgraph group is obtained based on the multiple first target subgraphs.

[0129] In this process, when performing ring structure equivalence verification on each subgraph in the equivalent candidate group, the ring structure feature library is used to verify the ring features of the subgraph. In this process, the ring structure equivalence of the subgraph is determined by verifying whether the ring type, ring topology features and ring nesting relationship are consistent, which improves the accuracy of ring structure equivalence verification and thus improves the comprehensiveness of the identification of equivalent subgraphs.

[0130] After the equivalence verification of the ring structure is passed, verify whether the connection relationship of its input signals is equivalent. The specific verification rules are as follows:

[0131] (1) Input signal source consistency: All input signals of the subgraph come from the same input port of the netlist or the output of the same cell, that is, the source node IDs of the input signals are completely consistent.

[0132] (2) Consistency of input signal timing relationship: The timing attributes of the input signal, such as clock domain and reset mechanism (synchronous reset / asynchronous reset), are completely consistent.

[0133] Taking subgraphs G7-3 and G8-3 corresponding to nodes 7 and 8 as examples:

[0134] (1) Initial expansion stage (G7-1 and G8-1): The input signal source of G7-1 is node 5, and the input signal source of G8-1 is node 6. Since the source nodes are different, this stage was not verified.

[0135] (2) After the first expansion (G7-2 and G8-2): The input signal sources of G7-2 are nodes 2 and 3, and the input signal sources of G8-2 are nodes 2 and 4. The source nodes are not completely consistent, and the verification of this stage is not passed.

[0136] (3) After the second expansion (G7-3 and G8-3): The input signal source of G7-3 is node 1 (transmitted through nodes 3 and 5), and the input signal source of G8-3 is also node 1 (transmitted through nodes 4 and 6). The cell types (AND2, CELL1), delay parameters, and timing attributes in the transmission path are completely consistent. Therefore, through the equivalence verification of the input signal connection relationship, it is finally determined that G7-3 and G8-3 are an equivalent subgraph pair.

[0137] Therefore, in some embodiments, input signal equivalence verification is performed on each subgraph in the ring structure equivalent subgraph group to obtain the equivalent subgraph group, including: if it is determined that there are multiple second target subgraphs in the ring structure equivalent subgraph group that have consistent input signal sources and consistent input signal timing relationships, then the equivalent subgraph group is obtained based on the multiple second target subgraphs.

[0138] In this process, the accuracy of equivalence subgraph identification is further improved by performing input signal equivalence verification on each subgraph in the ring structure equivalence subgraph group.

[0139] In this embodiment, considering that in actual circuit design, due to requirements such as feedback control logic and state machine design, loop graph structures inevitably exist in the netlist, when performing equivalence verification on each subgraph in the equivalence candidate group, loop structure equivalence verification is first performed on each subgraph in the equivalence candidate group to obtain a group of loop structure equivalent subgraphs. Then, considering that the probability of input signal equivalence in circuit design is the lowest, input signal equivalence verification is finally performed on the group of loop structure equivalent subgraphs to obtain an equivalent subgraph group. In this process, the number of subgraphs that need to be verified for equivalence is reduced step by step in a progressive manner, which not only improves the comprehensiveness of subgraph recognition but also improves recognition efficiency.

[0140] After three layers of matching and verification, a list of all equivalent subgraph groups is output. The list contains information such as subgraph ID, subgraph node set, subgraph edge set, loop structure features, and feature fingerprint, providing a basis for subgraph merging.

[0141] In some embodiments, reconstructing the original circuit netlist based on the equivalent subgraph group to generate an optimized circuit netlist includes: performing a merge constraint check on each subgraph in the equivalent subgraph group; merging the equivalent subgraphs that pass the merge constraint check to reconstruct the original circuit netlist and generate an optimized circuit netlist.

[0142] In the above implementation process, after the identification of equivalent subgraphs is completed, a safe merging strategy needs to be formulated based on the underlying physical constraints and ring structure characteristics to complete the deletion of redundant units and connections and the reconstruction of the netlist.

[0143] Before performing the merge operation, a constraint check is performed on each set of equivalent subgraphs to ensure that the merge operation does not violate physical design rules and timing requirements.

[0144] In some embodiments, a merge constraint check is performed on each subgraph in the equivalent subgraph group, including: a fan-out quantity constraint check, a timing constraint check, and a ring structure integrity constraint check on each subgraph in the equivalent subgraph group.

[0145] Taking subgraphs A and B as an example: Subgraphs A and B are equivalent, so we plan to keep subgraph A and delete subgraph B.

[0146] (1) Fan-out number constraint check: Query the current fan-out number of the target node in subgraph A, and calculate the merged fan-out number (current fan-out number + fan-out number of the target node in subgraph B). If the merged fan-out number exceeds the maximum fan-out limit of the unit (determined by the unit's physical parameters, such as the maximum fan-out number of a normal AND gate being 8), then the merge is rejected, and constraint conflict information is recorded; if the limit is not exceeded, proceed to the next step of the check. Here, the fan-out number refers to the total number of downstream input terminals (loads) connected to the output terminal of a logic unit.

[0147] (2) Timing Constraint Check: Extract the critical path delay (maximum delay from input to output) of subgraphs A and B using timing analysis tools, and verify whether the output signal of the merged subgraph A can meet the timing requirements of all target nodes. If the critical path delay of subgraph A is less than or equal to the critical path delay of subgraph B, and the output delay of the merged subgraph A does not exceed the setup and hold time requirements of the target nodes, then the timing constraint check is passed, and the next step of the check is performed. If the critical path delay of subgraph A is greater than the critical path delay of subgraph B, the timing margin of the target nodes needs to be further analyzed. If the margin is sufficient (≥ the delay difference), then the check is passed; otherwise, the merge is rejected.

[0148] (3) Ring structure integrity constraint check: If the subgraph contains a ring structure, the integrity of the ring structure must be ensured during the merging process. If subgraph A and subgraph B are part of the same ring structure, after merging, it is necessary to verify whether the node set and edge set of the ring can still form a closed path. If a ring break occurs (e.g., after deleting subgraph B, a certain edge of the ring is missing), then the merging is rejected. If subgraph A and subgraph B belong to different ring structures, after merging, it is necessary to verify whether there is a signal conflict between the two ring structures (e.g., if the same signal participates in the transmission of two rings at the same time, resulting in a logical contradiction). If a conflict exists, then the merging is rejected.

[0149] It should be noted that the order of the above fan-out quantity constraint check, timing constraint check, and ring structure integrity constraint check can be arbitrarily determined, and the three checks can also be performed simultaneously.

[0150] After the merge constraint check is completed, the equivalent subgraphs that have passed the merge constraint check will be merged to reconstruct the original circuit netlist and generate an optimized circuit netlist.

[0151] In this embodiment of the application, when reconstructing the original circuit netlist based on the equivalent subgraph group, a merging constraint check is performed on each subgraph in the equivalent subgraph group to ensure that the merging operation does not violate the circuit physical design rules and timing requirements, thereby improving the accuracy of the optimized circuit netlist.

[0152] In some embodiments, where the equivalent subgraphs include ring types; merging equivalent subgraphs that pass the merge constraint check to reconstruct the original circuit netlist and generate an optimized circuit netlist includes: determining a target merge strategy based on the ring type; and merging equivalent subgraphs that pass the merge constraint check based on the target merge strategy to reconstruct the original circuit netlist and generate an optimized circuit netlist.

[0153] As described above, rings include various types, such as self-rings, simple rings, and nested rings. Because different rings have different characteristics, their merging processes also differ.

[0154] Therefore, if an equivalent subgraph contains cycles, before merging the equivalent subgraphs, it is necessary to first determine the target merging strategy based on the cycle type, and then use the target merging strategy to execute the merging process.

[0155] The merger strategy is as follows:

[0156] (1) Self-loop subgraph merging strategy: For equivalent subgraphs containing self-loop structures (LOOP_SELF), the integrity of the self-loop edges must be preserved during merging. Taking subgraphs A and B as an example, subgraphs A and B are equivalent and contain corresponding types of self-loops. The plan is to retain subgraph A and delete subgraph B. Switch all input signals of subgraph B to the input nodes of subgraph A to ensure that the signal transmission of the self-loop edges of subgraph A is not affected; delete all nodes and edges of subgraph B, and delete redundant connections of the input nodes of subgraph B (i.e., connections that only point to subgraph B); if the self-loop edges of subgraph B are related to other signals, the related signals need to be switched to the self-loop edges of subgraph A to ensure that the logical function remains unchanged.

[0157] (2) Simple ring subgraph merging strategy: For equivalent subgraphs containing simple rings (LOOP_SIMPLE-n), the topology of the simple rings must be maintained during merging: prioritize retaining the subgraph with a more complete ring structure and lower critical path delay (denoted as retained subgraph), and delete the other subgraph (denoted as deleted subgraph); switch all output signal target nodes of the deleted subgraph to the output nodes of the retained subgraph; trace the input nodes of the deleted subgraph, and if the input node only provides signals to the deleted subgraph (without other target nodes), delete the input node and its corresponding connection; repeat the tracing until all redundant nodes (nodes only related to the deleted subgraph) are identified and deleted uniformly.

[0158] Taking the merging of equivalent subgraphs G7-3 and G8-3 corresponding to nodes 7 and 8 as an example (retaining subgraph G7-3 and deleting subgraph G8-3): Switch all target nodes (assuming they are netlist output ports or other units) of output node 8 of subgraph G8-3 to output node 7 of subgraph G7-3; Check the input node 6 (CELL1 type) of subgraph G8-3 and find that it only provides input signals to node 8 and has no other target nodes, so delete node 6 and the connection between node 6 and node 8; Trace the input node 4 (AND2 type) of node 6 and find that it only provides input signals to node 6 and has no other target nodes, so delete node 4 and the connection between node 4 and node 6; Continue tracing the input node 1 of node 4 and find that node 1 also provides signals to other units, so retain node 1 and stop tracing.

[0159] (3) Nested ring subgraph merging strategy: For equivalent subgraphs containing nested rings (LOOP_NESTED-k), the merging process should proceed step by step from the inside to the outside according to the nesting level of the rings: first merge the subgraphs corresponding to the inner ring to ensure that the integrity of the inner ring structure is not affected; then merge the subgraphs corresponding to the outer ring to avoid the inner ring from breaking due to the merging of the outer ring; during the merging process, the node connection relationship of each level of ring should be checked simultaneously to ensure that the nested structure remains unchanged.

[0160] After merging the equivalent subgraphs, the original circuit netlist is reconstructed. The specific steps are as follows:

[0161] (1) Redundant node and edge deletion

[0162] Based on the merging results, redundant unit nodes (all unit nodes in the subgraph are deleted), redundant port nodes (if the subgraph contains port nodes and has no other connections), and redundant edges (all connections related to redundant nodes and original connections of nodes whose target nodes have been switched) are deleted in batches. During the deletion process, the node list and edge list of the directed graph model in the netlist are updated synchronously to ensure data consistency.

[0163] (2) Signal connection update

[0164] Switch all input and output signal connections of the deleted subgraph to the corresponding nodes of the retained subgraph, and update the signal-node mapping. Simultaneously, modify the signal definitions and connection statements in the circuit netlist file to ensure correct syntax.

[0165] (3) Update of the ring structure feature library

[0166] Delete ring structure records related to redundant nodes. If the ring structure changes after merging (e.g., the nesting level is reduced), update the corresponding ring classification labels, node sets, edge sets, and other information to ensure that the ring structure feature library is consistent with the optimized circuit netlist.

[0167] (4) Optimized circuit netlist output

[0168] Generates optimized circuit netlist files (supports Verilog, EDIF, and other formats), and outputs a circuit netlist optimization report, which includes information such as the number of redundant elements deleted, the number of redundant connections, changes in ring structure, and the results of merging constraint checks.

[0169] In this embodiment, a target merging strategy is determined based on the ring type. The target merging strategy is then used to merge equivalent subgraphs that have passed the merging constraint check, thereby improving the accuracy of the merging and thus improving the accuracy of the optimized circuit netlist.

[0170] In some embodiments, after reconstructing the original circuit netlist based on the equivalent subgraph set to generate an optimized circuit netlist, the method further includes: if it is determined that there is no equivalent subgraph in the directed graph model formed by the optimized circuit netlist, or the number of iterations reaches a preset number of iterations, then the optimized circuit netlist is used as the target circuit netlist for simulation verification, and a verification report is generated; otherwise, the optimized circuit netlist is preprocessed to generate a new netlist directed graph model, and a new optimized circuit netlist is generated based on the new netlist directed graph model, until there is no equivalent subgraph in the directed graph model formed by the new optimized circuit netlist, or the number of iterations reaches a preset number of iterations, a new optimized circuit netlist is output, and the new optimized circuit netlist is simulated and verified, and a verification report is generated.

[0171] In the above implementation process, since a single merging may generate new equivalent subgraphs (e.g., after deleting redundant nodes, the connection relationships of other units are simplified, forming a new equivalent subgraph), it is necessary to repeatedly execute the complete process of "circuit netlist preprocessing and ring structure extraction → equivalent subgraph identification → secure merging and netlist reconstruction" on the optimized circuit netlist for iterative optimization.

[0172] (1) Iteration termination condition: If the number of cells and the number of signals in the netlist do not change after two consecutive optimizations (error ≤ 0.1%), then stop the iteration and output the final optimized netlist.

[0173] (2) Iteration limit: To avoid infinite iteration, a maximum number of iterations is set (default 5 times, which can be adjusted according to the size of the netlist). If the termination condition is not met even after the maximum number of iterations is reached, the iteration will also stop and the current optimization result will be output.

[0174] Taking the merging of the equivalent subgraphs G7-3 and G8-3 corresponding to nodes 7 and 8 as an example, after one merging:

[0175] (1) Redundant nodes 8 (CELL2), 6 (CELL1), and 4 (AND2) were removed, totaling 3 unit nodes.

[0176] (2) Redundant connections 6→8, 4→6, 2→6, 1→4, and 8→4, a total of 5 edges, were deleted.

[0177] As can be seen from the above, in the reconstructed circuit netlist, the number of cells is reduced by 50% (the original circuit netlist contained 6 cells, namely nodes 3 to 8, and nodes 4, 6 and 8 were deleted, totaling 3 cells), and the number of signals is reduced by 37.5% (the original circuit netlist contained 8 output signals, namely the output signals of 8 nodes, and 3 output signals were deleted, namely the outputs of nodes 4 to 6, the outputs of nodes 6 to 8, and the output of node 8).

[0178] The reconstructed circuit netlist is then optimized a second time. No new equivalent subgraphs are found, and the iteration termination condition is met. The final optimized netlist is then output.

[0179] To ensure that the optimized circuit netlist is completely consistent with the original circuit netlist, functional simulation and formal verification are required. The specific implementation steps are as follows:

[0180] (a) Functional simulation

[0181] (1) Test case generation

[0182] Based on the functional specifications of the original circuit netlist, generate a comprehensive test case set that covers all possible combinations of input port values, boundary conditions (such as clock frequency limits, reset signal triggering), and abnormal scenarios (such as input signal transitions, noise interference). The test case set must contain at least 1000 independent test vectors (more than 10000 for complex netlists) to ensure coverage of all logical functions of the netlist.

[0183] (2) Simulation execution

[0184] The original circuit netlist and the optimized circuit netlist were simulated using mainstream EDA simulation tools (such as ModelSim and VCS): the same test case set, clock signal and reset signal were loaded; the same simulation parameters (such as simulation accuracy and simulation duration) were set; and the output signal waveforms and data of the two netlists were recorded.

[0185] (3) Comparison of simulation results

[0186] The output results of the original circuit netlist and the optimized circuit netlist are compared cycle by cycle using waveform comparison tools (such as Debussy). If the output signals of all test cases are completely consistent (including signal level, transition time, and timing parameters), the functional simulation passes. If there are inconsistent output signals, the difference points are located, and it is analyzed whether the logic error is caused by the merging operation. If it is a problem with the merging strategy, it is necessary to go back to the merging stage, adjust the strategy, and re-optimize and simulate.

[0187] (ii) Formal verification

[0188] (1) Validation model construction

[0189] The original circuit netlist and the optimized circuit netlist are used as the "reference model" and "implementation model" for verification, respectively. A formal verification environment is constructed: the input port mapping relationship of the two models is defined (to ensure that the input signals correspond one-to-one); the equivalence judgment conditions of the output ports are defined (such as consistent signal levels and timing margin requirements); and the constraint information (such as clock constraints and reset constraints) in the netlist is imported.

[0190] (2) Equivalence proof

[0191] Use formal verification tools (such as Cadence Conformal or Synopsys Formality) to prove the equivalence of the two models: the tool automatically traverses all logical paths in the netlist to verify that the input-output mapping relationship between the reference model and the implementation model is completely consistent; focus on verifying logical paths containing loop structures to ensure that the feedback function of the loop and the state transition of the state machine are consistent with the original netlist; if the tool proves that the two models are completely equivalent, the formal verification passes; if there are unequal paths, the tool will output path details, and it is necessary to analyze whether it is caused by the deletion of redundant logic (if the redundant logic does not affect the overall function, it can be considered normal), or caused by merging errors (the merging strategy needs to be corrected).

[0192] (III) Verification Report Output

[0193] After verification is complete, a netlist verification report will be output, which includes:

[0194] (1) Functional simulation results: number of test cases, number of pass cases, number of failure cases, and details of differences (if any).

[0195] (2) Formal verification results: number of equivalent paths, number of non-equivalent paths (if any), and functional verification results of the ring structure.

[0196] (3) Conclusion: Whether the optimized circuit netlist is consistent with the original circuit netlist and whether it meets the design requirements.

[0197] Only when both functional simulation and formal verification pass are the netlist optimizations considered successful. The final output includes the optimized circuit netlist file and a complete set of reports (preprocessing report, equivalence subgraph identification report, merge optimization report, and verification report) for use in subsequent back-end processes such as circuit placement and routing.

[0198] In this embodiment, after generating the optimized circuit netlist, iterative optimization is performed, and the final generated circuit netlist is simulated and verified, which further improves the accuracy and functional consistency of the optimized circuit netlist.

[0199] In summary, the beneficial effects of the present invention are as follows:

[0200] (1) By verifying the equivalence of the loop structure and the input signal, the problem of incomplete identification of equivalent subgraphs in the netlist of the loop diagram circuit is solved, ensuring the correctness of the function of the merged netlist.

[0201] (2) It is compatible with both acyclic graphs and cyclic graph netlists, applicable to a wide range of scenarios, and can be seamlessly integrated into existing EDA tools and processes, reducing the cost of technology implementation.

[0202] (3) Effectively reduces redundant units and connections in the netlist. Experiments have verified that the number of netlist units can be reduced by 4%-8% and the number of signals can be reduced by 5%-10%.

[0203] Figure 4 This is a schematic diagram of the electronic device structure provided in the embodiments of this application, such as... Figure 4 As shown, the electronic device includes a processor 401, a memory 402, and a bus 403; wherein the processor 401 and the memory 402 communicate with each other via the bus 403. The processor 401 is used to call program instructions in the memory 402 to execute the methods provided in the above-described method embodiments.

[0204] Processor 401 can be an integrated circuit chip with signal processing capabilities. The processor 401 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0205] The memory 402 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0206] This application provides a computer program product, including: computer program instructions, which are executed by a processor to perform the methods provided in the above-described method embodiments.

[0207] This application provides a computer-readable storage medium, including: computer program instructions stored on the computer-readable storage medium, which, when executed by a processor, perform the methods provided in the above-described method embodiments.

[0208] Computer-readable storage media can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0209] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0210] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0211] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0212] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for optimizing a circuit netlist, characterized in that, The method includes: The original circuit netlist is preprocessed to generate a directed graph model of the netlist; Based on the directed graph model of the netlist, a candidate set of subgraphs is generated; Each subgraph in the candidate subgraph set is identified to obtain an equivalent subgraph group; Based on the equivalent subgraph set, the original circuit netlist is reconstructed to generate an optimized circuit netlist; The subgraph includes multi-dimensional features; the step of identifying each subgraph in the candidate subgraph set to obtain an equivalent subgraph group includes: Based on the multi-dimensional features, the feature fingerprint of the corresponding sub-graph is generated; Using the feature fingerprint, the sub-graph is grouped to obtain equivalent candidate groups; Perform ring structure equivalence verification on each subgraph in the equivalent candidate group to obtain a ring structure equivalent subgraph group; Perform input signal equivalence verification on each subgraph in the ring structure equivalent subgraph group to obtain the equivalent subgraph group; The step of performing ring structure equivalence verification on each subgraph in the equivalent candidate group to obtain a ring structure equivalent subgraph group includes: Using a ring structure feature library, ring feature verification is performed on subgraphs containing ring structures; wherein, the ring structure feature library is generated based on the netlist directed graph model; If it is determined that there are multiple first target subgraphs with the same ring type, the same ring topological features, and the same ring nesting relationship in the subgraph containing the ring structure, then the equivalent subgraph group of the ring structure is obtained based on the multiple first target subgraphs. The step of performing input signal equivalence verification on each subgraph in the equivalent subgraph group of the ring structure to obtain the equivalent subgraph group includes: If it is determined that there are multiple second target subgraphs in the ring structure equivalent subgraph group that have the same input signal source and the same input signal timing relationship, then the equivalent subgraph group is obtained based on the multiple second target subgraphs; The step of reconstructing the original circuit netlist based on the equivalent subgraph group to generate an optimized circuit netlist includes: Perform a merge constraint check on each subgraph in the equivalent subgraph group; The equivalent subgraphs that pass the merge constraint check are merged to reconstruct the original circuit netlist, generating the optimized circuit netlist.

2. The method according to claim 1, characterized in that, The multi-dimensional features include unit type combination features, input / output port features, ring structure features, and logical function expressions; the step of generating the feature fingerprint of the corresponding sub-graph based on the multi-dimensional features includes: The unit type combination features, the input / output port features, the ring structure features, and the logic function expressions are normalized respectively to obtain standard unit type combination features, standard input / output port features, standard ring structure features, and standard logic function expressions; Using a hash algorithm, the feature fingerprint of the subgraph is generated based on the standard unit type combination features, the standard input / output port features, the standard ring structure features, and the standard logical function expression.

3. The method according to claim 1, characterized in that, The step of performing a merge constraint check on each subgraph in the equivalent subgraph group includes: Perform fan-out quantity constraint checks, timing constraint checks, and ring structure integrity constraint checks on each subgraph in the equivalent subgraph group.

4. The method according to claim 3, characterized in that, in, The equivalent subgraph includes ring types; the merging of equivalent subgraphs that have passed the merge constraint check to reconstruct the original circuit netlist and generate the optimized circuit netlist includes: Determine the target merging strategy based on the ring type; Based on the target merging strategy, the equivalent subgraphs that have passed the merging constraint check are merged to reconstruct the original circuit netlist and generate the optimized circuit netlist.

5. The method according to any one of claims 1-4, characterized in that, in, The netlist directed graph model includes multiple nodes and directed edges connecting the nodes; The step of generating a candidate set of subgraphs based on the directed graph model of the netlist includes: Taking each node as a starting point, a first adjacent node directly connected to the starting point is determined based on the directed edge; wherein, the starting point and the first adjacent node constitute a minimum subgraph; Using the first adjacent node as a new starting point, and according to the preset expansion rules and the directed edges, the second adjacent node directly connected to the first adjacent node is added to the minimum subgraph to generate a new subgraph; Starting from the second adjacent node, new adjacent nodes are added to the new subgraph step by step according to the preset expansion rules until the new subgraph meets the preset subgraph requirements, thereby generating the subgraph candidate set.

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