A method for dynamic determination of memory type for prototyping and hardware simulation

Abstract

The application relates to the chip design simulation verification technical field, in particular to a memory type dynamic decision method for prototype verification and hardware simulation, which divides a sub-design according to a module level of each module in a user netlist and in combination with a first resource threshold sequence corresponding to an FPGA, matches design logic clustering characteristics, reduces cross-sub-design interconnection, adapts to the hardware segmentation demand of multi-FPGA prototype verification, reduces the layout and wiring difficulty, effectively improves the performance and frequency of the FPGA, and according to a first target conversion rate, a second target conversion rate and a target memory type of an object, the memory type allocation is realized, so that the relative balance and independence of various memory resources in the sub-design are realized as much as possible, the required FPGA chip quantity of the sub-design is reduced, and the performance of the FPGA is improved.

Description

Technical Field

[0001] This invention relates to the field of chip design simulation and verification technology, and in particular to a method for dynamically determining memory type for prototype verification and hardware simulation. Background Technology

[0002] In FPGA multi-chip prototyping and hardware simulation scenarios, on-chip memory resources are the core hardware resources that limit design partitioning and performance. When configuring memory types, existing prototyping and hardware simulation tools only bind design storage objects to a single memory type according to default rules. This may result in a large number of storage objects being bound to the same memory type, leading to a waste of other on-chip memory resources and indirectly reducing FPGA performance.

[0003] Moreover, netlist partitioning typically only isolates and counts the basic utilization of lookup tables, registers, and memory. This often leads to a disconnect between the storage resources required by the sub-designs partitioned from the netlist and the actual storage capacity of the FPGA hardware. Furthermore, the pursuit of optimal basic utilization of a single resource may result in frequent cross-chip partitioning of sub-designs, leading to a surge in the number of interconnects. Ultimately, this results in lower FPGA operating frequency and prototype verification stability, as well as lower FPGA performance.

[0004] Therefore, how to improve the performance of FPGAs in prototype verification and hardware simulation scenarios has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] A method for dynamically determining memory type for prototyping and hardware simulation, the method comprising:

[0007] S1. Based on the preset first resource threshold sequence and the resource occupancy statistics sequence corresponding to each module in the user netlist, the highest module level module is divided into several sub-designs, where each module corresponds to a module level.

[0008] S2, For any sub-design, determine the reference category corresponding to each object in the sub-design according to the preset constraint set, wherein the reference category includes a fixed category and a variable category;

[0009] S3. Based on the preset second resource threshold sequence and the reference category, target storage resource occupancy, first target conversion rate and second target conversion rate corresponding to each object in the sub-design, determine the target memory type corresponding to each object in the sub-design.

[0010] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the memory type dynamic determination method for prototype verification and hardware simulation provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0011] This invention provides a method for dynamically determining memory type for prototype verification and hardware simulation. Based on the module hierarchy of each module in the user netlist and combined with the first resource threshold sequence corresponding to the FPGA, sub-designs are divided. This aligns with the clustering characteristics of design logic, reduces cross-sub-design interconnections, adapts to the hardware partitioning requirements of multi-FPGA prototype verification, reduces placement and routing difficulty, and effectively improves FPGA performance and frequency. Furthermore, memory type allocation is achieved based on the object's first target conversion rate, second target conversion rate, and target memory type, ensuring relative balance and independence of various memory resources within the sub-design. This reduces the number of FPGA chips required for sub-design implementation, effectively improving FPGA performance. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a method for dynamically determining memory type for prototype verification and hardware simulation, provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This embodiment provides a method for dynamically determining memory type for prototype verification and hardware simulation. See [link to documentation]. Figure 1 The present invention provides a flowchart illustrating a method for dynamically determining memory type for prototype verification and hardware simulation, wherein the method includes:

[0016] S1. Based on the preset first resource threshold sequence and the resource occupancy statistics sequence corresponding to each module in the user netlist, the highest module level module is divided into several sub-designs, where each module corresponds to a module level.

[0017] S2, For any sub-design, determine the reference category corresponding to each object in the sub-design according to the preset constraint set, wherein the reference category includes a fixed category and a variable category;

[0018] S3. Based on the preset second resource threshold sequence and the reference category, target storage resource occupancy, first target conversion rate and second target conversion rate corresponding to each object in the sub-design, determine the target memory type corresponding to each object in the sub-design.

[0019] In this embodiment, the application is in the scenario of prototype verification and hardware simulation. Prototype verification and hardware simulation refer to hardware verification methods that reproduce the functions of ASICs, SoCs, etc. based on FPGA arrays.

[0020] The first resource threshold sequence includes multi-dimensional hardware resource upper limit thresholds used for netlist partitioning.

[0021] User netlists are circuit description files output by netlist synthesis tools. User netlists include all modules, objects, and interconnections. Objects refer to stored objects.

[0022] The resource usage statistics sequence refers to the multi-dimensional actual resource consumption values ​​of the corresponding module. The resource usage statistics sequence corresponds one-to-one with the dimensions of the first resource threshold sequence.

[0023] Module hierarchy refers to the nesting level of corresponding modules. For example, module hierarchy includes top-level module hierarchy, sub-module hierarchy and bottom-level module hierarchy.

[0024] The highest module level module refers to the top-level parent module of the user netlist, that is, the module corresponding to the top-level module level.

[0025] A sub-design refers to an independent design unit that can be adapted to a single FPGA after being partitioned by a netlist. A single sub-design may include multiple modules.

[0026] The preset constraint set is used to determine the memory type that the object is compatible with.

[0027] Reference categories refer to the adjustable attribute classification of objects based on their memory type. Reference categories include fixed categories and variable categories. Objects with fixed categories are those that can only adapt to a single memory type, while objects with variable categories are those that can adapt to two or more memory types.

[0028] The second resource threshold sequence is used to represent the upper limit of various types of storage resources that a single FPGA can support.

[0029] The target storage resource usage refers to the storage resource capacity required for the corresponding storage object to perform its functions.

[0030] The first target conversion rate refers to the resource equivalence conversion ratio of a variable object between the second memory type and the first memory type. In other words, the first target conversion rate is expressed as the ratio of the number of chips required to implement the variable object using the second memory type to the number of chips required to implement the variable object using the first memory type. The second target conversion rate refers to the resource equivalence conversion ratio of a variable object between the third memory type and the first memory type. In other words, the first target conversion rate is expressed as the ratio of the number of chips required to implement the variable object using the third memory type to the number of chips required to implement the variable object using the first memory type.

[0031] The target memory type refers to the type of hardware memory that the object is ultimately mapped to.

[0032] In one specific implementation, the first resource threshold sequence includes at least a lookup table resource threshold, a register resource threshold, a first storage resource threshold, a second storage resource threshold, and a third storage resource threshold. The resource occupancy statistics sequence includes at least a lookup table resource occupancy value, a register resource occupancy value, a first storage resource occupancy value, a second storage resource occupancy value, and a third storage resource occupancy value. The first resource threshold sequence corresponds to a first storage resource conversion rate and a second storage resource conversion rate. The resource occupancy statistics sequence corresponds to a first reference conversion rate and a second reference conversion rate. Step S101 includes the following steps:

[0033] S11, Divide the second storage resource threshold by the first storage resource conversion rate to obtain the second reference threshold;

[0034] S12, divide the third storage resource threshold by the second storage resource conversion rate to obtain the third reference threshold;

[0035] S13, add the first storage resource threshold, the second reference threshold and the third reference threshold to obtain the comprehensive storage resource threshold;

[0036] S14, a reference threshold sequence is formed by the lookup table resource threshold, the register resource threshold, and the storage resource comprehensive threshold;

[0037] S15, For any module, divide the first storage resource occupancy value corresponding to the module by the corresponding first reference conversion rate to obtain the second conversion occupancy value;

[0038] S16, divide the second storage resource occupancy value corresponding to the module by the corresponding second reference conversion rate to obtain the third conversion occupancy value;

[0039] S17, add the first storage resource occupancy value, the second conversion occupancy value and the third conversion occupancy value corresponding to the module to obtain the comprehensive storage resource occupancy value;

[0040] S18, a reference occupancy value sequence is formed from the lookup table resource occupancy value, register resource occupancy value, and storage resource occupancy value corresponding to this module;

[0041] S19, based on the reference threshold sequence and the reference occupancy value sequence corresponding to each module, the module at the highest module level is divided into several sub-designs.

[0042] Among them, the lookup table resource threshold refers to the upper limit of LUT resources, the register resource threshold refers to the upper limit of register resources, and the first storage resource threshold, the second storage resource threshold, and the third storage resource threshold refer to the upper limits of three types of hardware storage resources.

[0043] The lookup table resource usage value refers to the actual lookup table resource consumption value of the corresponding module, the register resource usage value refers to the actual register resource consumption value of the corresponding module, and the first storage resource usage value, the second storage resource usage value, and the third storage resource usage value refer to the actual three types of hardware storage resource consumption values ​​of the corresponding module.

[0044] The first storage resource conversion rate refers to the equivalent conversion ratio of the second storage resource threshold to the first storage resource threshold, and the second storage resource conversion rate refers to the equivalent conversion ratio of the third storage resource threshold to the first storage resource threshold.

[0045] The first reference conversion rate refers to the equivalent conversion ratio of the second storage resource occupancy value of the corresponding module relative to the first storage resource occupancy value, and the second reference conversion rate refers to the equivalent conversion ratio of the third storage resource occupancy value of the corresponding module relative to the first storage resource occupancy value.

[0046] The second reference threshold refers to the equivalent threshold after the second storage resource threshold is converted by the first storage resource conversion rate, and the third reference threshold refers to the equivalent threshold after the third storage resource threshold is converted by the second storage resource conversion rate.

[0047] The comprehensive threshold for storage resources refers to the upper limit of the total resources after normalization of the three types of hardware storage resources.

[0048] In one specific implementation, step S19 includes the following steps:

[0049] S191, if the element at each position in the reference occupancy value sequence corresponding to the highest module level is less than or equal to the element at the corresponding position in the reference threshold sequence, then the module at the highest module level is used as a sub-design; otherwise, a module set is formed from the various modules.

[0050] S192, Select any module with the lowest module level from the module set as the target module;

[0051] S193, use the module level of the target module as the level identifier i;

[0052] S194, if the element at each position in the reference occupancy value sequence corresponding to the target module is less than or equal to the element at the corresponding position in the reference threshold sequence, the module with module level i+1 to which the target module belongs is used as a temporary module.

[0053] S195, if the element at each position in the reference occupancy value sequence corresponding to the temporary module is less than or equal to the element at the corresponding position in the reference threshold sequence, then the temporary module is taken as the target module, and the process returns to step S193; otherwise, the target module is taken as a sub-design, and the target module and its contained modules are removed from the module set, and the process returns to step S192, until the module set contains only the module at the highest module level.

[0054] The module set refers to the set of modules to be divided. When the element at each position in the reference occupancy value sequence corresponding to the highest module level is less than or equal to the element at the corresponding position in the reference threshold sequence, it means that the resource consumption values ​​of the top-level module are all within the upper limit allowable range, and the top-level module can be directly used as a sub-design for subsequent memory type allocation. Otherwise, it is necessary to judge the resource compliance layer by layer starting from the bottom module.

[0055] The lowest-level module in a module set may consist of multiple modules. The lowest module level in a module set may be the bottom-level module level, the sub-module level, etc., and is dynamically determined based on the modules contained in the current module set.

[0056] The target module refers to the module to be segmented for determining the compliance of resources.

[0057] A temporary module is the direct parent module of the target module, used for hierarchical aggregation determination.

[0058] For example, a user netlist includes a top-level module, two sub-modules, and the bottom-level modules contained in each of the two sub-modules. When the resource compliance judgment of the top-level module exceeds the limit, a module set is formed by the top-level module, the two sub-modules, and the bottom-level modules contained in each of the two sub-modules. The lowest module level in the current module set is the bottom-level module level. One bottom-level module is selected as the target module. If the target module's resources are compliant, the resource compliance judgment is performed on the sub-modules to which the target module belongs. If the temporary module's resources are compliant, the temporary module is selected as the target module. At this time, the top-level module to which the temporary module belongs exceeds the resource limit. Therefore, the sub-module is determined as a sub-design, and the sub-module and its contained bottom-level modules are deleted from the module set. At this time, the module set contains the top-level module, the sub-module, and the bottom-level modules contained in the sub-module. A bottom-level module is selected again as the target module, and the same judgment process is used to determine another sub-design, resulting in two sub-designs. At this time, the module set only contains the module at the highest module level, and the iteration stops.

[0059] In one specific implementation, the preset constraint set includes a first constraint subset, a second constraint subset, and a third constraint subset, with each object corresponding to attribute information. Step S2 includes the following steps:

[0060] S21, for any object in the sub-design, if the attribute information corresponding to the object satisfies the first constraint subset, then it is determined that the object is suitable for the first memory type;

[0061] S22, if the attribute information corresponding to the object satisfies the second constraint subset, then it is determined that the object is suitable for the second memory type;

[0062] S23, if the attribute information corresponding to the object satisfies the third constraint subset, then it is determined that the object is suitable for the third memory type;

[0063] S24. If the object is only applicable to one of the first memory type, the second memory type, and the third memory type, then the reference category corresponding to the object is determined to be a fixed category; otherwise, the reference category corresponding to the object is determined to be a variable category.

[0064] The first constraint subset refers to the adaptation constraint rules for the first memory type, the second constraint subset refers to the adaptation constraint rules for the second memory type, and the third constraint subset refers to the adaptation constraint rules for the third memory type. The adaptation constraint rules contain multiple dimensions. For example, the dimensions included in the adaptation constraint rules are constraints such as the number of ports, timing, and write enable.

[0065] Attribute information refers to the multidimensional inherent attributes of the corresponding object. For example, the dimensions of attribute information include bit width, number of ports, read / write timing, number of byte write enabled, etc.

[0066] It should be noted that this embodiment uses three types of storage resources as examples for description. Implementers should know that, depending on the actual application scenario, expanding the storage resource types to more types is still within the protection scope of this invention.

[0067] In one specific implementation, the second resource threshold sequence includes a fourth storage resource threshold, a fifth storage resource threshold, and a sixth storage resource threshold, and step S3 includes the following steps:

[0068] S31, set each object with a reference category of fixed category and applicable to the first memory type as the first memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the first memory type, divide the sum by the fourth storage resource threshold and round it to obtain the first initial chip number;

[0069] S32, set each object with a reference category of fixed category and applicable to the second memory type as the second memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the second memory type, divide the sum by the fifth storage resource threshold and round it to obtain the second initial chip number;

[0070] S33, set each object with a reference category of fixed category and applicable to the third memory type as the third memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the third memory type, divide the sum by the sixth storage resource threshold and round it to obtain the third initial chip quantity;

[0071] S34, the maximum value among the first initial chip quantity, the second initial chip quantity, and the third initial chip quantity is used as the reference chip quantity;

[0072] S35, based on the number of reference chips, the reference category corresponding to each object in the sub-design, the target storage resource usage, the first target conversion rate, and the second target conversion rate, determine the target memory type corresponding to each object in the sub-design.

[0073] The first initial chip quantity refers to the number of chips required for a fixed category object to occupy the first memory type, the second initial chip quantity refers to the number of chips required for a fixed category object to occupy the second memory type, and the third initial chip quantity refers to the number of chips required for a fixed category object to occupy the third memory type.

[0074] Rounding refers to rounding up the chip count according to the smallest unit of granularity. For example, if the smallest unit of granularity of chip count is the tenths place, if all the digits after the tenths place have non-zero values, then regardless of the size of the digits after the tenths place, the digit in the tenths place is directly added by 1. Otherwise, the digit in the tenths place remains unchanged. The final result only retains the integer part and one decimal place. If the value before rounding is 1.333, then the result after rounding is 1.4.

[0075] The fourth storage resource threshold refers to the upper limit of resources corresponding to the first memory type in a single FPGA, the fifth storage resource threshold refers to the upper limit of resources corresponding to the second memory type in a single FPGA, and the sixth storage resource threshold refers to the upper limit of resources corresponding to the third memory type in a single FPGA.

[0076] The reference chip count refers to the maximum value among the first initial chip count, the second initial chip count, and the third initial chip count, which is used to provide a baseline chip count for allocating memory types to subsequent variable class objects.

[0077] In one specific implementation, step S35 includes the following steps:

[0078] S351, the number of reference chips is used as the number of temporary chips;

[0079] S352, set the memory type of each object in the subdesign whose reference category is a variable category to the first memory type;

[0080] S353, add up the target storage resource occupancy of each object in the sub-design whose memory type is the first memory type and whose reference category is a variable category, divide the sum by the fourth storage resource threshold and round it, and add the rounding result to the first initial chip number to obtain the first intermediate chip number.

[0081] S354, if the number of the first intermediate chips is less than or equal to the number of temporary chips, the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, each object in the sub-design with a reference category of variable category and applicable to the second memory type is sorted according to the corresponding first target conversion rate to obtain the first sequence of objects to be converted.

[0082] S355, set the j-th object in the first sequence of objects to be converted as the second memory type, divide the target storage resource occupancy corresponding to the j-th object by the fourth storage resource threshold and round it, update the first intermediate chip quantity with the difference between the first intermediate chip quantity and the rounding result, divide the product of the target storage resource occupancy corresponding to the j-th object and the corresponding first target conversion rate by the fifth storage resource threshold, round the division result and add it to the second intermediate chip quantity to update the second intermediate chip quantity, wherein j is initially set to 1, and the second intermediate chip quantity is initially the second initial chip quantity;

[0083] S356, if the number of the first intermediate chips and the number of the second intermediate chips are both less than or equal to the number of temporary chips, then the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, update j=j+1 and return to step S355 until the number of the first intermediate chips and the number of the second intermediate chips are both less than or equal to the number of temporary chips, or the number of the second intermediate chips is greater than the number of temporary chips. When the number of the second intermediate chips is greater than the number of temporary chips, set the j-th object as the first memory type and execute step S357.

[0084] S357, sort each object in the sub-design whose reference category is variable category, which is applicable to the third memory type and whose memory type has not been converted according to its corresponding second target conversion rate to obtain the second sequence of objects to be converted;

[0085] S358, set the kth object in the second sequence of objects to be converted as the third memory type, divide the target storage resource occupancy corresponding to the kth object by the fourth storage resource threshold and round it, update the first intermediate chip quantity with the difference between the first intermediate chip quantity and the rounding result, divide the product of the target storage resource occupancy corresponding to the kth object and the corresponding second target conversion rate by the sixth storage resource threshold, round the division result and add it to the third intermediate chip quantity to update the third intermediate chip quantity, where k is initially set to 1 and the third intermediate chip quantity is initially the third initial chip quantity;

[0086] S359, if the number of the first intermediate chips and the number of the third intermediate chips are both less than or equal to the number of temporary chips, then the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, update k=k+1 and return to step S358 until the number of the first intermediate chips and the number of the third intermediate chips are both less than or equal to the number of temporary chips, or the number of the third intermediate chips is greater than the number of temporary chips. When the number of the third intermediate chips is greater than the number of temporary chips, update the number of temporary chips with a preset step size and return to step S352 until the target memory type corresponding to each object in the sub-design is determined.

[0087] The temporary chip quantity refers to the dynamic chip quantity benchmark during the iterative allocation process, initially set as the reference chip quantity.

[0088] The first intermediate chip quantity refers to the number of real-time chips of the first memory type occupied during the iteration; the second intermediate chip quantity refers to the number of real-time chips of the second memory type occupied during the iteration; and the third intermediate chip quantity refers to the number of real-time chips of the third memory type occupied during the iteration.

[0089] The first sequence of objects to be converted refers to the conversion queue of variable objects that can be converted to the second memory type, arranged in descending order according to the corresponding first target conversion rate. The second sequence of objects to be converted refers to the conversion queue of variable objects that can be converted to the third memory type, arranged in descending order according to the corresponding second target conversion rate.

[0090] The preset step size refers to the increment value of the number of temporary chips in an iterative increment. For example, the preset step size is set to 0.1.

[0091] For example, suppose the initial number of chips is 2, the second initial number of chips is 1, the third initial number of chips is 1.5, and the number of reference chips is 2. Then the initial number of temporary chips is 2. The objects are classified into variable categories V1, V2, V3, V4, and V5. V1 corresponds to a target storage requirement equivalent to 25 BRAM chips, with a first target conversion rate of 0.15 and a second target conversion rate of 0.9. V2 corresponds to a target storage requirement equivalent to 20 BRAM chips, with a first target conversion rate of 0.125 and a second target conversion rate of 0.8. V3 corresponds to a target storage requirement equivalent to... The target memory usage for V4 is equivalent to 18 BRAM chips, with a first target conversion rate of 0.1 and a second target conversion rate of 0.7. The target memory usage for V4 is equivalent to 15 BRAM chips, with a first target conversion rate of 0.13. It cannot be converted to the third memory type. The target memory usage for V5 is equivalent to 12 BRAM chips, which cannot be converted to the second memory type. The second target conversion rate is 0.85. The fourth memory resource threshold is 30 BRAM chips, the fifth memory resource threshold is 6 URAM chips, and the sixth memory resource threshold is 80 LUTRAM chips.

[0092] In the first iteration, the number of first intermediate chips is calculated as (25+20+18+15+12) / 30+2=5. Since the number of first intermediate chips (5) is greater than the number of temporary chips (2), objects that can be converted to the second memory type are selected and sorted in ascending order according to the first target conversion rate, resulting in [V3, V2, V4, V1]. The initial number of second intermediate chips is 1. When j=1, V3 is converted to the second memory type. The number of first intermediate chips decreases to 5-f(18 / 30)=5-0.6=4.4, and the number of second intermediate chips increases to 1+f(18×0.1 / 6). Since the first intermediate chip count is still greater than 2, update j=2, convert V2 to the second memory type, the first intermediate chip count decreases to 4.4-f(20 / 30)=4.4-0.7=3.7, the second intermediate chip count increases to 1.3+f(20×0.125 / 6)=1.8, the first intermediate chip count is still greater than 2, update j=3, convert V4 to the second memory type, the first intermediate chip count decreases to 3.7-f(15 / 30)=3.7-0.5=3.2, the second intermediate chip count increases to 1.8+f(15×0.125 / 6). 13 / 6) = 2.2. The number of the first and second intermediate chips is greater than 2. V4 is restored to the first memory type. At this time, the number of the first intermediate chips is 3.7, and the number of the second intermediate chips is 1.8. Objects that can be converted to the third memory type but have not yet been converted are selected and sorted in ascending order according to the second target conversion rate, resulting in [V5, V1]. The initial number of the third intermediate chips is 1.5. When k=1, V5 is converted to the third memory type. The number of the first intermediate chips decreases to 3.7 - f(12 / 30) = 3.7 - 0.4 = 3.3. The number of chips increases to 1.5 + f(12 × 0.85 / 80) = 1.7. The number of first intermediate chips is still greater than 2. Update k = 2 and convert V1 to the third memory type. The number of first intermediate chips decreases to 3.3 - f(25 / 30) = 3.3 - 0.9 = 2.4. The number of third intermediate chips increases to 1.7 + f(25 × 0.9 / 80) = 2. There are no objects that can be converted to memory type. The number of first intermediate chips is still greater than 2. Adjust the number of temporary chips to 2.1 and perform the second round of iteration. Here, f() is the rounding process with tenths as the granularity.

[0093] In the second iteration, the number of first intermediate chips is calculated to be 5. Since the number of first intermediate chips (5) is greater than the number of temporary chips (2.1), objects that can be converted to the second memory type are selected and sorted in ascending order according to the first target conversion rate, resulting in [V3, V2, V4, V1]. The initial number of second intermediate chips is 1. When j=1, V3 is converted to the second memory type. The number of first intermediate chips decreases to 5 - f(18 / 30) = 5 - 0.6 = 4.4, and the number of second intermediate chips increases to 1 + f(18 × 0.1 / 6) = 1.3. The number of chips is still greater than 2.1, so update j=2 and convert V2 to the second memory type. The number of first intermediate chips decreases to 4.4 - f(20 / 30) = 4.4 - 0.7 = 3.7, and the number of second intermediate chips increases to 1.3 + f(20 × 0.125 / 6) = 1.8. The number of first intermediate chips is still greater than 2.1, so update j=3 and convert V4 to the second memory type. The number of first intermediate chips decreases to 3.7 - f(15 / 30) = 3.7 - 0.5 = 3.2, and the number of second intermediate chips increases to 1.8 + f(15 × 0.125 / 6) = 1.8. Since 0.13 / 6) = 2.2, the number of the first and second intermediate chips is greater than 2.1. V4 is restored to the first memory type. At this time, the number of the first intermediate chips is 3.7, and the number of the second intermediate chips is 1.8. Objects that can be converted to the third memory type but have not been converted are selected and sorted in ascending order according to the second target conversion rate, resulting in [V5, V1]. The initial number of the third intermediate chips is 1.5. When k=1, V5 is converted to the third memory type, and the number of the first intermediate chips decreases to 3.7 - f(12 / 30) = 3.7 - 0. .4=3.3, the number of third intermediate chips increases to 1.5+f(12×0.85 / 80)=1.7, the number of first intermediate chips is still greater than 2, update k=2, convert V1 to the third memory type, the number of first intermediate chips decreases to 3.3-f(25 / 30)=3.3-0.9=2.4, the number of third intermediate chips increases to 1.7+f(25×0.9 / 80)=2, there are no objects that can be converted to memory type, the number of first intermediate chips is still greater than 2.1, adjust the number of temporary chips to 2.2, and perform the third round of iteration;

[0094] In the third iteration, the number of first intermediate chips is calculated to be 5. Since the number of first intermediate chips (5) is greater than the number of temporary chips (2.2), objects that can be converted to the second memory type are selected and sorted in ascending order according to the first target conversion rate, resulting in [V3, V2, V4, V1]. The initial number of second intermediate chips is 1. When j=1, V3 is converted to the second memory type. The number of first intermediate chips decreases to 5 - f(18 / 30) = 5 - 0.6 = 4.4, and the number of second intermediate chips increases to 1 + f(18 × 0.1 / 6) = 1.3. The number of first intermediate chips is still greater than 2.2, so j=2 is updated, and V2 is converted to the second memory type. The number of first intermediate chips is reduced to 4.4 - f(20 / 30) = 4.4 - 0.7 = 3.7, and the number of second intermediate chips is increased to 1.3 + f(20 × 0.125 / 6) = 1.8. The number of first intermediate chips is still greater than 2.2, so j=3 is updated, and V4 is converted to the second memory type. The number of first intermediate chips is reduced to 3.7 - f(15 / 30) = 3.7 - 0.5 = 3.2, and the number of second intermediate chips is increased to 1.8 + f(15 × 0.13 / 6) = 2.2. J=4 is updated, and V1 is converted to the second memory type. The number of first intermediate chips is reduced to 3.2 - f(20 / 30) = 4.4 - 0.7 = 3.7. 30) = 3.7 - 0.9 = 2.8, the number of second intermediate chips increases to 1.8 + f(25 × 0.15 / 6) = 2.5, the number of second intermediate chips is greater than 2.2, V1 is restored to the first memory type, at this time the number of first intermediate chips is 3.2, the number of second intermediate chips is 2.2, the objects that can be converted to the third memory type and have not been converted are filtered out and sorted in ascending order according to the second target conversion rate, resulting in [V5, V1], the initial number of third intermediate chips is 1.5, when k=1, V5 is converted to the third memory type, the number of first intermediate chips decreases to 3.2 - f(12 / 30) = 3. 2 - 0.4 = 2.8, the number of third intermediate chips increases to 1.5 + f(12 × 0.85 / 80) = 1.7, the number of first intermediate chips is still greater than 2, update k = 2, convert V1 to the third memory type, the number of first intermediate chips decreases to 2.8 - f(25 / 30) = 2.8 - 0.9 = 1.9, the number of third intermediate chips increases to 1.7 + f(25 × 0.9 / 80) = 2, the iteration is completed, that is, when the number of temporary chips is 2.2, each object in this sub-design determines the corresponding target memory type, V2, V3 and V4 are the second memory type, and V1 and V5 are the third memory type.

[0095] In one specific implementation, the first memory type is a BRAM memory type, the second memory type is a URAM memory type, and the third memory type is a LUTRAM memory type.

[0096] Among them, BRAM memory type refers to block RAM in FPGA, which is a general medium-granularity storage resource; URAM memory type refers to Ultra RAM in FPGA, which is a large-granularity high-bandwidth storage resource; and LUTRAM memory type refers to fine-granularity storage resource implemented by lookup tables in FPGA.

[0097] In one specific implementation, the method for dynamically determining the memory type for prototype verification and hardware simulation further includes:

[0098] S4. Based on the target memory type corresponding to each object in each sub-design, the user netlist is instantiated by deduplication.

[0099] Among them, the deduplication instantiation process of the netlist refers to the Uniquify netlist, which splits the shared module template into independent instances for one-to-one correspondence with objects, and completes the mapping of the allocation scheme to the netlist.

[0100] In this embodiment, sub-designs are divided according to the module hierarchy of each module in the user netlist and the first resource threshold sequence corresponding to the FPGA. This conforms to the clustering characteristics of design logic, reduces cross-sub-design interconnections, adapts to the hardware partitioning requirements of multi-FPGA prototype verification, reduces placement and routing difficulty, and effectively improves the performance and frequency of the FPGA. Moreover, memory type allocation is achieved based on the first target conversion rate, the second target conversion rate, and the target memory type of the object, so that the relative balance and independence of various memory resources are achieved as much as possible within the sub-design. This reduces the number of FPGA chips required to implement the sub-design, which is equivalent to improving the performance of the FPGA.

[0101] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A method for dynamically determining memory type for prototype verification and hardware simulation, characterized in that, The method for dynamically determining the memory type for prototype verification and hardware simulation includes: S1. Based on the preset first resource threshold sequence and the resource occupancy statistics sequence corresponding to each module in the user netlist, the highest module level module is divided into several sub-designs, where each module corresponds to a module level. S2, For any sub-design, determine the reference category corresponding to each object in the sub-design according to the preset constraint set, wherein the reference category includes a fixed category and a variable category; S3. Based on the preset second resource threshold sequence and the reference category, target storage resource occupancy, first target conversion rate and second target conversion rate corresponding to each object in the sub-design, determine the target memory type corresponding to each object in the sub-design. The first target conversion rate is expressed as the ratio of the number of chips required to implement the object of the corresponding variable category using the second memory type to the number of chips required to implement the object of the corresponding variable category using the first memory type. The second target conversion rate is expressed as the ratio of the number of chips required to implement the object of the corresponding variable category using the third memory type to the number of chips required to implement the object of the corresponding variable category using the first memory type.

2. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 1, characterized in that, The first resource threshold sequence includes at least a lookup table resource threshold, a register resource threshold, a first storage resource threshold, a second storage resource threshold, and a third storage resource threshold. The resource occupancy statistics sequence includes at least a lookup table resource occupancy value, a register resource occupancy value, a first storage resource occupancy value, a second storage resource occupancy value, and a third storage resource occupancy value. The first resource threshold sequence corresponds to a first storage resource conversion rate and a second storage resource conversion rate. The resource occupancy statistics sequence corresponds to a first reference conversion rate and a second reference conversion rate. The first storage resource conversion rate is the equivalent conversion ratio of the second storage resource threshold to the first storage resource threshold. The second storage resource conversion rate is the equivalent conversion ratio of the third storage resource threshold to the first storage resource threshold. The first reference conversion rate is the equivalent conversion ratio of the second storage resource occupancy value of the corresponding module to the first storage resource occupancy value. The second reference conversion rate is the equivalent conversion ratio of the third storage resource occupancy value of the corresponding module to the first storage resource occupancy value. Step S1 includes the following steps: S11, Divide the second storage resource threshold by the first storage resource conversion rate to obtain the second reference threshold; S12, divide the third storage resource threshold by the second storage resource conversion rate to obtain the third reference threshold; S13, add the first storage resource threshold, the second reference threshold and the third reference threshold to obtain the comprehensive storage resource threshold; S14, a reference threshold sequence is formed by the lookup table resource threshold, the register resource threshold, and the storage resource comprehensive threshold; S15, For any module, divide the second storage resource occupancy value corresponding to the module by the corresponding first reference conversion rate to obtain the second conversion occupancy value; S16, divide the third storage resource occupancy value corresponding to the module by the corresponding second reference conversion rate to obtain the third conversion occupancy value; S17, add the first storage resource occupancy value, the second conversion occupancy value and the third conversion occupancy value corresponding to the module to obtain the comprehensive storage resource occupancy value; S18, a reference occupancy value sequence is formed from the lookup table resource occupancy value, register resource occupancy value and storage resource occupancy value corresponding to this module; S19, based on the reference threshold sequence and the reference occupancy value sequence corresponding to each module, the module at the highest module level is divided into several sub-designs.

3. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 2, characterized in that, Step S19 includes the following steps: S191, if the element at each position in the reference occupancy value sequence corresponding to the highest module level is less than or equal to the element at the corresponding position in the reference threshold sequence, then the module at the highest module level is used as a sub-design; otherwise, a module set is formed from the various modules. S192, Select any module with the lowest module level from the module set as the target module; S193, use the module level of the target module as the level identifier i; S194, if the element at each position in the reference occupancy value sequence corresponding to the target module is less than or equal to the element at the corresponding position in the reference threshold sequence, the module with module level i+1 to which the target module belongs is used as a temporary module. S195, if the element at each position in the reference occupancy value sequence corresponding to the temporary module is less than or equal to the element at the corresponding position in the reference threshold sequence, then the temporary module is taken as the target module, and the process returns to step S193; otherwise, the target module is taken as a sub-design, and the target module and its contained modules are removed from the module set, and the process returns to step S192, until the module set contains only the module at the highest module level.

4. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 1, characterized in that, The preset constraint set includes a first constraint subset, a second constraint subset, and a third constraint subset. Each object corresponds to attribute information. Step S2 includes the following steps: S21, for any object in the sub-design, if the attribute information corresponding to the object satisfies the first constraint subset, then it is determined that the object is suitable for the first memory type; S22, if the attribute information corresponding to the object satisfies the second constraint subset, then it is determined that the object is suitable for the second memory type; S23, if the attribute information corresponding to the object satisfies the third constraint subset, then it is determined that the object is suitable for the third memory type; S24. If the object is only applicable to one of the first memory type, the second memory type, and the third memory type, then the reference category corresponding to the object is determined to be a fixed category; otherwise, the reference category corresponding to the object is determined to be a variable category.

5. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 4, characterized in that, The second resource threshold sequence includes a fourth storage resource threshold, a fifth storage resource threshold, and a sixth storage resource threshold. Step S3 includes the following steps: S31, set each object with a reference category of fixed category and applicable to the first memory type as the first memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the first memory type, divide the sum by the fourth storage resource threshold and round it to obtain the first initial chip number; S32, set each object with a reference category of fixed category and applicable to the second memory type as the second memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the second memory type, divide the sum by the fifth storage resource threshold and round it to obtain the second initial chip number; S33, set each object with a reference category of fixed category and applicable to the third memory type as the third memory type, add up the target storage resource occupancy corresponding to each object with a reference category of fixed category and applicable to the third memory type, divide the sum by the sixth storage resource threshold and round it to obtain the third initial chip quantity; S34, the maximum value among the first initial chip quantity, the second initial chip quantity, and the third initial chip quantity is used as the reference chip quantity; S35, based on the number of reference chips, the reference category corresponding to each object in the sub-design, the target storage resource usage, the first target conversion rate, and the second target conversion rate, determine the target memory type corresponding to each object in the sub-design.

6. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 5, step S35 includes the following steps: S351, the number of reference chips is used as the number of temporary chips; S352, set the memory type of each object in the subdesign whose reference category is a variable category to the first memory type; S353, add up the target storage resource occupancy of each object in the sub-design whose memory type is the first memory type and whose reference category is a variable category, divide the sum by the fourth storage resource threshold and round it, and add the rounding result to the first initial chip number to obtain the first intermediate chip number. S354, if the number of the first intermediate chips is less than or equal to the number of temporary chips, the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, each object in the sub-design with a reference category of variable category and applicable to the second memory type is sorted according to the corresponding first target conversion rate to obtain the first sequence of objects to be converted. S355, the j-th object in the first sequence of objects to be converted is set as the second memory type. The target storage resource occupancy corresponding to the j-th object is divided by the fourth storage resource threshold and rounded. The difference between the number of the first intermediate chips and the rounding result is used to update the number of the first intermediate chips. The product of the target storage resource occupancy corresponding to the j-th object and the corresponding first target conversion rate is divided by the fifth storage resource threshold. The division result is rounded and added to the number of the second intermediate chips to update the number of the second intermediate chips. j is initially set to 1, and the number of the second intermediate chips is initially set to the number of the second initial chips; S356, if the number of the first intermediate chips and the number of the second intermediate chips are both less than or equal to the number of temporary chips, then the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, update j=j+1 and return to step S355 until the number of the first intermediate chips and the number of the second intermediate chips are both less than or equal to the number of temporary chips, or the number of the second intermediate chips is greater than the number of temporary chips. When the number of the second intermediate chips is greater than the number of temporary chips, set the j-th object as the first memory type and execute step S357. S357, sort each object in the sub-design whose reference category is variable category, which is applicable to the third memory type and whose memory type has not been converted according to its corresponding second target conversion rate to obtain the second sequence of objects to be converted; S358, set the kth object in the second sequence of objects to be converted as the third memory type, divide the target storage resource occupancy corresponding to the kth object by the fourth storage resource threshold and round it, update the first intermediate chip quantity with the difference between the first intermediate chip quantity and the rounding result, divide the product of the target storage resource occupancy corresponding to the kth object and the corresponding second target conversion rate by the sixth storage resource threshold, round the division result and add it to the third intermediate chip quantity to update the third intermediate chip quantity, where k is initially set to 1 and the third intermediate chip quantity is initially the third initial chip quantity; S359, if the number of the first intermediate chips and the number of the third intermediate chips are both less than or equal to the number of temporary chips, then the memory type corresponding to each object in the current sub-design is used as the target memory type corresponding to each object; otherwise, update k=k+1 and return to step S358 until the number of the first intermediate chips and the number of the third intermediate chips are both less than or equal to the number of temporary chips, or the number of the third intermediate chips is greater than the number of temporary chips. When the number of the third intermediate chips is greater than the number of temporary chips, update the number of temporary chips with a preset step size and return to step S352 until the target memory type corresponding to each object in the sub-design is determined.

7. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 4, characterized in that, The first memory type is BRAM, the second memory type is URAM, and the third memory type is LUTRAM.

8. The method for dynamically determining memory type for prototype verification and hardware simulation according to claim 1, characterized in that, The method for dynamically determining memory type for prototype verification and hardware simulation also includes: S4. Based on the target memory type corresponding to each object in each sub-design, the user netlist is instantiated by deduplication.

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